};
/* global register indices */
-static TCGv cpu_env, current_tc_gprs, cpu_T[2];
-
-/* The code generator doesn't like lots of temporaries, so maintain our own
- cache for reuse within a function. */
-#define MAX_TEMPS 4
-static int num_temps;
-static TCGv temps[MAX_TEMPS];
-
-/* Allocate a temporary variable. */
-static TCGv new_tmp(void)
-{
- TCGv tmp;
- if (num_temps == MAX_TEMPS)
- abort();
-
- if (GET_TCGV(temps[num_temps]))
- return temps[num_temps++];
-
- tmp = tcg_temp_new(TCG_TYPE_I32);
- temps[num_temps++] = tmp;
- return tmp;
-}
-
-/* Release a temporary variable. */
-static void dead_tmp(TCGv tmp)
-{
- int i;
- num_temps--;
- i = num_temps;
- if (GET_TCGV(temps[i]) == GET_TCGV(tmp))
- return;
-
- /* Shuffle this temp to the last slot. */
- while (GET_TCGV(temps[i]) != GET_TCGV(tmp))
- i--;
- while (i < num_temps) {
- temps[i] = temps[i + 1];
- i++;
- }
- temps[i] = tmp;
-}
+static TCGv cpu_env, current_tc_gprs, current_tc_hi, cpu_T[2];
typedef struct DisasContext {
struct TranslationBlock *tb;
tcg_gen_st_tl(t, current_tc_gprs, sizeof(target_ulong) * reg);
}
+/* Moves to/from HI and LO registers. */
+static inline void gen_load_LO (TCGv t, int reg)
+{
+ tcg_gen_ld_tl(t, current_tc_hi,
+ offsetof(CPUState, LO)
+ - offsetof(CPUState, HI)
+ + sizeof(target_ulong) * reg);
+}
+
+static inline void gen_store_LO (TCGv t, int reg)
+{
+ tcg_gen_st_tl(t, current_tc_hi,
+ offsetof(CPUState, LO)
+ - offsetof(CPUState, HI)
+ + sizeof(target_ulong) * reg);
+}
+
+static inline void gen_load_HI (TCGv t, int reg)
+{
+ tcg_gen_ld_tl(t, current_tc_hi, sizeof(target_ulong) * reg);
+}
+
+static inline void gen_store_HI (TCGv t, int reg)
+{
+ tcg_gen_st_tl(t, current_tc_hi, sizeof(target_ulong) * reg);
+}
+
/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr (TCGv t, int reg)
{
if (reg == 0)
tcg_gen_movi_tl(t, 0);
else {
- TCGv r_tmp = new_tmp();
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
tcg_gen_ld_tl(t, r_tmp, sizeof(target_ulong) * reg);
- dead_tmp(r_tmp);
+ tcg_temp_free(r_tmp);
}
}
static inline void gen_store_srsgpr (TCGv t, int reg)
{
if (reg != 0) {
- TCGv r_tmp = new_tmp();
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
tcg_gen_st_tl(t, r_tmp, sizeof(target_ulong) * reg);
- dead_tmp(r_tmp);
+ tcg_temp_free(r_tmp);
}
}
int l1 = gen_new_label(); \
int l2 = gen_new_label(); \
\
- tcg_gen_brcond_tl(cond, cpu_T[0], tcg_const_tl(val), l1); \
+ tcg_gen_brcondi_tl(cond, cpu_T[0], val, l1); \
tcg_gen_movi_tl(cpu_T[0], 0); \
tcg_gen_br(l2); \
gen_set_label(l1); \
int l1 = gen_new_label(); \
int l2 = gen_new_label(); \
\
- tcg_gen_brcond_tl(cond, cpu_T[0], tcg_const_tl(0), l1); \
+ tcg_gen_brcondi_tl(cond, cpu_T[0], 0, l1); \
tcg_gen_movi_tl(cpu_T[0], 0); \
tcg_gen_br(l2); \
gen_set_label(l1); \
static inline void gen_save_pc(target_ulong pc)
{
TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tc_off = new_tmp();
- TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tc_off = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tc_off_ptr = tcg_temp_new(TCG_TYPE_PTR);
TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_movi_tl(r_tmp, pc);
tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
- tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
- tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
+ tcg_gen_ext_i32_ptr(r_tc_off_ptr, r_tc_off);
+ tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
- dead_tmp(r_tc_off);
+ tcg_temp_free(r_tc_off);
+ tcg_temp_free(r_tc_off_tl);
+ tcg_temp_free(r_ptr);
+ tcg_temp_free(r_tmp);
}
static inline void gen_breg_pc(void)
{
TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tc_off = new_tmp();
- TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tc_off = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tc_off_ptr = tcg_temp_new(TCG_TYPE_PTR);
TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
- tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
- tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
+ tcg_gen_ext_i32_ptr(r_tc_off_ptr, r_tc_off);
+ tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
- dead_tmp(r_tc_off);
+ tcg_temp_free(r_tc_off);
+ tcg_temp_free(r_tc_off_tl);
+ tcg_temp_free(r_ptr);
+ tcg_temp_free(r_tmp);
}
static inline void gen_save_btarget(target_ulong btarget)
with Status_UX = 0 should be casted to 32-bit and sign extended.
See the MIPS64 PRA manual, section 4.10. */
{
- TCGv r_tmp = new_tmp();
int l1 = gen_new_label();
- tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
- tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
- tcg_gen_brcond_i32(TCG_COND_NE, r_tmp, tcg_const_i32(MIPS_HFLAG_UM), l1);
- tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
- tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
- tcg_gen_brcond_i32(TCG_COND_NE, r_tmp, tcg_const_i32(0), l1);
+ {
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
+ tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
+ tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
+ }
+ {
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
+ tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
+ tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
+ }
tcg_gen_ext32s_i64(cpu_T[0], cpu_T[0]);
gen_set_label(l1);
- dead_tmp(r_tmp);
}
#endif
}
int l3 = gen_new_label(); \
\
tcg_gen_andi_tl(r_tmp, cpu_T[0], almask); \
- tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp, tcg_const_tl(0), l1); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
- generate_exception(ctx, EXCP_AdES); \
+ generate_exception(ctx, EXCP_AdES); \
gen_set_label(l1); \
tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2); \
tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp1, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp1, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
/* rotr is decoded as srl on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
if (uimm != 0) {
- TCGv r_tmp1 = new_tmp();
- TCGv r_tmp2 = new_tmp();
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
tcg_gen_movi_i32(r_tmp2, 0x20);
tcg_gen_shl_i32(r_tmp2, r_tmp1, r_tmp2);
tcg_gen_shri_i32(r_tmp1, r_tmp1, uimm);
tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp2);
- tcg_gen_ext_i32_tl(r_tmp1, cpu_T[0]);
- dead_tmp(r_tmp1);
- dead_tmp(r_tmp2);
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
+ tcg_temp_free(r_tmp1);
+ tcg_temp_free(r_tmp2);
}
opn = "rotr";
} else {
tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp1, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp1, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
/* operands of different sign, first operand and result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp1, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
/* operands of same sign, result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp1, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
/* operands of different sign, first operand and result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
{
int l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
gen_store_gpr(cpu_T[0], rd);
gen_set_label(l1);
}
{
int l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], 0, l1);
gen_store_gpr(cpu_T[0], rd);
gen_set_label(l1);
}
int l2 = gen_new_label();
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
- tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
{
- TCGv r_tmp1 = new_tmp();
- TCGv r_tmp2 = new_tmp();
- TCGv r_tmp3 = new_tmp();
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
tcg_gen_shl_i32(r_tmp3, r_tmp2, r_tmp3);
tcg_gen_shr_i32(r_tmp1, r_tmp2, r_tmp1);
tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp3);
- tcg_gen_ext_i32_tl(r_tmp1, cpu_T[0]);
- dead_tmp(r_tmp1);
- dead_tmp(r_tmp2);
- dead_tmp(r_tmp3);
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
+ tcg_temp_free(r_tmp1);
+ tcg_temp_free(r_tmp2);
+ tcg_temp_free(r_tmp3);
tcg_gen_br(l2);
}
gen_set_label(l1);
int l2 = gen_new_label();
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
- tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
}
switch (opc) {
case OPC_MFHI:
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, HI[0]));
+ gen_load_HI(cpu_T[0], 0);
gen_store_gpr(cpu_T[0], reg);
opn = "mfhi";
break;
case OPC_MFLO:
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, LO[0]));
+ gen_load_LO(cpu_T[0], 0);
gen_store_gpr(cpu_T[0], reg);
opn = "mflo";
break;
case OPC_MTHI:
gen_load_gpr(cpu_T[0], reg);
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, HI[0]));
+ gen_store_HI(cpu_T[0], 0);
opn = "mthi";
break;
case OPC_MTLO:
gen_load_gpr(cpu_T[0], reg);
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, LO[0]));
+ gen_store_LO(cpu_T[0], 0);
opn = "mtlo";
break;
default:
{
int l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), l1);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
{
- TCGv r_tmp1 = new_tmp();
- TCGv r_tmp2 = new_tmp();
- TCGv r_tmp3 = new_tmp();
- TCGv r_tc_off = new_tmp();
- TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
-
- tcg_gen_ext_i32_tl(r_tmp1, cpu_T[0]);
- tcg_gen_ext_i32_tl(r_tmp2, cpu_T[1]);
- tcg_gen_div_i32(r_tmp3, r_tmp1, r_tmp2);
- tcg_gen_rem_i32(r_tmp1, r_tmp1, r_tmp2);
- tcg_gen_trunc_tl_i32(cpu_T[0], r_tmp3);
- tcg_gen_trunc_tl_i32(cpu_T[1], r_tmp1);
- dead_tmp(r_tmp1);
- dead_tmp(r_tmp2);
- dead_tmp(r_tmp3);
- tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
- tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
- tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
- tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
- tcg_gen_st_tl(cpu_T[0], r_ptr, offsetof(CPUState, LO));
- tcg_gen_st_tl(cpu_T[1], r_ptr, offsetof(CPUState, HI));
- dead_tmp(r_tc_off);
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
+
+ tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
+ tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
+ tcg_gen_div_i64(r_tmp3, r_tmp1, r_tmp2);
+ tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
+ tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ gen_store_LO(cpu_T[0], 0);
+ gen_store_HI(cpu_T[1], 0);
}
gen_set_label(l1);
}
{
int l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), l1);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
{
- TCGv r_tmp1 = new_tmp();
- TCGv r_tmp2 = new_tmp();
- TCGv r_tmp3 = new_tmp();
- TCGv r_tc_off = new_tmp();
- TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
-
- tcg_gen_ext_i32_tl(r_tmp1, cpu_T[0]);
- tcg_gen_ext_i32_tl(r_tmp2, cpu_T[1]);
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
tcg_gen_divu_i32(r_tmp3, r_tmp1, r_tmp2);
tcg_gen_remu_i32(r_tmp1, r_tmp1, r_tmp2);
- tcg_gen_trunc_tl_i32(cpu_T[0], r_tmp3);
- tcg_gen_trunc_tl_i32(cpu_T[1], r_tmp1);
- dead_tmp(r_tmp1);
- dead_tmp(r_tmp2);
- dead_tmp(r_tmp3);
- tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
- tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
- tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
- tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
- tcg_gen_st_tl(cpu_T[0], r_ptr, offsetof(CPUState, LO));
- tcg_gen_st_tl(cpu_T[1], r_ptr, offsetof(CPUState, HI));
- dead_tmp(r_tc_off);
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp3);
+ tcg_gen_ext_i32_tl(cpu_T[1], r_tmp1);
+ tcg_temp_free(r_tmp1);
+ tcg_temp_free(r_tmp2);
+ tcg_temp_free(r_tmp3);
+ gen_store_LO(cpu_T[0], 0);
+ gen_store_HI(cpu_T[1], 0);
}
gen_set_label(l1);
}
{
int l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
{
- TCGv r_tc_off = new_tmp();
- TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
int l2 = gen_new_label();
- int l3 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], tcg_const_tl(1ULL << 63), l2);
- tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(-1ULL), l2);
- tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_movi_tl(cpu_T[1], 0);
- tcg_gen_br(l3);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], -1LL << 63, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1LL, l2);
+ {
+ tcg_gen_movi_tl(cpu_T[1], 0);
+ gen_store_LO(cpu_T[0], 0);
+ gen_store_HI(cpu_T[1], 0);
+ tcg_gen_br(l1);
+ }
gen_set_label(l2);
- tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_rem_i64(cpu_T[1], cpu_T[0], cpu_T[1]);
- gen_set_label(l3);
-
- tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
- tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
- tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
- tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
- tcg_gen_st_tl(cpu_T[0], r_ptr, offsetof(CPUState, LO));
- tcg_gen_st_tl(cpu_T[1], r_ptr, offsetof(CPUState, HI));
- dead_tmp(r_tc_off);
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+
+ tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]);
+ tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]);
+ gen_store_LO(r_tmp1, 0);
+ gen_store_HI(r_tmp2, 0);
+ }
}
gen_set_label(l1);
}
{
int l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tc_off = new_tmp();
- TCGv r_tc_off_tl = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_divu_i64(r_tmp1, cpu_T[0], cpu_T[1]);
tcg_gen_remu_i64(r_tmp2, cpu_T[0], cpu_T[1]);
- tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
- tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
- tcg_gen_ext_i32_ptr(r_tc_off_tl, r_tc_off);
- tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_tl);
- tcg_gen_st_tl(r_tmp1, r_ptr, offsetof(CPUState, LO));
- tcg_gen_st_tl(r_tmp2, r_ptr, offsetof(CPUState, HI));
- dead_tmp(r_tc_off);
+ gen_store_LO(r_tmp1, 0);
+ gen_store_HI(r_tmp2, 0);
}
gen_set_label(l1);
}
static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp64 = tcg_temp_new(TCG_TYPE_I64);
if (sel != 0)
check_insn(env, ctx, ISA_MIPS32);
case 0:
switch (sel) {
case 0:
- gen_op_mfc0_index();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Index";
break;
case 1:
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpecontrol();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_yqmask();
+ tcg_gen_ld_i64(r_tmp64, cpu_env, offsetof(CPUState, CP0_YQMask));
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeschedule();
+ tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeschefback();
+ tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeopt();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- gen_op_mfc0_entrylo0();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EntryLo0";
break;
case 1:
case 3:
switch (sel) {
case 0:
- gen_op_mfc0_entrylo1();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- gen_op_mfc0_context();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "Context";
break;
case 1:
case 5:
switch (sel) {
case 0:
- gen_op_mfc0_pagemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_pagegrain();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_op_mfc0_wired();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf4();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_hwrena();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "HWREna";
break;
default:
case 8:
switch (sel) {
case 0:
- gen_op_mfc0_badvaddr();
- rn = "BadVaddr";
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ rn = "BadVAddr";
break;
default:
goto die;
case 10:
switch (sel) {
case 0:
- gen_op_mfc0_entryhi();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_op_mfc0_compare();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_op_mfc0_status();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_intctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsmap();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSMap";
break;
default:
case 13:
switch (sel) {
case 0:
- gen_op_mfc0_cause();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Cause";
break;
default:
case 14:
switch (sel) {
case 0:
- gen_op_mfc0_epc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EPC";
break;
default:
case 15:
switch (sel) {
case 0:
- gen_op_mfc0_prid();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_ebase();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_op_mfc0_config0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config";
break;
case 1:
- gen_op_mfc0_config1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config1";
break;
case 2:
- gen_op_mfc0_config2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config2";
break;
case 3:
- gen_op_mfc0_config3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config3";
break;
/* 4,5 are reserved */
/* 6,7 are implementation dependent */
case 6:
- gen_op_mfc0_config6();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config6";
break;
case 7:
- gen_op_mfc0_config7();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config7";
break;
default:
case 0:
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- gen_op_mfc0_xcontext();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "XContext";
break;
#endif
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mfc0_framemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Framemask";
break;
default:
case 24:
switch (sel) {
case 0:
- gen_op_mfc0_depc(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_op_mfc0_performance0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Performance0";
break;
case 1:
case 2:
case 4:
case 6:
- gen_op_mfc0_taglo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datalo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_op_mfc0_taghi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datahi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- gen_op_mfc0_errorepc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "ErrorEPC";
break;
default:
case 31:
switch (sel) {
case 0:
- gen_op_mfc0_desave(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DESAVE";
break;
default:
break;
case 8:
/* ignored */
- rn = "BadVaddr";
+ rn = "BadVAddr";
break;
case 9:
switch (sel) {
static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
if (sel != 0)
check_insn(env, ctx, ISA_MIPS64);
case 0:
switch (sel) {
case 0:
- gen_op_mfc0_index();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Index";
break;
case 1:
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpecontrol();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_op_dmfc0_yqmask();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_op_dmfc0_vpeschedule();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_op_dmfc0_vpeschefback();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeopt();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- gen_op_dmfc0_entrylo0();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
rn = "EntryLo0";
break;
case 1:
case 3:
switch (sel) {
case 0:
- gen_op_dmfc0_entrylo1();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- gen_op_dmfc0_context();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
rn = "Context";
break;
case 1:
case 5:
switch (sel) {
case 0:
- gen_op_mfc0_pagemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_pagegrain();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_op_mfc0_wired();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf4();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_hwrena();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "HWREna";
break;
default:
case 8:
switch (sel) {
case 0:
- gen_op_dmfc0_badvaddr();
- rn = "BadVaddr";
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ rn = "BadVAddr";
break;
default:
goto die;
case 10:
switch (sel) {
case 0:
- gen_op_dmfc0_entryhi();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_op_mfc0_compare();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_op_mfc0_status();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_intctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsmap();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSMap";
break;
default:
case 13:
switch (sel) {
case 0:
- gen_op_mfc0_cause();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Cause";
break;
default:
case 14:
switch (sel) {
case 0:
- gen_op_dmfc0_epc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
rn = "EPC";
break;
default:
case 15:
switch (sel) {
case 0:
- gen_op_mfc0_prid();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_ebase();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_op_mfc0_config0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config";
break;
case 1:
- gen_op_mfc0_config1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config1";
break;
case 2:
- gen_op_mfc0_config2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config2";
break;
case 3:
- gen_op_mfc0_config3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config3";
break;
/* 6,7 are implementation dependent */
+ case 6:
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
+ rn = "Config6";
+ break;
+ case 7:
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
+ rn = "Config7";
+ break;
default:
goto die;
}
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- gen_op_dmfc0_xcontext();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
rn = "XContext";
break;
default:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mfc0_framemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Framemask";
break;
default:
case 24:
switch (sel) {
case 0:
- gen_op_dmfc0_depc(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_op_mfc0_performance0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Performance0";
break;
case 1:
case 2:
case 4:
case 6:
- gen_op_mfc0_taglo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datalo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_op_mfc0_taghi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datahi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- gen_op_dmfc0_errorepc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
case 31:
switch (sel) {
case 0:
- gen_op_mfc0_desave(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DESAVE";
break;
default:
break;
case 8:
/* ignored */
- rn = "BadVaddr";
+ rn = "BadVAddr";
break;
case 9:
switch (sel) {
static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
{
+ int l1 = gen_new_label();
uint32_t ccbit;
+ TCGCond cond;
- gen_load_gpr(cpu_T[0], rd);
- gen_load_gpr(cpu_T[1], rs);
- if (cc) {
+ if (cc)
ccbit = 1 << (24 + cc);
- } else
+ else
ccbit = 1 << 23;
- if (!tf)
- gen_op_movf(ccbit);
+ if (tf)
+ cond = TCG_COND_EQ;
else
- gen_op_movt(ccbit);
+ cond = TCG_COND_NE;
+
+ gen_load_gpr(cpu_T[0], rd);
+ gen_load_gpr(cpu_T[1], rs);
+ {
+ TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
+ tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
+ tcg_temp_free(r_ptr);
+ tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
+ tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
+ }
+ tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
+
+ gen_set_label(l1);
gen_store_gpr(cpu_T[0], rd);
}
}
GEN_MOVCF(d);
GEN_MOVCF(s);
-GEN_MOVCF(ps);
#undef GEN_MOVCF
static void gen_farith (DisasContext *ctx, uint32_t op1,
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
GEN_LOAD_FREG_FTN(WTH2, fd);
- gen_movcf_ps(ctx, (ft >> 2) & 0x7, ft & 0x1);
+ if (ft & 0x1)
+ gen_op_float_movt_ps ((ft >> 2) & 0x7);
+ else
+ gen_op_float_movf_ps ((ft >> 2) & 0x7);
GEN_STORE_FTN_FREG(fd, WT2);
GEN_STORE_FTN_FREG(fd, WTH2);
opn = "movcf.ps";
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
- tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
int l1 = gen_new_label();
tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
- tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_tl(0), l1);
+ tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
gen_goto_tb(ctx, 0, ctx->btarget);
if (search_pc && loglevel)
fprintf (logfile, "search pc %d\n", search_pc);
- num_temps = 0;
- memset(temps, 0, sizeof(temps));
-
- num_temps = 0;
- memset(temps, 0, sizeof(temps));
-
pc_start = tb->pc;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
ctx.pc = pc_start;
}
ctx.opcode = ldl_code(ctx.pc);
decode_opc(env, &ctx);
- if (num_temps) {
- fprintf(stderr,
- "Internal resource leak before " TARGET_FMT_lx "\n",
- ctx.pc);
- num_temps = 0;
- }
ctx.pc += 4;
if (env->singlestep_enabled)
TCG_AREG0,
offsetof(CPUState, current_tc_gprs),
"current_tc_gprs");
+ current_tc_hi = tcg_global_mem_new(TCG_TYPE_PTR,
+ TCG_AREG0,
+ offsetof(CPUState, current_tc_hi),
+ "current_tc_hi");
#if TARGET_LONG_BITS > HOST_LONG_BITS
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, t0), "T0");
projects / qemu.git / blobdiff