}
}
else {
-#if 0
switch(offs) {
+#if 0
case 0x0c:
ret = s->dr;
break;
case 0x10:
ret = 0;
break;
+#endif
case 0x1c:
- ret = s->sptr;
- break;
+ s->sptr = val & 0x8f;
+ return;
}
-#endif
}
fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
}
}
else {
-#if 0
switch(offs) {
+#if 0
case 0x0c:
ret = s->dr;
break;
case 0x14:
ret = s->rx_fifo[0];
break;
+#endif
case 0x1c:
ret = s->sptr;
break;
}
-#endif
}
#ifdef DEBUG_SERIAL
printf("sh_serial: read offs=0x%02x val=0x%x\n",
int s_io_memory;
s = qemu_mallocz(sizeof(sh_serial_state));
- if (!s)
- return;
s->feat = feat;
s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
sh_serial_writefn, s);
- cpu_register_physical_memory(base, 0x28, s_io_memory);
+ cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
+ cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
s->chr = chr;