#include <hw/qdev.h>
#include "qemu/bitops.h"
+#include "exec/address-spaces.h"
#include "cpu.h"
#include "ioinst.h"
#include "css.h"
#include "trace.h"
+#include "hw/s390x/s390_flic.h"
typedef struct CrwContainer {
CRW crw;
ChpInfo chpids[MAX_CHPID + 1];
} CssImage;
+typedef struct IoAdapter {
+ uint32_t id;
+ uint8_t type;
+ uint8_t isc;
+ QTAILQ_ENTRY(IoAdapter) sibling;
+} IoAdapter;
+
typedef struct ChannelSubSys {
QTAILQ_HEAD(, CrwContainer) pending_crws;
bool do_crw_mchk;
uint64_t chnmon_area;
CssImage *css[MAX_CSSID + 1];
uint8_t default_cssid;
+ QTAILQ_HEAD(, IoAdapter) io_adapters;
} ChannelSubSys;
static ChannelSubSys *channel_subsys;
return 0;
}
-static uint16_t css_build_subchannel_id(SubchDev *sch)
+int css_register_io_adapter(uint8_t type, uint8_t isc, bool swap,
+ bool maskable, uint32_t *id)
+{
+ IoAdapter *adapter;
+ bool found = false;
+ int ret;
+ S390FLICState *fs = s390_get_flic();
+ S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
+
+ *id = 0;
+ QTAILQ_FOREACH(adapter, &channel_subsys->io_adapters, sibling) {
+ if ((adapter->type == type) && (adapter->isc == isc)) {
+ *id = adapter->id;
+ found = true;
+ ret = 0;
+ break;
+ }
+ if (adapter->id >= *id) {
+ *id = adapter->id + 1;
+ }
+ }
+ if (found) {
+ goto out;
+ }
+ adapter = g_new0(IoAdapter, 1);
+ ret = fsc->register_io_adapter(fs, *id, isc, swap, maskable);
+ if (ret == 0) {
+ adapter->id = *id;
+ adapter->isc = isc;
+ adapter->type = type;
+ QTAILQ_INSERT_TAIL(&channel_subsys->io_adapters, adapter, sibling);
+ } else {
+ g_free(adapter);
+ fprintf(stderr, "Unexpected error %d when registering adapter %d\n",
+ ret, *id);
+ }
+out:
+ return ret;
+}
+
+uint16_t css_build_subchannel_id(SubchDev *sch)
{
if (channel_subsys->max_cssid > 0) {
return (sch->cssid << 8) | (1 << 3) | (sch->ssid << 1) | 1;
static void css_inject_io_interrupt(SubchDev *sch)
{
- S390CPU *cpu = s390_cpu_addr2state(0);
uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
sch->curr_status.pmcw.intparm, isc, "");
- s390_io_interrupt(cpu,
- css_build_subchannel_id(sch),
+ s390_io_interrupt(css_build_subchannel_id(sch),
sch->schid,
sch->curr_status.pmcw.intparm,
- (0x80 >> isc) << 24);
+ isc << 27);
}
void css_conditional_io_interrupt(SubchDev *sch)
* with alert status.
*/
if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
- S390CPU *cpu = s390_cpu_addr2state(0);
uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
sch->curr_status.scsw.ctrl |=
SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
/* Inject an I/O interrupt. */
- s390_io_interrupt(cpu,
- css_build_subchannel_id(sch),
+ s390_io_interrupt(css_build_subchannel_id(sch),
sch->schid,
sch->curr_status.pmcw.intparm,
- (0x80 >> isc) << 24);
+ isc << 27);
}
}
+void css_adapter_interrupt(uint8_t isc)
+{
+ uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
+
+ trace_css_adapter_interrupt(isc);
+ s390_io_interrupt(0, 0, 0, io_int_word);
+}
+
static void sch_handle_clear_func(SubchDev *sch)
{
PMCW *p = &sch->curr_status.pmcw;
/* Path management: In our simple css, we always choose the only path. */
path = 0x80;
- /* Reset values prior to 'issueing the clear signal'. */
+ /* Reset values prior to 'issuing the clear signal'. */
p->lpum = 0;
p->pom = 0xff;
s->flags &= ~SCSW_FLAGS_MASK_PNO;
/* We always 'attempt to issue the clear signal', and we always succeed. */
- sch->orb = NULL;
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
s->ctrl &= ~SCSW_ACTL_CLEAR_PEND;
PMCW *p = &sch->curr_status.pmcw;
SCSW *s = &sch->curr_status.scsw;
+ hwaddr curr_ccw = sch->channel_prog;
int path;
/* Path management: In our simple css, we always choose the only path. */
path = 0x80;
/* We always 'attempt to issue the halt signal', and we always succeed. */
- sch->orb = NULL;
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
s->ctrl &= ~SCSW_ACTL_HALT_PEND;
(s->ctrl & SCSW_ACTL_SUSP))) {
s->dstat = SCSW_DSTAT_DEVICE_END;
}
+ if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
+ (s->ctrl & SCSW_ACTL_SUSP)) {
+ s->cpa = curr_ccw + 8;
+ }
s->cstat = 0;
p->lpum = path;
}
}
-static CCW1 copy_ccw_from_guest(hwaddr addr)
+static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
{
- CCW1 tmp;
+ CCW0 tmp0;
+ CCW1 tmp1;
CCW1 ret;
- cpu_physical_memory_read(addr, &tmp, sizeof(tmp));
- ret.cmd_code = tmp.cmd_code;
- ret.flags = tmp.flags;
- ret.count = be16_to_cpu(tmp.count);
- ret.cda = be32_to_cpu(tmp.cda);
-
+ if (fmt1) {
+ cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
+ ret.cmd_code = tmp1.cmd_code;
+ ret.flags = tmp1.flags;
+ ret.count = be16_to_cpu(tmp1.count);
+ ret.cda = be32_to_cpu(tmp1.cda);
+ } else {
+ cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
+ ret.cmd_code = tmp0.cmd_code;
+ ret.flags = tmp0.flags;
+ ret.count = be16_to_cpu(tmp0.count);
+ ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
+ }
return ret;
}
return -EIO;
}
- ccw = copy_ccw_from_guest(ccw_addr);
+ /* Translate everything to format-1 ccws - the information is the same. */
+ ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
/* Check for invalid command codes. */
if ((ccw.cmd_code & 0x0f) == 0) {
check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC));
+ if (!ccw.cda) {
+ if (sch->ccw_no_data_cnt == 255) {
+ return -EINVAL;
+ }
+ sch->ccw_no_data_cnt++;
+ }
+
/* Look at the command. */
switch (ccw.cmd_code) {
case CCW_CMD_NOOP:
return ret;
}
-static void sch_handle_start_func(SubchDev *sch)
+static void sch_handle_start_func(SubchDev *sch, ORB *orb)
{
PMCW *p = &sch->curr_status.pmcw;
SCSW *s = &sch->curr_status.scsw;
- ORB *orb = sch->orb;
int path;
int ret;
if (!(s->ctrl & SCSW_ACTL_SUSP)) {
/* Look at the orb and try to execute the channel program. */
+ assert(orb != NULL); /* resume does not pass an orb */
p->intparm = orb->intparm;
if (!(orb->lpm & path)) {
/* Generate a deferred cc 3 condition. */
s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND);
return;
}
+ sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT);
+ sch->ccw_no_data_cnt = 0;
} else {
s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND);
}
s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
SCSW_STCTL_STATUS_PEND;
s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END;
+ s->cpa = sch->channel_prog + 8;
break;
case -ENOSYS:
/* unsupported command, generate unit check (command reject) */
s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
+ s->cpa = sch->channel_prog + 8;
break;
case -EFAULT:
/* memory problem, generate channel data check */
s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
+ s->cpa = sch->channel_prog + 8;
break;
case -EBUSY:
/* subchannel busy, generate deferred cc 1 */
s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
+ s->cpa = sch->channel_prog + 8;
break;
}
} while (ret == -EAGAIN);
* read/writes) asynchronous later on if we start supporting more than
* our current very simple devices.
*/
-static void do_subchannel_work(SubchDev *sch)
+static void do_subchannel_work(SubchDev *sch, ORB *orb)
{
SCSW *s = &sch->curr_status.scsw;
} else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
sch_handle_halt_func(sch);
} else if (s->ctrl & SCSW_FCTL_START_FUNC) {
- sch_handle_start_func(sch);
+ sch_handle_start_func(sch, orb);
} else {
/* Cannot happen. */
return;
}
}
-int css_do_msch(SubchDev *sch, SCHIB *orig_schib)
+int css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
{
SCSW *s = &sch->curr_status.scsw;
PMCW *p = &sch->curr_status.pmcw;
+ uint16_t oldflags;
int ret;
SCHIB schib;
copy_schib_from_guest(&schib, orig_schib);
/* Only update the program-modifiable fields. */
p->intparm = schib.pmcw.intparm;
+ oldflags = p->flags;
p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
PMCW_FLAGS_MASK_MP);
(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
sch->curr_status.mba = schib.mba;
+ /* Has the channel been disabled? */
+ if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0
+ && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) {
+ sch->disable_cb(sch);
+ }
+
ret = 0;
out:
SCSW_ACTL_SUSP);
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
- sch->orb = NULL;
s->dstat = 0;
s->cstat = 0;
ret = 0;
s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_FCTL_CLEAR_FUNC;
- do_subchannel_work(sch);
+ do_subchannel_work(sch, NULL);
ret = 0;
out:
}
s->ctrl |= SCSW_ACTL_HALT_PEND;
- do_subchannel_work(sch);
+ do_subchannel_work(sch, NULL);
ret = 0;
out:
/* Format 1, per-subchannel area. */
uint32_t count;
- count = ldl_phys(sch->curr_status.mba);
+ count = address_space_ldl(&address_space_memory,
+ sch->curr_status.mba,
+ MEMTXATTRS_UNSPECIFIED,
+ NULL);
count++;
- stl_phys(sch->curr_status.mba, count);
+ address_space_stl(&address_space_memory, sch->curr_status.mba, count,
+ MEMTXATTRS_UNSPECIFIED, NULL);
} else {
/* Format 0, global area. */
uint32_t offset;
uint16_t count;
offset = sch->curr_status.pmcw.mbi << 5;
- count = lduw_phys(channel_subsys->chnmon_area + offset);
+ count = address_space_lduw(&address_space_memory,
+ channel_subsys->chnmon_area + offset,
+ MEMTXATTRS_UNSPECIFIED,
+ NULL);
count++;
- stw_phys(channel_subsys->chnmon_area + offset, count);
+ address_space_stw(&address_space_memory,
+ channel_subsys->chnmon_area + offset, count,
+ MEMTXATTRS_UNSPECIFIED, NULL);
}
}
if (channel_subsys->chnmon_active) {
css_update_chnmon(sch);
}
- sch->orb = orb;
sch->channel_prog = orb->cpa;
/* Trigger the start function. */
s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND);
s->flags &= ~SCSW_FLAGS_MASK_PNO;
- do_subchannel_work(sch);
+ do_subchannel_work(sch, orb);
ret = 0;
out:
return ret;
}
-static void copy_irb_to_guest(IRB *dest, const IRB *src)
+static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw,
+ int *irb_len)
{
int i;
+ uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
+ uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
copy_scsw_to_guest(&dest->scsw, &src->scsw);
for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
dest->ecw[i] = cpu_to_be32(src->ecw[i]);
}
- for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
- dest->emw[i] = cpu_to_be32(src->emw[i]);
+ *irb_len = sizeof(*dest) - sizeof(dest->emw);
+
+ /* extended measurements enabled? */
+ if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
+ !(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
+ !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) {
+ return;
+ }
+ /* extended measurements pending? */
+ if (!(stctl & SCSW_STCTL_STATUS_PEND)) {
+ return;
}
+ if ((stctl & SCSW_STCTL_PRIMARY) ||
+ (stctl == SCSW_STCTL_SECONDARY) ||
+ ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) {
+ for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
+ dest->emw[i] = cpu_to_be32(src->emw[i]);
+ }
+ }
+ *irb_len = sizeof(*dest);
}
-int css_do_tsch(SubchDev *sch, IRB *target_irb)
+int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
{
SCSW *s = &sch->curr_status.scsw;
PMCW *p = &sch->curr_status.pmcw;
uint16_t stctl;
- uint16_t fctl;
- uint16_t actl;
IRB irb;
- int ret;
if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) {
- ret = 3;
- goto out;
+ return 3;
}
stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
- fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
- actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
/* Prepare the irb for the guest. */
memset(&irb, 0, sizeof(IRB));
(p->chars & PMCW_CHARS_MASK_CSENSE)) {
irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data));
- irb.esw[1] = 0x02000000 | (sizeof(sch->sense_data) << 8);
+ irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8);
}
}
/* Store the irb to the guest. */
- copy_irb_to_guest(target_irb, &irb);
+ copy_irb_to_guest(target_irb, &irb, p, irb_len);
+
+ return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
+}
+
+void css_do_tsch_update_subch(SubchDev *sch)
+{
+ SCSW *s = &sch->curr_status.scsw;
+ PMCW *p = &sch->curr_status.pmcw;
+ uint16_t stctl;
+ uint16_t fctl;
+ uint16_t actl;
+
+ stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
+ fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
+ actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
/* Clear conditions on subchannel, if applicable. */
if (stctl & SCSW_STCTL_STATUS_PEND) {
memset(sch->sense_data, 0 , sizeof(sch->sense_data));
}
}
-
- ret = ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
-
-out:
- return ret;
}
static void copy_crw_to_guest(CRW *dest, const CRW *src)
return ret;
}
+static void copy_crw_from_guest(CRW *dest, const CRW *src)
+{
+ dest->flags = be16_to_cpu(src->flags);
+ dest->rsid = be16_to_cpu(src->rsid);
+}
+
+void css_undo_stcrw(CRW *crw)
+{
+ CrwContainer *crw_cont;
+
+ crw_cont = g_try_malloc0(sizeof(CrwContainer));
+ if (!crw_cont) {
+ channel_subsys->crws_lost = true;
+ return;
+ }
+ copy_crw_from_guest(&crw_cont->crw, crw);
+
+ QTAILQ_INSERT_HEAD(&channel_subsys->pending_crws, crw_cont, sibling);
+}
+
int css_do_tpi(IOIntCode *int_code, int lowcore)
{
/* No pending interrupts for !KVM. */
}
s->ctrl |= SCSW_ACTL_RESUME_PEND;
- do_subchannel_work(sch);
+ do_subchannel_work(sch, NULL);
ret = 0;
out:
return 0;
}
-bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
+bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid)
{
SubchSet *set;
+ uint8_t real_cssid;
- if (cssid > MAX_CSSID || ssid > MAX_SSID || !channel_subsys->css[cssid] ||
- !channel_subsys->css[cssid]->sch_set[ssid]) {
+ real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid;
+ if (real_cssid > MAX_CSSID || ssid > MAX_SSID ||
+ !channel_subsys->css[real_cssid] ||
+ !channel_subsys->css[real_cssid]->sch_set[ssid]) {
return true;
}
- set = channel_subsys->css[cssid]->sch_set[ssid];
+ set = channel_subsys->css[real_cssid]->sch_set[ssid];
return schid > find_last_bit(set->schids_used,
(MAX_SCHID + 1) / sizeof(unsigned long));
}
QTAILQ_INSERT_TAIL(&channel_subsys->pending_crws, crw_cont, sibling);
if (channel_subsys->do_crw_mchk) {
- S390CPU *cpu = s390_cpu_addr2state(0);
-
channel_subsys->do_crw_mchk = false;
/* Inject crw pending machine check. */
- s390_crw_mchk(cpu);
+ s390_crw_mchk();
}
}
/* TODO */
}
+void css_generate_css_crws(uint8_t cssid)
+{
+ css_queue_crw(CRW_RSC_CSS, 0, 0, cssid);
+}
+
int css_enable_mcsse(void)
{
trace_css_enable_facility("mcsse");
return 0;
}
+void subch_device_save(SubchDev *s, QEMUFile *f)
+{
+ int i;
+
+ qemu_put_byte(f, s->cssid);
+ qemu_put_byte(f, s->ssid);
+ qemu_put_be16(f, s->schid);
+ qemu_put_be16(f, s->devno);
+ qemu_put_byte(f, s->thinint_active);
+ /* SCHIB */
+ /* PMCW */
+ qemu_put_be32(f, s->curr_status.pmcw.intparm);
+ qemu_put_be16(f, s->curr_status.pmcw.flags);
+ qemu_put_be16(f, s->curr_status.pmcw.devno);
+ qemu_put_byte(f, s->curr_status.pmcw.lpm);
+ qemu_put_byte(f, s->curr_status.pmcw.pnom);
+ qemu_put_byte(f, s->curr_status.pmcw.lpum);
+ qemu_put_byte(f, s->curr_status.pmcw.pim);
+ qemu_put_be16(f, s->curr_status.pmcw.mbi);
+ qemu_put_byte(f, s->curr_status.pmcw.pom);
+ qemu_put_byte(f, s->curr_status.pmcw.pam);
+ qemu_put_buffer(f, s->curr_status.pmcw.chpid, 8);
+ qemu_put_be32(f, s->curr_status.pmcw.chars);
+ /* SCSW */
+ qemu_put_be16(f, s->curr_status.scsw.flags);
+ qemu_put_be16(f, s->curr_status.scsw.ctrl);
+ qemu_put_be32(f, s->curr_status.scsw.cpa);
+ qemu_put_byte(f, s->curr_status.scsw.dstat);
+ qemu_put_byte(f, s->curr_status.scsw.cstat);
+ qemu_put_be16(f, s->curr_status.scsw.count);
+ qemu_put_be64(f, s->curr_status.mba);
+ qemu_put_buffer(f, s->curr_status.mda, 4);
+ /* end SCHIB */
+ qemu_put_buffer(f, s->sense_data, 32);
+ qemu_put_be64(f, s->channel_prog);
+ /* last cmd */
+ qemu_put_byte(f, s->last_cmd.cmd_code);
+ qemu_put_byte(f, s->last_cmd.flags);
+ qemu_put_be16(f, s->last_cmd.count);
+ qemu_put_be32(f, s->last_cmd.cda);
+ qemu_put_byte(f, s->last_cmd_valid);
+ qemu_put_byte(f, s->id.reserved);
+ qemu_put_be16(f, s->id.cu_type);
+ qemu_put_byte(f, s->id.cu_model);
+ qemu_put_be16(f, s->id.dev_type);
+ qemu_put_byte(f, s->id.dev_model);
+ qemu_put_byte(f, s->id.unused);
+ for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) {
+ qemu_put_byte(f, s->id.ciw[i].type);
+ qemu_put_byte(f, s->id.ciw[i].command);
+ qemu_put_be16(f, s->id.ciw[i].count);
+ }
+ qemu_put_byte(f, s->ccw_fmt_1);
+ qemu_put_byte(f, s->ccw_no_data_cnt);
+ return;
+}
+
+int subch_device_load(SubchDev *s, QEMUFile *f)
+{
+ int i;
+
+ s->cssid = qemu_get_byte(f);
+ s->ssid = qemu_get_byte(f);
+ s->schid = qemu_get_be16(f);
+ s->devno = qemu_get_be16(f);
+ s->thinint_active = qemu_get_byte(f);
+ /* SCHIB */
+ /* PMCW */
+ s->curr_status.pmcw.intparm = qemu_get_be32(f);
+ s->curr_status.pmcw.flags = qemu_get_be16(f);
+ s->curr_status.pmcw.devno = qemu_get_be16(f);
+ s->curr_status.pmcw.lpm = qemu_get_byte(f);
+ s->curr_status.pmcw.pnom = qemu_get_byte(f);
+ s->curr_status.pmcw.lpum = qemu_get_byte(f);
+ s->curr_status.pmcw.pim = qemu_get_byte(f);
+ s->curr_status.pmcw.mbi = qemu_get_be16(f);
+ s->curr_status.pmcw.pom = qemu_get_byte(f);
+ s->curr_status.pmcw.pam = qemu_get_byte(f);
+ qemu_get_buffer(f, s->curr_status.pmcw.chpid, 8);
+ s->curr_status.pmcw.chars = qemu_get_be32(f);
+ /* SCSW */
+ s->curr_status.scsw.flags = qemu_get_be16(f);
+ s->curr_status.scsw.ctrl = qemu_get_be16(f);
+ s->curr_status.scsw.cpa = qemu_get_be32(f);
+ s->curr_status.scsw.dstat = qemu_get_byte(f);
+ s->curr_status.scsw.cstat = qemu_get_byte(f);
+ s->curr_status.scsw.count = qemu_get_be16(f);
+ s->curr_status.mba = qemu_get_be64(f);
+ qemu_get_buffer(f, s->curr_status.mda, 4);
+ /* end SCHIB */
+ qemu_get_buffer(f, s->sense_data, 32);
+ s->channel_prog = qemu_get_be64(f);
+ /* last cmd */
+ s->last_cmd.cmd_code = qemu_get_byte(f);
+ s->last_cmd.flags = qemu_get_byte(f);
+ s->last_cmd.count = qemu_get_be16(f);
+ s->last_cmd.cda = qemu_get_be32(f);
+ s->last_cmd_valid = qemu_get_byte(f);
+ s->id.reserved = qemu_get_byte(f);
+ s->id.cu_type = qemu_get_be16(f);
+ s->id.cu_model = qemu_get_byte(f);
+ s->id.dev_type = qemu_get_be16(f);
+ s->id.dev_model = qemu_get_byte(f);
+ s->id.unused = qemu_get_byte(f);
+ for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) {
+ s->id.ciw[i].type = qemu_get_byte(f);
+ s->id.ciw[i].command = qemu_get_byte(f);
+ s->id.ciw[i].count = qemu_get_be16(f);
+ }
+ s->ccw_fmt_1 = qemu_get_byte(f);
+ s->ccw_no_data_cnt = qemu_get_byte(f);
+ /*
+ * Hack alert. We don't migrate the channel subsystem status (no
+ * device!), but we need to find out if the guest enabled mss/mcss-e.
+ * If the subchannel is enabled, it certainly was able to access it,
+ * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
+ * values. This is not watertight, but better than nothing.
+ */
+ if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
+ if (s->ssid) {
+ channel_subsys->max_ssid = MAX_SSID;
+ }
+ if (s->cssid != channel_subsys->default_cssid) {
+ channel_subsys->max_cssid = MAX_CSSID;
+ }
+ }
+ return 0;
+}
+
+
static void css_init(void)
{
channel_subsys = g_malloc0(sizeof(*channel_subsys));
channel_subsys->do_crw_mchk = true;
channel_subsys->crws_lost = false;
channel_subsys->chnmon_active = false;
+ QTAILQ_INIT(&channel_subsys->io_adapters);
}
machine_init(css_init);
{
PMCW *p = &sch->curr_status.pmcw;
+ if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) {
+ sch->disable_cb(sch);
+ }
+
p->intparm = 0;
p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
- sch->orb = NULL;
+ sch->thinint_active = false;
}
void css_reset(void)
projects / qemu.git / blobdiff