pp = pte1 & 0x00000003;
}
if (ptem == ctx->ptem) {
- if (ctx->raddr != (target_phys_addr_t)-1ULL) {
+ if (ctx->raddr != (hwaddr)-1ULL) {
/* all matches should have equal RPN, WIMG & PP */
if ((ctx->raddr & mmask) != (pte1 & mmask)) {
qemu_log("Bad RPN/WIMG/PP\n");
ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0);
}
-void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way, int is_code,
- target_ulong pte0, target_ulong pte1)
+static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
+ int is_code, target_ulong pte0, target_ulong pte1)
{
ppc6xx_tlb_t *tlb;
int nr;
return ret;
}
-static inline target_phys_addr_t get_pteg_offset(CPUPPCState *env,
- target_phys_addr_t hash,
+static inline hwaddr get_pteg_offset(CPUPPCState *env,
+ hwaddr hash,
int pte_size)
{
return (hash * pte_size * 8) & env->htab_mask;
static inline int find_pte2(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
int rw, int type, int target_page_bits)
{
- target_phys_addr_t pteg_off;
+ hwaddr pteg_off;
target_ulong pte0, pte1;
int i, good = -1;
int ret, r;
return NULL;
}
-void ppc_slb_invalidate_all(CPUPPCState *env)
+/*****************************************************************************/
+/* SPR accesses */
+
+void helper_slbia(CPUPPCState *env)
{
int n, do_invalidate;
}
}
-void ppc_slb_invalidate_one(CPUPPCState *env, uint64_t T0)
+void helper_slbie(CPUPPCState *env, target_ulong addr)
{
ppc_slb_t *slb;
- slb = slb_lookup(env, T0);
+ slb = slb_lookup(env, addr);
if (!slb) {
return;
}
return 0;
}
-int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb, target_ulong *rt)
+static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
+ target_ulong *rt)
{
int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
return 0;
}
-int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb, target_ulong *rt)
+static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
+ target_ulong *rt)
{
int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
{
- target_phys_addr_t hash;
+ hwaddr hash;
target_ulong vsid;
int ds, pr, target_page_bits;
int ret, ret2;
ctx->hash[1] = ~hash;
/* Initialize real address with an invalid value */
- ctx->raddr = (target_phys_addr_t)-1ULL;
+ ctx->raddr = (hwaddr)-1ULL;
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
/* Software TLB search */
}
#if defined(DUMP_PAGE_TABLES)
if (qemu_log_enabled()) {
- target_phys_addr_t curaddr;
+ hwaddr curaddr;
uint32_t a0, a1, a2, a3;
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
}
/* Generic TLB check function for embedded PowerPC implementations */
-int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddrp,
- target_ulong address, uint32_t pid, int ext,
- int i)
+static int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
+ hwaddr *raddrp,
+ target_ulong address, uint32_t pid, int ext,
+ int i)
{
target_ulong mask;
return -1;
}
*raddrp = (tlb->RPN & mask) | (address & ~mask);
-#if (TARGET_PHYS_ADDR_BITS >= 36)
if (ext) {
/* Extend the physical address to 36 bits */
- *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
+ *raddrp |= (uint64_t)(tlb->RPN & 0xF) << 32;
}
-#endif
return 0;
}
/* Generic TLB search function for PowerPC embedded implementations */
-int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid)
+static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
+ uint32_t pid)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, ret;
/* Default return value is no match */
{
#if !defined(FLUSH_ALL_TLBS)
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
target_ulong page, end;
int i;
int access_type)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, ret, zsel, zpr, pr;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (hwaddr)-1ULL;
pr = msr_pr;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
}
static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddr, int *prot,
+ hwaddr *raddr, int *prot,
target_ulong address, int rw,
int access_type, int i)
{
int access_type)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, ret;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (hwaddr)-1ULL;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
return ret;
}
-void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot)
+static void booke206_flush_tlb(CPUPPCState *env, int flags,
+ const int check_iprot)
{
int tlb_size;
int i, j;
tlb_flush(env, 1);
}
-target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env,
- ppcmas_tlb_t *tlb)
+static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
+ ppcmas_tlb_t *tlb)
{
int tlbm_size;
/* TLB check function for MAS based SoftTLBs */
int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddrp,
+ hwaddr *raddrp,
target_ulong address, uint32_t pid)
{
target_ulong mask;
}
static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddr, int *prot,
+ hwaddr *raddr, int *prot,
target_ulong address, int rw,
int access_type)
{
int access_type)
{
ppcmas_tlb_t *tlb;
- target_phys_addr_t raddr;
+ hwaddr raddr;
int i, j, ret;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (hwaddr)-1ULL;
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
int ways = booke206_tlb_ways(env, i);
entry = &env->tlb.tlbe[0];
for (i = 0; i < env->nb_tlb; i++, entry++) {
- target_phys_addr_t ea, pa;
+ hwaddr ea, pa;
target_ulong mask;
uint64_t size = (uint64_t)entry->size;
char size_buf[20];
mask = ~(entry->size - 1);
ea = entry->EPN & mask;
pa = entry->RPN & mask;
-#if (TARGET_PHYS_ADDR_BITS >= 36)
/* Extend the physical address to 36 bits */
- pa |= (target_phys_addr_t)(entry->RPN & 0xF) << 32;
-#endif
+ pa |= (hwaddr)(entry->RPN & 0xF) << 32;
size /= 1024;
if (size >= 1024) {
snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "M", size / 1024);
entry = &env->tlb.tlbm[offset];
for (i = 0; i < tlbsize; i++, entry++) {
- target_phys_addr_t ea, pa, size;
+ hwaddr ea, pa, size;
int tsize;
if (!(entry->mas1 & MAS1_VALID)) {
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
mmubooks_dump_mmu(f, cpu_fprintf, env);
break;
#endif
case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
/* Real address are 60 bits long */
ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
ctx->prot |= PAGE_WRITE;
return ret;
}
-int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
- int rw, int access_type)
+static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
{
int ret;
case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
#endif
if (ret < 0) {
/* We didn't match any BAT entry or don't have BATs */
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
{
mmu_ctx_t ctx;
case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
#endif
env->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x40000000;
case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
#endif
env->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
nr, ul == 0 ? 'u' : 'l', value, env->nip);
}
-void ppc_store_ibatu(CPUPPCState *env, int nr, target_ulong value)
+void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
{
target_ulong mask;
}
}
-void ppc_store_ibatl(CPUPPCState *env, int nr, target_ulong value)
+void helper_store_ibatl(CPUPPCState *env, uint32_t nr, target_ulong value)
{
dump_store_bat(env, 'I', 1, nr, value);
env->IBAT[1][nr] = value;
}
-void ppc_store_dbatu(CPUPPCState *env, int nr, target_ulong value)
+void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
{
target_ulong mask;
}
}
-void ppc_store_dbatl(CPUPPCState *env, int nr, target_ulong value)
+void helper_store_dbatl(CPUPPCState *env, uint32_t nr, target_ulong value)
{
dump_store_bat(env, 'D', 1, nr, value);
env->DBAT[1][nr] = value;
}
-void ppc_store_ibatu_601(CPUPPCState *env, int nr, target_ulong value)
+void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
{
target_ulong mask;
#if defined(FLUSH_ALL_TLBS)
}
}
-void ppc_store_ibatl_601(CPUPPCState *env, int nr, target_ulong value)
+void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
{
target_ulong mask;
#if defined(FLUSH_ALL_TLBS)
case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
#endif /* defined(TARGET_PPC64) */
tlb_flush(env, 1);
break;
case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
/* tlbie invalidate TLBs for all segments */
/* XXX: given the fact that there are too many segments to invalidate,
* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
}
}
-#if defined(TARGET_PPC64)
-target_ulong ppc_load_sr(CPUPPCState *env, int slb_nr)
+/* Segment registers load and store */
+target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
{
- /* XXX */
- return 0;
-}
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64) {
+ /* XXX */
+ return 0;
+ }
#endif
+ return env->sr[sr_num];
+}
-void ppc_store_sr(CPUPPCState *env, int srnum, target_ulong value)
+void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
{
LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
- srnum, value, env->sr[srnum]);
+ (int)srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
uint64_t rb = 0, rs = 0;
}
#endif /* !defined(CONFIG_USER_ONLY) */
-/*****************************************************************************/
-/* SPR accesses */
-
#if !defined(CONFIG_USER_ONLY)
-void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong val)
-{
- ppc_store_ibatu(env, nr, val);
-}
-
-void helper_store_ibatl(CPUPPCState *env, uint32_t nr, target_ulong val)
-{
- ppc_store_ibatl(env, nr, val);
-}
-
-void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong val)
-{
- ppc_store_dbatu(env, nr, val);
-}
-
-void helper_store_dbatl(CPUPPCState *env, uint32_t nr, target_ulong val)
-{
- ppc_store_dbatl(env, nr, val);
-}
-
-void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong val)
-{
- ppc_store_ibatl_601(env, nr, val);
-}
-
-void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong val)
-{
- ppc_store_ibatu_601(env, nr, val);
-}
-
-/* Segment registers load and store */
-target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
-{
-#if defined(TARGET_PPC64)
- if (env->mmu_model & POWERPC_MMU_64) {
- return ppc_load_sr(env, sr_num);
- }
-#endif
- return env->sr[sr_num];
-}
-
-void helper_store_sr(CPUPPCState *env, target_ulong sr_num, target_ulong val)
-{
- ppc_store_sr(env, sr_num, val);
-}
-
/* SLB management */
#if defined(TARGET_PPC64)
void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
}
return rt;
}
-
-void helper_slbia(CPUPPCState *env)
-{
- ppc_slb_invalidate_all(env);
-}
-
-void helper_slbie(CPUPPCState *env, target_ulong addr)
-{
- ppc_slb_invalidate_one(env, addr);
-}
-
#endif /* defined(TARGET_PPC64) */
/* TLB management */
uint32_t tlbncfg, tlbn;
ppcmas_tlb_t *tlb;
uint32_t size_tlb, size_ps;
+ target_ulong mask;
+
switch (env->spr[SPR_BOOKE_MAS0] & MAS0_WQ_MASK) {
case MAS0_WQ_ALWAYS:
tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
}
- /* XXX needs to change when supporting 64-bit e500 */
- tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & 0xffffffff;
+ /* Make a mask from TLB size to discard invalid bits in EPN field */
+ mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
+ /* Add a mask for page attributes */
+ mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E;
+
+ if (!msr_cm) {
+ /* Executing a tlbwe instruction in 32-bit mode will set
+ * bits 0:31 of the TLB EPN field to zero.
+ */
+ mask &= 0xffffffff;
+ }
+
+ tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & mask;
if (!(tlbncfg & TLBnCFG_IPROT)) {
/* no IPROT supported by TLB */
{
ppcmas_tlb_t *tlb = NULL;
int i, j;
- target_phys_addr_t raddr;
+ hwaddr raddr;
uint32_t spid, sas;
spid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID_MASK) >> MAS6_SPID_SHIFT;
projects / qemu.git / blobdiff