#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
-extern int nographic;
extern FILE *logfile;
typedef struct {
static PITState *pit;
+static struct _loaderparams {
+ int ram_size;
+ const char *kernel_filename;
+ const char *kernel_cmdline;
+ const char *initrd_filename;
+} loaderparams;
+
/* Malta FPGA */
static void malta_fpga_update_display(void *opaque)
{
int i;
MaltaFPGAState *s = opaque;
- if (!nographic) {
- for (i = 7 ; i >= 0 ; i--) {
- if (s->leds & (1 << i))
- leds_text[i] = '#';
- else
- leds_text[i] = ' ';
- }
- leds_text[8] = '\0';
-
- qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
- qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
+ for (i = 7 ; i >= 0 ; i--) {
+ if (s->leds & (1 << i))
+ leds_text[i] = '#';
+ else
+ leds_text[i] = ' ';
}
+ leds_text[8] = '\0';
+
+ qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
+ qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
}
/*
cpu_register_physical_memory(base, 0x900, malta);
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
- if (!nographic) {
- s->display = qemu_chr_open("vc");
- qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
- qemu_chr_printf(s->display, "+ +\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
- qemu_chr_printf(s->display, "\n");
- qemu_chr_printf(s->display, "Malta ASCII\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
- qemu_chr_printf(s->display, "+ +\r\n");
- qemu_chr_printf(s->display, "+--------+\r\n");
-
- uart_chr = qemu_chr_open("vc");
- qemu_chr_printf(uart_chr, "CBUS UART\r\n");
- s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
- }
+ s->display = qemu_chr_open("vc");
+ qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
+ qemu_chr_printf(s->display, "+--------+\r\n");
+ qemu_chr_printf(s->display, "+ +\r\n");
+ qemu_chr_printf(s->display, "+--------+\r\n");
+ qemu_chr_printf(s->display, "\n");
+ qemu_chr_printf(s->display, "Malta ASCII\r\n");
+ qemu_chr_printf(s->display, "+--------+\r\n");
+ qemu_chr_printf(s->display, "+ +\r\n");
+ qemu_chr_printf(s->display, "+--------+\r\n");
+
+ uart_chr = qemu_chr_open("vc");
+ qemu_chr_printf(uart_chr, "CBUS UART\r\n");
+ s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s);
stl_raw(p++, 0x00000000); /* nop */
/* YAMON service vector */
- stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
+ stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
- stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
+ stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_raw(p++, 0x3c070000 | (env->ram_size >> 16)); /* lui a3, high(env->ram_size) */
- stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
+ stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
+ stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
/* Load BAR registers as done by YAMON */
+ stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
+#else
+ stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
+#endif
+ stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
+
stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
#ifdef TARGET_WORDS_BIGENDIAN
long initrd_size;
ram_addr_t initrd_offset;
- if (load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND,
+ if (load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
&kernel_entry, &kernel_low, &kernel_high) < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
- env->kernel_filename);
+ loaderparams.kernel_filename);
exit(1);
}
/* load initrd */
initrd_size = 0;
initrd_offset = 0;
- if (env->initrd_filename) {
- initrd_size = get_image_size (env->initrd_filename);
+ if (loaderparams.initrd_filename) {
+ initrd_size = get_image_size (loaderparams.initrd_filename);
if (initrd_size > 0) {
initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
- if (initrd_offset + initrd_size > env->ram_size) {
+ if (initrd_offset + initrd_size > ram_size) {
fprintf(stderr,
"qemu: memory too small for initial ram disk '%s'\n",
- env->initrd_filename);
+ loaderparams.initrd_filename);
exit(1);
}
- initrd_size = load_image(env->initrd_filename,
+ initrd_size = load_image(loaderparams.initrd_filename,
phys_ram_base + initrd_offset);
}
if (initrd_size == (target_ulong) -1) {
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
- env->initrd_filename);
+ loaderparams.initrd_filename);
exit(1);
}
}
/* Store command line. */
- prom_set(index++, env->kernel_filename);
+ prom_set(index++, loaderparams.kernel_filename);
if (initrd_size > 0)
prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
PHYS_TO_VIRT(initrd_offset), initrd_size,
- env->kernel_cmdline);
+ loaderparams.kernel_cmdline);
else
- prom_set(index++, env->kernel_cmdline);
+ prom_set(index++, loaderparams.kernel_cmdline);
/* Setup minimum environment variables */
prom_set(index++, "memsize");
- prom_set(index++, "%i", env->ram_size);
+ prom_set(index++, "%i", loaderparams.ram_size);
prom_set(index++, "modetty0");
prom_set(index++, "38400n8r");
prom_set(index++, NULL);
{
CPUState *env = opaque;
cpu_reset(env);
- cpu_mips_register(env, NULL);
/* The bootload does not need to be rewritten as it is located in a
read only location. The kernel location and the arguments table
location does not change. */
- if (env->kernel_filename) {
+ if (loaderparams.kernel_filename) {
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
load_kernel (env);
}
}
static
-void mips_malta_init (int ram_size, int vga_ram_size, int boot_device,
+void mips_malta_init (int ram_size, int vga_ram_size, const char *boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
/* fdctrl_t *floppy_controller; */
MaltaFPGAState *malta_fpga;
int ret;
- mips_def_t *def;
qemu_irq *i8259;
int piix4_devfn;
uint8_t *eeprom_buf;
cpu_model = "24Kf";
#endif
}
- if (mips_find_by_name(cpu_model, &def) != 0)
- def = NULL;
- env = cpu_init();
- cpu_mips_register(env, def);
+ env = cpu_init(cpu_model);
+ if (!env) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
qemu_register_reset(main_cpu_reset, env);
/* Load a BIOS image unless a kernel image has been specified. */
if (!kernel_filename) {
- snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
+ if (bios_name == NULL)
+ bios_name = BIOS_FILENAME;
+ snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
ret = load_image(buf, phys_ram_base + bios_offset);
if (ret < 0 || ret > BIOS_SIZE) {
fprintf(stderr,
/* If a kernel image has been specified, write a small bootloader
to the flash location. */
if (kernel_filename) {
- env->ram_size = ram_size;
- env->kernel_filename = kernel_filename;
- env->kernel_cmdline = kernel_cmdline;
- env->initrd_filename = initrd_filename;
+ loaderparams.ram_size = ram_size;
+ loaderparams.kernel_filename = kernel_filename;
+ loaderparams.kernel_cmdline = kernel_cmdline;
+ loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel(env);
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
write_bootloader(env, bios_offset, kernel_entry);
projects / qemu.git / blobdiff