#include "hw.h"
#include "pc.h"
#include "qemu-timer.h"
+#include "osdep.h"
//#define DEBUG_APIC
//#define DEBUG_IOAPIC
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
static void apic_update_irq(APICState *s);
-/* Find first bit starting from msb. Return 0 if value = 0 */
+/* Find first bit starting from msb */
static int fls_bit(uint32_t value)
{
+#if QEMU_GNUC_PREREQ(3, 4)
+ return 31 - __builtin_clz(value);
+#else
unsigned int ret = 0;
-#if defined(HOST_I386)
- __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
- return ret;
-#else
if (value > 0xffff)
value >>= 16, ret = 16;
if (value > 0xff)
#endif
}
-/* Find first bit starting from lsb. Return 0 if value = 0 */
+/* Find first bit starting from lsb */
static int ffs_bit(uint32_t value)
{
+#if QEMU_GNUC_PREREQ(3, 4)
+ return __builtin_ffs(value) - 1;
+#else
unsigned int ret = 0;
-#if defined(HOST_I386)
- __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value));
- return ret;
-#else
if (!value)
return 0;
if (!(value & 0xffff))
tab[i] &= ~mask;
}
+static void apic_local_deliver(CPUState *env, int vector)
+{
+ APICState *s = env->apic_state;
+ uint32_t lvt = s->lvt[vector];
+ int trigger_mode;
+
+ if (lvt & APIC_LVT_MASKED)
+ return;
+
+ switch ((lvt >> 8) & 7) {
+ case APIC_DM_SMI:
+ cpu_interrupt(env, CPU_INTERRUPT_SMI);
+ break;
+
+ case APIC_DM_NMI:
+ cpu_interrupt(env, CPU_INTERRUPT_NMI);
+ break;
+
+ case APIC_DM_EXTINT:
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ break;
+
+ case APIC_DM_FIXED:
+ trigger_mode = APIC_TRIGGER_EDGE;
+ if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
+ (lvt & APIC_LVT_LEVEL_TRIGGER))
+ trigger_mode = APIC_TRIGGER_LEVEL;
+ apic_set_irq(s, lvt & 0xff, trigger_mode);
+ }
+}
+
+void apic_deliver_pic_intr(CPUState *env, int level)
+{
+ if (level)
+ apic_local_deliver(env, APIC_LVT_LINT0);
+ else {
+ APICState *s = env->apic_state;
+ uint32_t lvt = s->lvt[APIC_LVT_LINT0];
+
+ switch ((lvt >> 8) & 7) {
+ case APIC_DM_FIXED:
+ if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
+ break;
+ reset_bit(s->irr, lvt & 0xff);
+ /* fall through */
+ case APIC_DM_EXTINT:
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ break;
+ }
+ }
+}
+
#define foreach_apic(apic, deliver_bitmask, code) \
{\
int __i, __j, __mask;\
break;
case APIC_DM_SMI:
+ foreach_apic(apic_iter, deliver_bitmask,
+ cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
+ return;
+
case APIC_DM_NMI:
- break;
+ foreach_apic(apic_iter, deliver_bitmask,
+ cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
+ return;
case APIC_DM_INIT:
/* normal INIT IPI sent to processors */
s->initial_count = 0;
s->initial_count_load_time = 0;
s->next_time = 0;
+
+ cpu_reset(s->cpu_env);
+
+ if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
+ s->cpu_env->halted = 1;
}
/* send a SIPI message to the CPU to start it */
static void apic_startup(APICState *s, int vector_num)
{
CPUState *env = s->cpu_env;
- if (!(env->hflags & HF_HALTED_MASK))
+ if (!env->halted)
return;
env->eip = 0;
cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
0xffff, 0);
- env->hflags &= ~HF_HALTED_MASK;
+ env->halted = 0;
}
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
lvt0 = s->lvt[APIC_LVT_LINT0];
- if (s->id == 0 &&
- ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
- ((lvt0 & APIC_LVT_MASKED) == 0 &&
- ((lvt0 >> 8) & 0x7) == APIC_DM_EXTINT)))
+ if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
+ (lvt0 & APIC_LVT_MASKED) == 0)
return 1;
return 0;
d = (current_time - s->initial_count_load_time) >>
s->count_shift;
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
+ if (!s->initial_count)
+ goto no_timer;
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
} else {
if (d >= s->initial_count)
{
APICState *s = opaque;
- if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
- apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
- }
+ apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
apic_timer_update(s, s->next_time);
}
/* ppr */
val = apic_get_ppr(s);
break;
+ case 0x0b:
+ val = 0;
+ break;
case 0x0d:
val = s->log_dest << 24;
break;
qemu_put_be32s(f, &s->icr[0]);
qemu_put_be32s(f, &s->icr[1]);
qemu_put_be32s(f, &s->divide_conf);
- qemu_put_be32s(f, &s->count_shift);
+ qemu_put_be32(f, s->count_shift);
qemu_put_be32s(f, &s->initial_count);
- qemu_put_be64s(f, &s->initial_count_load_time);
- qemu_put_be64s(f, &s->next_time);
+ qemu_put_be64(f, s->initial_count_load_time);
+ qemu_put_be64(f, s->next_time);
qemu_put_timer(f, s->timer);
}
qemu_get_be32s(f, &s->icr[0]);
qemu_get_be32s(f, &s->icr[1]);
qemu_get_be32s(f, &s->divide_conf);
- qemu_get_be32s(f, &s->count_shift);
+ s->count_shift=qemu_get_be32(f);
qemu_get_be32s(f, &s->initial_count);
- qemu_get_be64s(f, &s->initial_count_load_time);
- qemu_get_be64s(f, &s->next_time);
+ s->initial_count_load_time=qemu_get_be64(f);
+ s->next_time=qemu_get_be64(f);
if (version_id >= 2)
qemu_get_timer(f, s->timer);
static void apic_reset(void *opaque)
{
APICState *s = opaque;
+
+ s->apicbase = 0xfee00000 |
+ (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
+
apic_init_ipi(s);
- /*
- * LINT0 delivery mode is set to ExtInt at initialization time
- * typically by BIOS, so PIC interrupt can be delivered to the
- * processor when local APIC is enabled.
- */
- s->lvt[APIC_LVT_LINT0] = 0x700;
+ if (s->id == 0) {
+ /*
+ * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
+ * time typically by BIOS, so PIC interrupt can be delivered to the
+ * processor when local APIC is enabled.
+ */
+ s->lvt[APIC_LVT_LINT0] = 0x700;
+ }
}
static CPUReadMemoryFunc *apic_mem_read[3] = {
if (!s)
return -1;
env->apic_state = s;
- apic_init_ipi(s);
s->id = last_apic_id++;
env->cpuid_apic_id = s->id;
s->cpu_env = env;
- s->apicbase = 0xfee00000 |
- (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
- /*
- * LINT0 delivery mode is set to ExtInt at initialization time
- * typically by BIOS, so PIC interrupt can be delivered to the
- * processor when local APIC is enabled.
- */
- s->lvt[APIC_LVT_LINT0] = 0x700;
+ apic_reset(s);
/* XXX: mapping more APICs at the same memory location */
if (apic_io_memory == 0) {
projects / qemu.git / blobdiff