*
*/
-#include "hw.h"
-#include "primecell.h"
+#include "sysbus.h"
#include "qemu-timer.h"
-#include "sysemu.h"
//#define DEBUG_PL031
#ifdef DEBUG_PL031
-#define DPRINTF(fmt, args...) \
-do { printf("pl031: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...) \
+do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define DPRINTF(fmt, args...) do {} while(0)
+#define DPRINTF(fmt, ...) do {} while(0)
#endif
#define RTC_DR 0x00 /* Data read register */
#define RTC_ICR 0x1c /* Interrupt clear register */
typedef struct {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
QEMUTimer *timer;
qemu_irq irq;
- uint32_t base;
- uint64_t start_time;
uint32_t tick_offset;
uint32_t mr;
uint32_t is;
} pl031_state;
+static const VMStateDescription vmstate_pl031 = {
+ .name = "pl031",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(tick_offset, pl031_state),
+ VMSTATE_UINT32(mr, pl031_state),
+ VMSTATE_UINT32(lr, pl031_state),
+ VMSTATE_UINT32(cr, pl031_state),
+ VMSTATE_UINT32(im, pl031_state),
+ VMSTATE_UINT32(is, pl031_state),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const unsigned char pl031_id[] = {
0x31, 0x10, 0x14, 0x00, /* Device ID */
0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
static uint32_t pl031_get_count(pl031_state *s)
{
- /* This assumes qemu_get_clock returns the time since the machine was
+ /* This assumes qemu_get_clock_ns returns the time since the machine was
created. */
- return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec;
+ return s->tick_offset + qemu_get_clock_ns(vm_clock) / get_ticks_per_sec();
}
static void pl031_set_alarm(pl031_state *s)
int64_t now;
uint32_t ticks;
- now = qemu_get_clock(vm_clock);
- ticks = s->tick_offset + now / ticks_per_sec;
+ now = qemu_get_clock_ns(vm_clock);
+ ticks = s->tick_offset + now / get_ticks_per_sec();
/* The timer wraps around. This subtraction also wraps in the same way,
and gives correct results when alarm < now_ticks. */
qemu_del_timer(s->timer);
pl031_interrupt(s);
} else {
- qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec);
+ qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
}
}
-static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
+static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
- offset -= s->base;
-
if (offset >= 0xfe0 && offset < 0x1000)
return pl031_id[(offset - 0xfe0) >> 2];
(int)offset);
break;
default:
- cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
- (int)offset);
+ hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
break;
}
}
static void pl031_write(void * opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
- offset -= s->base;
switch (offset) {
case RTC_LR:
pl031_update(s);
break;
case RTC_ICR:
- /* The PL031 documentation (DDI0224B) states that the interupt is
+ /* The PL031 documentation (DDI0224B) states that the interrupt is
cleared when bit 0 of the written value is set. However the
arm926e documentation (DDI0287B) states that the interrupt is
cleared when any value is written. */
break;
default:
- cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
- (int)offset);
+ hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
break;
}
}
-static CPUWriteMemoryFunc * pl031_writefn[] = {
- pl031_write,
- pl031_write,
- pl031_write
+static const MemoryRegionOps pl031_ops = {
+ .read = pl031_read,
+ .write = pl031_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUReadMemoryFunc * pl031_readfn[] = {
- pl031_read,
- pl031_read,
- pl031_read
-};
-
-void pl031_init(uint32_t base, qemu_irq irq)
+static int pl031_init(SysBusDevice *dev)
{
- int iomemtype;
- pl031_state *s;
- time_t ti;
- struct tm *tm;
+ pl031_state *s = FROM_SYSBUS(pl031_state, dev);
+ struct tm tm;
+
+ memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
- s = qemu_mallocz(sizeof(pl031_state));
- if (!s)
- cpu_abort(cpu_single_env, "pl031_init: Out of memory\n");
+ sysbus_init_irq(dev, &s->irq);
+ /* ??? We assume vm_clock is zero at this point. */
+ qemu_get_timedate(&tm, 0);
+ s->tick_offset = mktimegm(&tm);
- iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
- if (iomemtype == -1)
- cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
+ s->timer = qemu_new_timer_ns(vm_clock, pl031_interrupt, s);
+ return 0;
+}
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
+static SysBusDeviceInfo pl031_info = {
+ .init = pl031_init,
+ .qdev.name = "pl031",
+ .qdev.size = sizeof(pl031_state),
+ .qdev.vmsd = &vmstate_pl031,
+ .qdev.no_user = 1,
+};
- s->base = base;
- s->irq = irq;
- /* ??? We assume vm_clock is zero at this point. */
- time(&ti);
- if (rtc_utc)
- tm = gmtime(&ti);
- else
- tm = localtime(&ti);
- s->tick_offset = mktime(tm);
-
- s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s);
+static void pl031_register_devices(void)
+{
+ sysbus_register_withprop(&pl031_info);
}
+
+device_init(pl031_register_devices)
projects / qemu.git / blobdiff