use an uint64_t for the max_sz parameter in load_image_targphys

[qemu.git] / hw / dma.c

diff --git a/hw/dma.c b/hw/dma.c
index d779e4c94acface384a13257dae53b5486faf33d..0a9322daa3df807f3486799744c92ae0cd94af23 100644 (file)
--- a/hw/dma.c
+++ b/hw/dma.c
@@ -28,17 +28,13 @@
 
 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
 #ifdef DEBUG_DMA
 
 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
 #ifdef DEBUG_DMA

-#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)

 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
 #else
 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
 #else

-#define lwarn(...)

 #define linfo(...)
 #define ldebug(...)
 #endif
 
 #define linfo(...)
 #define ldebug(...)
 #endif
 

-#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
-

 struct dma_regs {
     int now[2];
     uint16_t base[2];
 struct dma_regs {
     int now[2];
     uint16_t base[2];


@@ -61,6 +57,7 @@ static struct dma_cont {
     uint8_t flip_flop;
     int dshift;
     struct dma_regs regs[4];
     uint8_t flip_flop;
     int dshift;
     struct dma_regs regs[4];

+    qemu_irq *cpu_request_exit;

 } dma_controllers[2];
 
 enum {
 } dma_controllers[2];
 
 enum {


@@ -78,6 +75,8 @@ enum {
 
 };
 
 
 };
 

+static void DMA_run (void);
+

 static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
 
 static void write_page (void *opaque, uint32_t nport, uint32_t data)
 static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
 
 static void write_page (void *opaque, uint32_t nport, uint32_t data)


@@ -214,6 +213,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
             d->status &= ~(1 << (ichan + 4));
         }
         d->status &= ~(1 << ichan);
             d->status &= ~(1 << (ichan + 4));
         }
         d->status &= ~(1 << ichan);

+        DMA_run();

         break;
 
     case 0x0a:                  /* single mask */
         break;
 
     case 0x0a:                  /* single mask */


@@ -221,6 +221,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
             d->mask |= 1 << (data & 3);
         else
             d->mask &= ~(1 << (data & 3));
             d->mask |= 1 << (data & 3);
         else
             d->mask &= ~(1 << (data & 3));

+        DMA_run();

         break;
 
     case 0x0b:                  /* mode */
         break;
 
     case 0x0b:                  /* mode */


@@ -255,10 +256,12 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
 
     case 0x0e:                  /* clear mask for all channels */
         d->mask = 0;
 
     case 0x0e:                  /* clear mask for all channels */
         d->mask = 0;

+        DMA_run();

         break;
 
     case 0x0f:                  /* write mask for all channels */
         d->mask = data;
         break;
 
     case 0x0f:                  /* write mask for all channels */
         d->mask = data;

+        DMA_run();

         break;
 
     default:
         break;
 
     default:


@@ -310,6 +313,7 @@ void DMA_hold_DREQ (int nchan)
     ichan = nchan & 3;
     linfo ("held cont=%d chan=%d\n", ncont, ichan);
     dma_controllers[ncont].status |= 1 << (ichan + 4);
     ichan = nchan & 3;
     linfo ("held cont=%d chan=%d\n", ncont, ichan);
     dma_controllers[ncont].status |= 1 << (ichan + 4);

+    DMA_run();

 }
 
 void DMA_release_DREQ (int nchan)
 }
 
 void DMA_release_DREQ (int nchan)


@@ -320,6 +324,7 @@ void DMA_release_DREQ (int nchan)
     ichan = nchan & 3;
     linfo ("released cont=%d chan=%d\n", ncont, ichan);
     dma_controllers[ncont].status &= ~(1 << (ichan + 4));
     ichan = nchan & 3;
     linfo ("released cont=%d chan=%d\n", ncont, ichan);
     dma_controllers[ncont].status &= ~(1 << (ichan + 4));

+    DMA_run();

 }
 
 static void channel_run (int ncont, int ichan)
 }
 
 static void channel_run (int ncont, int ichan)


@@ -340,17 +345,27 @@ static void channel_run (int ncont, int ichan)
     }
 #endif
 
     }
 #endif
 

-    r = dma_controllers[ncont].regs + ichan;

     n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
                              r->now[COUNT], (r->base[COUNT] + 1) << ncont);
     r->now[COUNT] = n;
     ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
 }
 
     n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
                              r->now[COUNT], (r->base[COUNT] + 1) << ncont);
     r->now[COUNT] = n;
     ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
 }
 

-void DMA_run (void)
+static QEMUBH *dma_bh;
+
+static void DMA_run (void)

 {
     struct dma_cont *d;
     int icont, ichan;
 {
     struct dma_cont *d;
     int icont, ichan;

+    int rearm = 0;
+    static int running = 0;
+
+    if (running) {
+        rearm = 1;
+        goto out;
+    } else {
+        running = 1;
+    }

 
     d = dma_controllers;
 
 
     d = dma_controllers;
 


@@ -360,10 +375,22 @@ void DMA_run (void)
 
             mask = 1 << ichan;
 
 
             mask = 1 << ichan;
 

-            if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4))))
+            if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {

                 channel_run (icont, ichan);
                 channel_run (icont, ichan);

+                rearm = 1;
+            }

         }
     }
         }
     }

+
+    running = 0;
+out:
+    if (rearm)
+        qemu_bh_schedule_idle(dma_bh);
+}
+
+static void DMA_run_bh(void *unused)
+{
+    DMA_run();

 }
 
 void DMA_register_channel (int nchan,
 }
 
 void DMA_register_channel (int nchan,


@@ -428,9 +455,9 @@ int DMA_write_memory (int nchan, void *buf, int pos, int len)
 /* request the emulator to transfer a new DMA memory block ASAP */
 void DMA_schedule(int nchan)
 {
 /* request the emulator to transfer a new DMA memory block ASAP */
 void DMA_schedule(int nchan)
 {

-    CPUState *env = cpu_single_env;
-    if (env)
-        cpu_interrupt(env, CPU_INTERRUPT_EXIT);
+    struct dma_cont *d = &dma_controllers[nchan > 3];
+
+    qemu_irq_pulse(*d->cpu_request_exit);

 }
 
 static void dma_reset(void *opaque)
 }
 
 static void dma_reset(void *opaque)


@@ -439,19 +466,28 @@ static void dma_reset(void *opaque)
     write_cont (d, (0x0d << d->dshift), 0);
 }
 
     write_cont (d, (0x0d << d->dshift), 0);
 }
 

+static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
+{
+    dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
+           nchan, dma_pos, dma_len);
+    return dma_pos;
+}
+

 /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
 static void dma_init2(struct dma_cont *d, int base, int dshift,
 /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
 static void dma_init2(struct dma_cont *d, int base, int dshift,

-                      int page_base, int pageh_base)
+                      int page_base, int pageh_base,
+                      qemu_irq *cpu_request_exit)

 {
 {

-    const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
+    static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };

     int i;
 
     d->dshift = dshift;
     int i;
 
     d->dshift = dshift;

+    d->cpu_request_exit = cpu_request_exit;

     for (i = 0; i < 8; i++) {
         register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
         register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
     }
     for (i = 0; i < 8; i++) {
         register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
         register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
     }

-    for (i = 0; i < LENOFA (page_port_list); i++) {
+    for (i = 0; i < ARRAY_SIZE (page_port_list); i++) {

         register_ioport_write (page_base + page_port_list[i], 1, 1,
                                write_page, d);
         register_ioport_read (page_base + page_port_list[i], 1, 1,
         register_ioport_write (page_base + page_port_list[i], 1, 1,
                                write_page, d);
         register_ioport_read (page_base + page_port_list[i], 1, 1,


@@ -471,68 +507,59 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
     }
     qemu_register_reset(dma_reset, d);
     dma_reset(d);
     }
     qemu_register_reset(dma_reset, d);
     dma_reset(d);

+    for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
+        d->regs[i].transfer_handler = dma_phony_handler;
+    }

 }
 
 }
 

-static void dma_save (QEMUFile *f, void *opaque)
-{
-    struct dma_cont *d = opaque;
-    int i;
-
-    /* qemu_put_8s (f, &d->status); */
-    qemu_put_8s (f, &d->command);
-    qemu_put_8s (f, &d->mask);
-    qemu_put_8s (f, &d->flip_flop);
-    qemu_put_be32s (f, &d->dshift);
-
-    for (i = 0; i < 4; ++i) {
-        struct dma_regs *r = &d->regs[i];
-        qemu_put_be32s (f, &r->now[0]);
-        qemu_put_be32s (f, &r->now[1]);
-        qemu_put_be16s (f, &r->base[0]);
-        qemu_put_be16s (f, &r->base[1]);
-        qemu_put_8s (f, &r->mode);
-        qemu_put_8s (f, &r->page);
-        qemu_put_8s (f, &r->pageh);
-        qemu_put_8s (f, &r->dack);
-        qemu_put_8s (f, &r->eop);
+static const VMStateDescription vmstate_dma_regs = {
+    .name = "dma_regs",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField []) {
+        VMSTATE_INT32_ARRAY(now, struct dma_regs, 2),
+        VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2),
+        VMSTATE_UINT8(mode, struct dma_regs),
+        VMSTATE_UINT8(page, struct dma_regs),
+        VMSTATE_UINT8(pageh, struct dma_regs),
+        VMSTATE_UINT8(dack, struct dma_regs),
+        VMSTATE_UINT8(eop, struct dma_regs),
+        VMSTATE_END_OF_LIST()

     }
     }

-}
+};

 
 

-static int dma_load (QEMUFile *f, void *opaque, int version_id)
+static int dma_post_load(void *opaque, int version_id)

 {
 {

-    struct dma_cont *d = opaque;
-    int i;
+    DMA_run();

 
 

-    if (version_id != 1)
-        return -EINVAL;
-
-    /* qemu_get_8s (f, &d->status); */
-    qemu_get_8s (f, &d->command);
-    qemu_get_8s (f, &d->mask);
-    qemu_get_8s (f, &d->flip_flop);
-    qemu_get_be32s (f, &d->dshift);
-
-    for (i = 0; i < 4; ++i) {
-        struct dma_regs *r = &d->regs[i];
-        qemu_get_be32s (f, &r->now[0]);
-        qemu_get_be32s (f, &r->now[1]);
-        qemu_get_be16s (f, &r->base[0]);
-        qemu_get_be16s (f, &r->base[1]);
-        qemu_get_8s (f, &r->mode);
-        qemu_get_8s (f, &r->page);
-        qemu_get_8s (f, &r->pageh);
-        qemu_get_8s (f, &r->dack);
-        qemu_get_8s (f, &r->eop);
-    }

     return 0;
 }
 
     return 0;
 }
 

-void DMA_init (int high_page_enable)
+static const VMStateDescription vmstate_dma = {
+    .name = "dma",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .post_load = dma_post_load,
+    .fields      = (VMStateField []) {
+        VMSTATE_UINT8(command, struct dma_cont),
+        VMSTATE_UINT8(mask, struct dma_cont),
+        VMSTATE_UINT8(flip_flop, struct dma_cont),
+        VMSTATE_INT32(dshift, struct dma_cont),
+        VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)

 {
     dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
 {
     dma_init2(&dma_controllers[0], 0x00, 0, 0x80,

-              high_page_enable ? 0x480 : -1);
+              high_page_enable ? 0x480 : -1, cpu_request_exit);

     dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
     dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,

-              high_page_enable ? 0x488 : -1);
-    register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]);
-    register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]);
+              high_page_enable ? 0x488 : -1, cpu_request_exit);
+    vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
+    vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
+
+    dma_bh = qemu_bh_new(DMA_run_bh, NULL);

 }
 }