xilinx_ethlite: use qdev properties for configuration.

[qemu.git] / hw / heathrow_pic.c

diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index dc2a30c8520e1f404ef37b449bfb22b16dbd792a..500b9f19bf9430a0a99930ec5b138820ddc83cf0 100644 (file)
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -25,7 +25,15 @@
 #include "hw.h"
 #include "ppc_mac.h"
 
-//#define DEBUG
+/* debug PIC */
+//#define DEBUG_PIC
+
+#ifdef DEBUG_PIC
+#define PIC_DPRINTF(fmt, ...)                                   \
+    do { printf("PIC: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define PIC_DPRINTF(fmt, ...)
+#endif
 
 typedef struct HeathrowPIC {
     uint32_t events;
@@ -64,9 +72,7 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
     value = bswap32(value);
 #endif
     n = ((addr & 0xfff) - 0x10) >> 4;
-#ifdef DEBUG
-    printf("pic_writel: " PADDRX " %u: %08x\n", addr, n, value);
-#endif
+    PIC_DPRINTF("writel: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
     if (n >= 2)
         return;
     pic = &s->pics[n];
@@ -113,22 +119,20 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
             break;
         }
     }
-#ifdef DEBUG
-    printf("pic_readl: " PADDRX " %u: %08x\n", addr, n, value);
-#endif
+    PIC_DPRINTF("readl: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
 #ifdef TARGET_WORDS_BIGENDIAN
     value = bswap32(value);
 #endif
     return value;
 }
 
-static CPUWriteMemoryFunc *pic_write[] = {
+static CPUWriteMemoryFunc * const pic_write[] = {
     &pic_writel,
     &pic_writel,
     &pic_writel,
 };
 
-static CPUReadMemoryFunc *pic_read[] = {
+static CPUReadMemoryFunc * const pic_read[] = {
     &pic_readl,
     &pic_readl,
     &pic_readl,
@@ -145,7 +149,7 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
     {
         static int last_level[64];
         if (last_level[num] != level) {
-            printf("set_irq: num=0x%02x level=%d\n", num, level);
+            PIC_DPRINTF("set_irq: num=0x%02x level=%d\n", num, level);
             last_level[num] = level;
         }
     }
@@ -161,17 +165,72 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
     heathrow_pic_update(s);
 }
 
+static void heathrow_pic_save_one(QEMUFile *f, HeathrowPIC *s)
+{
+    qemu_put_be32s(f, &s->events);
+    qemu_put_be32s(f, &s->mask);
+    qemu_put_be32s(f, &s->levels);
+    qemu_put_be32s(f, &s->level_triggered);
+}
+
+static void heathrow_pic_save(QEMUFile *f, void *opaque)
+{
+    HeathrowPICS *s = (HeathrowPICS *)opaque;
+
+    heathrow_pic_save_one(f, &s->pics[0]);
+    heathrow_pic_save_one(f, &s->pics[1]);
+}
+
+static void heathrow_pic_load_one(QEMUFile *f, HeathrowPIC *s)
+{
+    qemu_get_be32s(f, &s->events);
+    qemu_get_be32s(f, &s->mask);
+    qemu_get_be32s(f, &s->levels);
+    qemu_get_be32s(f, &s->level_triggered);
+}
+
+static int heathrow_pic_load(QEMUFile *f, void *opaque, int version_id)
+{
+    HeathrowPICS *s = (HeathrowPICS *)opaque;
+
+    if (version_id != 1)
+        return -EINVAL;
+
+    heathrow_pic_load_one(f, &s->pics[0]);
+    heathrow_pic_load_one(f, &s->pics[1]);
+
+    return 0;
+}
+
+static void heathrow_pic_reset_one(HeathrowPIC *s)
+{
+    memset(s, '\0', sizeof(HeathrowPIC));
+}
+
+static void heathrow_pic_reset(void *opaque)
+{
+    HeathrowPICS *s = opaque;
+
+    heathrow_pic_reset_one(&s->pics[0]);
+    heathrow_pic_reset_one(&s->pics[1]);
+
+    s->pics[0].level_triggered = 0;
+    s->pics[1].level_triggered = 0x1ff00000;
+}
+
 qemu_irq *heathrow_pic_init(int *pmem_index,
                             int nb_cpus, qemu_irq **irqs)
 {
     HeathrowPICS *s;
 
     s = qemu_mallocz(sizeof(HeathrowPICS));
-    s->pics[0].level_triggered = 0;
-    s->pics[1].level_triggered = 0x1ff00000;
     /* only 1 CPU */
     s->irqs = irqs[0];
-    *pmem_index = cpu_register_io_memory(0, pic_read, pic_write, s);
+    *pmem_index = cpu_register_io_memory(pic_read, pic_write, s);
 
+    register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
+                    heathrow_pic_load, s);
+    qemu_register_reset(heathrow_pic_reset, s);
+    heathrow_pic_reset(s);
     return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
 }