according to jump_pc[T2] */
/* global register indexes */
-static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst;
-static TCGv cpu_psr, cpu_fsr, cpu_gregs[8];
+static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
+static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
#ifdef TARGET_SPARC64
static TCGv cpu_xcc;
#endif
/* local register indexes (only used inside old micro ops) */
-static TCGv cpu_tmp0;
+static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
typedef struct DisasContext {
target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
#define IS_IMM (insn & (1<<13))
-static void disas_sparc_insn(DisasContext * dc);
+/* floating point registers moves */
+static void gen_op_load_fpr_FT0(unsigned int src)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
+}
-#ifdef TARGET_SPARC64
-#define GEN32(func, NAME) \
-static GenOpFunc * const NAME ## _table [64] = { \
-NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
-NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
-NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
-NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
-NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
-NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
-NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
-NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
-NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
-NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
-NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
-NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
-}; \
-static inline void func(int n) \
-{ \
- NAME ## _table[n](); \
+static void gen_op_load_fpr_FT1(unsigned int src)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
}
-#else
-#define GEN32(func, NAME) \
-static GenOpFunc *const NAME ## _table [32] = { \
-NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
-NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
-NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
-NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
-NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
-NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
-NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
-NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
-}; \
-static inline void func(int n) \
-{ \
- NAME ## _table[n](); \
+
+static void gen_op_store_FT0_fpr(unsigned int dst)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
}
-#endif
-/* floating point registers moves */
-GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
-GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
-GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
-GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
+static void gen_op_load_fpr_DT0(unsigned int src)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
+}
-GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
-GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
-GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
-GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
+static void gen_op_load_fpr_DT1(unsigned int src)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
+}
-#if defined(CONFIG_USER_ONLY)
-GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
-GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
-GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
-GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
+static void gen_op_store_DT0_fpr(unsigned int dst)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
+}
+
+#ifdef CONFIG_USER_ONLY
+static void gen_op_load_fpr_QT0(unsigned int src)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
+}
+
+static void gen_op_load_fpr_QT1(unsigned int src)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
+}
+
+static void gen_op_store_QT0_fpr(unsigned int dst)
+{
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
+}
#endif
/* moves */
#ifdef __i386__
OP_LD_TABLE(std);
#endif /* __i386__ */
-OP_LD_TABLE(stf);
OP_LD_TABLE(stdf);
-OP_LD_TABLE(ldf);
OP_LD_TABLE(lddf);
#endif
#ifdef TARGET_ABI32
-#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
+#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
#else
#define ABI32_MASK(addr)
#endif
-static inline void gen_movl_simm_T1(int32_t val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
static inline void gen_movl_reg_TN(int reg, TCGv tn)
{
if (reg == 0)
}
}
-static inline void gen_movl_reg_T0(int reg)
-{
- gen_movl_reg_TN(reg, cpu_T[0]);
-}
-
-static inline void gen_movl_reg_T1(int reg)
-{
- gen_movl_reg_TN(reg, cpu_T[1]);
-}
-
-#ifdef __i386__
-static inline void gen_movl_reg_T2(int reg)
-{
- gen_movl_reg_TN(reg, cpu_T[2]);
-}
-
-#endif /* __i386__ */
static inline void gen_movl_TN_reg(int reg, TCGv tn)
{
if (reg == 0)
}
}
-static inline void gen_movl_T0_reg(int reg)
-{
- gen_movl_TN_reg(reg, cpu_T[0]);
-}
-
-static inline void gen_movl_T1_reg(int reg)
-{
- gen_movl_TN_reg(reg, cpu_T[1]);
-}
-
-static inline void gen_op_movl_T0_env(size_t offset)
-{
- tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
-}
-
-static inline void gen_op_movl_env_T0(size_t offset)
-{
- tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
-}
-
-static inline void gen_op_movtl_T0_env(size_t offset)
-{
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
-}
-
-static inline void gen_op_movtl_env_T0(size_t offset)
-{
- tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
-}
-
-static inline void gen_op_add_T1_T0(void)
-{
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_or_T1_T0(void)
-{
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_xor_T1_T0(void)
-{
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_jmp_im(target_ulong pc)
-{
- tcg_gen_movi_tl(cpu_tmp0, pc);
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
-}
-
-static inline void gen_movl_npc_im(target_ulong npc)
-{
- tcg_gen_movi_tl(cpu_tmp0, npc);
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
-}
-
static inline void gen_goto_tb(DisasContext *s, int tb_num,
target_ulong pc, target_ulong npc)
{
(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
- gen_jmp_im(pc);
- gen_movl_npc_im(npc);
+ tcg_gen_movi_tl(cpu_pc, pc);
+ tcg_gen_movi_tl(cpu_npc, npc);
tcg_gen_exit_tb((long)tb + tb_num);
} else {
/* jump to another page: currently not optimized */
- gen_jmp_im(pc);
- gen_movl_npc_im(npc);
+ tcg_gen_movi_tl(cpu_pc, pc);
+ tcg_gen_movi_tl(cpu_npc, npc);
tcg_gen_exit_tb(0);
}
}
// XXX suboptimal
static inline void gen_mov_reg_N(TCGv reg, TCGv src)
{
- tcg_gen_shri_i32(reg, src, 23);
+ tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_shri_tl(reg, reg, 23);
tcg_gen_andi_tl(reg, reg, 0x1);
}
static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
{
- tcg_gen_shri_i32(reg, src, 22);
+ tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_shri_tl(reg, reg, 22);
tcg_gen_andi_tl(reg, reg, 0x1);
}
static inline void gen_mov_reg_V(TCGv reg, TCGv src)
{
- tcg_gen_shri_i32(reg, src, 21);
+ tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_shri_tl(reg, reg, 21);
tcg_gen_andi_tl(reg, reg, 0x1);
}
static inline void gen_mov_reg_C(TCGv reg, TCGv src)
{
- tcg_gen_shri_i32(reg, src, 20);
+ tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_shri_tl(reg, reg, 20);
tcg_gen_andi_tl(reg, reg, 0x1);
}
-static inline void gen_op_exception(int exception)
+static inline void gen_cc_clear_icc(void)
{
- TCGv r_except;
-
- r_except = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_except, exception);
- tcg_gen_helper_0_1(raise_exception, r_except);
+ tcg_gen_movi_i32(cpu_psr, 0);
}
-static inline void gen_cc_clear(void)
-{
- tcg_gen_movi_i32(cpu_psr, 0);
#ifdef TARGET_SPARC64
+static inline void gen_cc_clear_xcc(void)
+{
tcg_gen_movi_i32(cpu_xcc, 0);
-#endif
}
+#endif
/* old op:
if (!T0)
if ((int32_t) T0 < 0)
env->psr |= PSR_NEG;
*/
-static inline void gen_cc_NZ(TCGv dst)
+static inline void gen_cc_NZ_icc(TCGv dst)
{
+ TCGv r_temp;
int l1, l2;
- TCGv r_zero;
l1 = gen_new_label();
l2 = gen_new_label();
- r_zero = tcg_const_tl(0);
- tcg_gen_brcond_i32(TCG_COND_NE, dst, r_zero, l1);
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
+ tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
gen_set_label(l1);
- tcg_gen_brcond_i32(TCG_COND_GE, dst, r_zero, l2);
+ tcg_gen_ext_i32_tl(r_temp, dst);
+ tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
gen_set_label(l2);
+}
+
#ifdef TARGET_SPARC64
- {
- int l3, l4;
-
- l3 = gen_new_label();
- l4 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_NE, dst, r_zero, l3);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
- gen_set_label(l3);
- tcg_gen_brcond_tl(TCG_COND_GE, dst, r_zero, l4);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
- gen_set_label(l4);
- }
-#endif
+static inline void gen_cc_NZ_xcc(TCGv dst)
+{
+ int l1, l2;
+
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
+ gen_set_label(l1);
+ tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
+ gen_set_label(l2);
}
+#endif
/* old op:
if (T0 < src1)
env->psr |= PSR_CARRY;
*/
-static inline void gen_cc_C_add(TCGv dst, TCGv src1)
+static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
{
+ TCGv r_temp;
int l1;
l1 = gen_new_label();
- tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
+ tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
gen_set_label(l1);
+}
+
#ifdef TARGET_SPARC64
- {
- int l2;
+static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
+{
+ int l1;
- l2 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
- gen_set_label(l2);
- }
-#endif
+ l1 = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
+ gen_set_label(l1);
}
+#endif
/* old op:
if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
env->psr |= PSR_OVF;
*/
-static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
{
- TCGv r_temp, r_temp2, r_temp3, r_zero;
+ TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
- r_temp2 = tcg_temp_new(TCG_TYPE_TL);
- r_temp3 = tcg_temp_new(TCG_TYPE_TL);
- r_zero = tcg_const_tl(0);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xori_tl(r_temp, r_temp, -1);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
- tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
+ tcg_gen_xor_tl(cpu_tmp0, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
+ tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
gen_set_label(l1);
+}
+
#ifdef TARGET_SPARC64
- {
- int l2;
-
- l2 = gen_new_label();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xori_tl(r_temp, r_temp, -1);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
- gen_set_label(l2);
- }
-#endif
+static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
+{
+ TCGv r_temp;
+ int l1;
+
+ l1 = gen_new_label();
+
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_xor_tl(cpu_tmp0, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
+ tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
+ gen_set_label(l1);
}
+#endif
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
{
- TCGv r_temp, r_temp2, r_temp3, r_zero;
+ TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
- r_temp2 = tcg_temp_new(TCG_TYPE_TL);
- r_temp3 = tcg_temp_new(TCG_TYPE_TL);
- r_zero = tcg_const_tl(0);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xori_tl(r_temp, r_temp, -1);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
- tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
- gen_op_exception(TT_TOVF);
+ tcg_gen_xor_tl(cpu_tmp0, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
+ tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l1);
-#ifdef TARGET_SPARC64
- {
- int l2;
-
- l2 = gen_new_label();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xori_tl(r_temp, r_temp, -1);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
- gen_op_exception(TT_TOVF);
- gen_set_label(l2);
- }
-#endif
}
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
{
int l1;
- TCGv r_zero, r_temp;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
- r_temp = tcg_temp_new(TCG_TYPE_TL);
- tcg_gen_or_tl(r_temp, src1, src2);
- tcg_gen_andi_tl(r_temp, r_temp, 0x3);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
+ tcg_gen_or_tl(cpu_tmp0, src1, src2);
+ tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
+ tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
gen_set_label(l1);
}
static inline void gen_tag_tv(TCGv src1, TCGv src2)
{
int l1;
- TCGv r_zero, r_temp;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
- r_temp = tcg_temp_new(TCG_TYPE_TL);
- tcg_gen_or_tl(r_temp, src1, src2);
- tcg_gen_andi_tl(r_temp, r_temp, 0x3);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
- gen_op_exception(TT_TOVF);
+ tcg_gen_or_tl(cpu_tmp0, src1, src2);
+ tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
+ tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l1);
}
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
- gen_cc_C_add(cpu_T[0], cpu_cc_src);
- gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
}
static inline void gen_op_addx_T1_T0_cc(void)
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
- gen_cc_clear();
- gen_cc_C_add(cpu_T[0], cpu_cc_src);
+ gen_cc_clear_icc();
+ gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
+#endif
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_cc_C_add(cpu_T[0], cpu_cc_src);
- gen_cc_NZ(cpu_T[0]);
- gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#ifdef TARGET_SPARC64
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
}
static inline void gen_op_tadd_T1_T0_cc(void)
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
- gen_cc_C_add(cpu_T[0], cpu_cc_src);
- gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
}
static inline void gen_op_tadd_T1_T0_ccTV(void)
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
- gen_cc_C_add(cpu_T[0], cpu_cc_src);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
}
/* old op:
if (src1 < T1)
env->psr |= PSR_CARRY;
*/
-static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
+static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
{
+ TCGv r_temp1, r_temp2;
int l1;
l1 = gen_new_label();
- tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
+ r_temp1 = tcg_temp_new(TCG_TYPE_TL);
+ r_temp2 = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
+ tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
+ tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
gen_set_label(l1);
+}
+
#ifdef TARGET_SPARC64
- {
- int l2;
+static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
+{
+ int l1;
- l2 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
- gen_set_label(l2);
- }
-#endif
+ l1 = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
+ gen_set_label(l1);
}
+#endif
/* old op:
if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
env->psr |= PSR_OVF;
*/
-static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
{
- TCGv r_temp, r_temp2, r_temp3, r_zero;
+ TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
- r_temp2 = tcg_temp_new(TCG_TYPE_TL);
- r_temp3 = tcg_temp_new(TCG_TYPE_TL);
- r_zero = tcg_const_tl(0);
tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
- tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
+ tcg_gen_xor_tl(cpu_tmp0, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
+ tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
gen_set_label(l1);
+}
+
#ifdef TARGET_SPARC64
- {
- int l2;
-
- l2 = gen_new_label();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
- gen_set_label(l2);
- }
-#endif
+static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
+{
+ TCGv r_temp;
+ int l1;
+
+ l1 = gen_new_label();
+
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xor_tl(cpu_tmp0, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
+ tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
+ gen_set_label(l1);
}
+#endif
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
{
- TCGv r_temp, r_temp2, r_temp3, r_zero;
+ TCGv r_temp;
int l1;
l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
- r_temp2 = tcg_temp_new(TCG_TYPE_TL);
- r_temp3 = tcg_temp_new(TCG_TYPE_TL);
- r_zero = tcg_const_tl(0);
tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
- tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
- gen_op_exception(TT_TOVF);
+ tcg_gen_xor_tl(cpu_tmp0, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
+ tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
gen_set_label(l1);
-#ifdef TARGET_SPARC64
- {
- int l2;
-
- l2 = gen_new_label();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xor_tl(r_temp2, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, r_temp2);
- tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
- gen_op_exception(TT_TOVF);
- gen_set_label(l2);
- }
-#endif
+ tcg_gen_discard_tl(r_temp);
}
static inline void gen_op_sub_T1_T0_cc(void)
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
- gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
- gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);
+ gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);
+ gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
}
static inline void gen_op_subx_T1_T0_cc(void)
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
- gen_cc_clear();
- gen_cc_C_sub(cpu_T[0], cpu_cc_src);
+ gen_cc_clear_icc();
+ gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src);
+#endif
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_cc_C_sub(cpu_T[0], cpu_cc_src);
- gen_cc_NZ(cpu_T[0]);
- gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#ifdef TARGET_SPARC64
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src);
+ gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
}
static inline void gen_op_tsub_T1_T0_cc(void)
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
- gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
- gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);
+ gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);
+ gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
}
static inline void gen_op_tsub_T1_T0_ccTV(void)
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
- gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_NZ_xcc(cpu_T[0]);
+ gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);
+ gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
+#endif
+}
+
+static inline void gen_op_mulscc_T1_T0(void)
+{
+ TCGv r_temp, r_temp2;
+ int l1, l2;
+
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ r_temp2 = tcg_temp_new(TCG_TYPE_I32);
+
+ /* old op:
+ if (!(env->y & 1))
+ T1 = 0;
+ */
+ tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
+ tcg_gen_trunc_tl_i32(r_temp2, r_temp);
+ tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
+ tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
+ tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_movi_tl(cpu_cc_src2, 0);
+ gen_set_label(l2);
+
+ // b2 = T0 & 1;
+ // env->y = (b2 << 31) | (env->y >> 1);
+ tcg_gen_trunc_tl_i32(r_temp2, cpu_T[0]);
+ tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
+ tcg_gen_shli_i32(r_temp2, r_temp2, 31);
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
+ tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
+ tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
+
+ // b1 = N ^ V;
+ gen_mov_reg_N(cpu_tmp0, cpu_psr);
+ gen_mov_reg_V(r_temp, cpu_psr);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
+
+ // T0 = (b1 << 31) | (T0 >> 1);
+ // src1 = T0;
+ tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
+ tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1);
+ tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
+
+ /* do addition and update flags */
+ tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2);
+ tcg_gen_discard_tl(r_temp);
+
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+ gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_cc_src2);
+ gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
+}
+
+static inline void gen_op_umul_T1_T0(void)
+{
+ TCGv r_temp, r_temp2;
+
+ r_temp = tcg_temp_new(TCG_TYPE_I64);
+ r_temp2 = tcg_temp_new(TCG_TYPE_I64);
+
+ tcg_gen_extu_tl_i64(r_temp, cpu_T[1]);
+ tcg_gen_extu_tl_i64(r_temp2, cpu_T[0]);
+ tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
+
+ tcg_gen_shri_i64(r_temp, r_temp2, 32);
+ tcg_gen_trunc_i64_i32(r_temp, r_temp);
+ tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
+#ifdef TARGET_SPARC64
+ tcg_gen_mov_i64(cpu_T[0], r_temp2);
+#else
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
+#endif
+
+ tcg_gen_discard_i64(r_temp);
+ tcg_gen_discard_i64(r_temp2);
}
+static inline void gen_op_smul_T1_T0(void)
+{
+ TCGv r_temp, r_temp2;
+
+ r_temp = tcg_temp_new(TCG_TYPE_I64);
+ r_temp2 = tcg_temp_new(TCG_TYPE_I64);
+
+ tcg_gen_ext_tl_i64(r_temp, cpu_T[1]);
+ tcg_gen_ext_tl_i64(r_temp2, cpu_T[0]);
+ tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
+
+ tcg_gen_shri_i64(r_temp, r_temp2, 32);
+ tcg_gen_trunc_i64_i32(r_temp, r_temp);
+ tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
#ifdef TARGET_SPARC64
-static inline void gen_trap_ifdivzero_i64(TCGv divisor)
+ tcg_gen_mov_i64(cpu_T[0], r_temp2);
+#else
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
+#endif
+
+ tcg_gen_discard_i64(r_temp);
+ tcg_gen_discard_i64(r_temp2);
+}
+
+#ifdef TARGET_SPARC64
+static inline void gen_trap_ifdivzero_tl(TCGv divisor)
{
int l1;
l1 = gen_new_label();
- tcg_gen_brcond_i64(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
- gen_op_exception(TT_DIV_ZERO);
+ tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
gen_set_label(l1);
}
l1 = gen_new_label();
l2 = gen_new_label();
- gen_trap_ifdivzero_i64(cpu_T[1]);
- tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[0], tcg_const_i64(INT64_MIN), l1);
- tcg_gen_brcond_i64(TCG_COND_NE, cpu_T[1], tcg_const_i64(-1), l1);
+ gen_trap_ifdivzero_tl(cpu_T[1]);
+ tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], tcg_const_tl(INT64_MIN), l1);
+ tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(-1), l1);
tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
- gen_op_jmp_label(l2);
+ tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_set_label(l2);
static inline void gen_op_div_cc(void)
{
int l1;
- TCGv r_zero;
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
- tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], r_zero, l1);
+ tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
+ tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
gen_set_label(l1);
}
static inline void gen_op_logic_T0_cc(void)
{
- gen_cc_clear();
- gen_cc_NZ(cpu_T[0]);
+ gen_cc_clear_icc();
+ gen_cc_NZ_icc(cpu_T[0]);
+#ifdef TARGET_SPARC64
+ gen_cc_clear_xcc();
+ gen_cc_NZ_xcc(cpu_T[0]);
+#endif
}
// 1
// Z | (N ^ V)
static inline void gen_op_eval_ble(TCGv dst, TCGv src)
{
- TCGv r_flag;
-
- r_flag = tcg_temp_new(TCG_TYPE_TL);
- gen_mov_reg_N(r_flag, src);
+ gen_mov_reg_N(cpu_tmp0, src);
gen_mov_reg_V(dst, src);
- tcg_gen_xor_tl(dst, dst, r_flag);
- gen_mov_reg_Z(r_flag, src);
- tcg_gen_or_tl(dst, dst, r_flag);
+ tcg_gen_xor_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_Z(cpu_tmp0, src);
+ tcg_gen_or_tl(dst, dst, cpu_tmp0);
}
// N ^ V
static inline void gen_op_eval_bl(TCGv dst, TCGv src)
{
- TCGv r_V;
-
- r_V = tcg_temp_new(TCG_TYPE_TL);
- gen_mov_reg_V(r_V, src);
+ gen_mov_reg_V(cpu_tmp0, src);
gen_mov_reg_N(dst, src);
- tcg_gen_xor_tl(dst, dst, r_V);
+ tcg_gen_xor_tl(dst, dst, cpu_tmp0);
}
// C | Z
static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
{
- TCGv r_Z;
-
- r_Z = tcg_temp_new(TCG_TYPE_TL);
- gen_mov_reg_Z(r_Z, src);
+ gen_mov_reg_Z(cpu_tmp0, src);
gen_mov_reg_C(dst, src);
- tcg_gen_or_tl(dst, dst, r_Z);
+ tcg_gen_or_tl(dst, dst, cpu_tmp0);
}
// C
// !(Z | (N ^ V))
static inline void gen_op_eval_bg(TCGv dst, TCGv src)
{
- TCGv r_flag;
-
- r_flag = tcg_temp_new(TCG_TYPE_TL);
- gen_mov_reg_N(r_flag, src);
+ gen_mov_reg_N(cpu_tmp0, src);
gen_mov_reg_V(dst, src);
- tcg_gen_xor_tl(dst, dst, r_flag);
- gen_mov_reg_Z(r_flag, src);
- tcg_gen_or_tl(dst, dst, r_flag);
+ tcg_gen_xor_tl(dst, dst, cpu_tmp0);
+ gen_mov_reg_Z(cpu_tmp0, src);
+ tcg_gen_or_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
// !(N ^ V)
static inline void gen_op_eval_bge(TCGv dst, TCGv src)
{
- TCGv r_V;
-
- r_V = tcg_temp_new(TCG_TYPE_TL);
- gen_mov_reg_V(r_V, src);
+ gen_mov_reg_V(cpu_tmp0, src);
gen_mov_reg_N(dst, src);
- tcg_gen_xor_tl(dst, dst, r_V);
+ tcg_gen_xor_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
// !(C | Z)
static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
{
- TCGv r_Z;
-
- r_Z = tcg_temp_new(TCG_TYPE_TL);
- gen_mov_reg_Z(r_Z, src);
+ gen_mov_reg_Z(cpu_tmp0, src);
gen_mov_reg_C(dst, src);
- tcg_gen_or_tl(dst, dst, r_Z);
+ tcg_gen_or_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
unsigned int fcc_offset)
{
- tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
+ tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_shri_tl(reg, reg, 10 + fcc_offset);
tcg_gen_andi_tl(reg, reg, 0x1);
}
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
unsigned int fcc_offset)
{
- tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
+ tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_shri_tl(reg, reg, 11 + fcc_offset);
tcg_gen_andi_tl(reg, reg, 0x1);
}
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_or_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_or_tl(dst, dst, cpu_tmp0);
}
// 1 or 2: FCC0 ^ FCC1
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_xor_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_xor_tl(dst, dst, cpu_tmp0);
}
// 1 or 3: FCC0
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
- tcg_gen_and_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
+ tcg_gen_and_tl(dst, dst, cpu_tmp0);
}
// 2 or 3: FCC1
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
tcg_gen_xori_tl(dst, dst, 0x1);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_and_tl(dst, dst, cpu_tmp0);
}
// 3: FCC0 & FCC1
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_and_tl(dst, dst, cpu_tmp0);
}
// 0: !(FCC0 | FCC1)
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_or_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_or_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_xor_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_xor_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
- tcg_gen_and_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
+ tcg_gen_and_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
tcg_gen_xori_tl(dst, dst, 0x1);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_and_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
unsigned int fcc_offset)
{
- TCGv r_fcc1;
-
- r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
gen_mov_reg_FCC0(dst, src, fcc_offset);
- gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
- tcg_gen_and_tl(dst, dst, r_fcc1);
+ gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
+ tcg_gen_and_tl(dst, dst, cpu_tmp0);
tcg_gen_xori_tl(dst, dst, 0x1);
}
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
target_ulong pc2, TCGv r_cond)
{
- TCGv r_zero;
int l1;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
gen_goto_tb(dc, 0, pc1, pc1 + 4);
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
target_ulong pc2, TCGv r_cond)
{
- TCGv r_zero;
int l1;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
gen_goto_tb(dc, 0, pc2, pc1);
gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
}
-static inline void gen_branch(DisasContext *dc, target_ulong pc,
- target_ulong npc)
-{
- gen_goto_tb(dc, 0, pc, npc);
-}
-
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
TCGv r_cond)
{
- TCGv r_zero;
int l1, l2;
l1 = gen_new_label();
l2 = gen_new_label();
- r_zero = tcg_const_tl(0);
- tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
- gen_movl_npc_im(npc1);
- gen_op_jmp_label(l2);
+ tcg_gen_movi_tl(cpu_npc, npc1);
+ tcg_gen_br(l2);
gen_set_label(l1);
- gen_movl_npc_im(npc2);
+ tcg_gen_movi_tl(cpu_npc, npc2);
gen_set_label(l2);
}
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
dc->npc = DYNAMIC_PC;
} else if (dc->npc != DYNAMIC_PC) {
- gen_movl_npc_im(dc->npc);
+ tcg_gen_movi_tl(cpu_npc, dc->npc);
}
}
static inline void save_state(DisasContext * dc)
{
- gen_jmp_im(dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
save_npc(dc);
}
{
if (dc->npc == JUMP_PC) {
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
- tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
dc->pc = DYNAMIC_PC;
} else if (dc->npc == DYNAMIC_PC) {
- tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
dc->pc = DYNAMIC_PC;
} else {
dc->pc = dc->npc;
static inline void gen_op_next_insn(void)
{
- tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
- tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
+ tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
}
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
static inline void gen_cond_reg(TCGv r_dst, int cond)
{
- TCGv r_zero;
int l1;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
- tcg_gen_mov_tl(r_dst, r_zero);
- tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
+ tcg_gen_movi_tl(r_dst, 0);
+ tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1);
tcg_gen_movi_tl(r_dst, 1);
gen_set_label(l1);
}
{
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
- gen_op_exception(TT_FP_EXCP);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
}
static int gen_trap_ifnofpu(DisasContext * dc)
#if !defined(CONFIG_USER_ONLY)
if (!dc->fpu_enabled) {
save_state(dc);
- gen_op_exception(TT_NFPU_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
dc->is_br = 1;
return 1;
}
tcg_gen_helper_0_0(helper_clear_float_exceptions);
}
+static inline void gen_check_align(TCGv r_addr, int align)
+{
+ tcg_gen_helper_0_2(helper_check_align, r_addr, tcg_const_i32(align));
+}
+
+static inline void gen_op_check_align_T0_1(void)
+{
+ gen_check_align(cpu_T[0], 1);
+}
+
+static inline void gen_op_check_align_T0_3(void)
+{
+ gen_check_align(cpu_T[0], 3);
+}
+
+static inline void gen_op_check_align_T0_7(void)
+{
+ gen_check_align(cpu_T[0], 7);
+}
+
/* asi moves */
#ifdef TARGET_SPARC64
-static inline void gen_ld_asi(int insn, int size, int sign)
+static inline TCGv gen_get_asi(int insn, TCGv r_addr)
{
int asi, offset;
- TCGv r_size, r_sign;
+ TCGv r_asi;
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_sign = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_size, size);
- tcg_gen_movi_i32(r_sign, sign);
if (IS_IMM) {
+ r_asi = tcg_temp_new(TCG_TYPE_I32);
offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
+ tcg_gen_addi_tl(r_addr, r_addr, offset);
+ tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
} else {
asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(cpu_T[1], asi);
+ r_asi = tcg_const_i32(asi);
}
- tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,
- r_sign);
+ return r_asi;
+}
+
+static inline void gen_ld_asi(int insn, int size, int sign)
+{
+ TCGv r_asi;
+
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi,
+ tcg_const_i32(size), tcg_const_i32(sign));
+ tcg_gen_discard_i32(r_asi);
}
static inline void gen_st_asi(int insn, int size)
{
- int asi, offset;
- TCGv r_asi, r_size;
+ TCGv r_asi;
- r_asi = tcg_temp_new(TCG_TYPE_I32);
- r_size = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_size, size);
- if (IS_IMM) {
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
- } else {
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_asi, asi);
- }
- tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi,
+ tcg_const_i32(size));
+ tcg_gen_discard_i32(r_asi);
}
static inline void gen_ldf_asi(int insn, int size, int rd)
{
- int asi, offset;
- TCGv r_asi, r_size, r_rd;
+ TCGv r_asi;
- r_asi = tcg_temp_new(TCG_TYPE_I32);
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_rd = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_size, size);
- tcg_gen_movi_i32(r_rd, rd);
- if (IS_IMM) {
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
- } else {
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_asi, asi);
- }
- tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd);
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
+ tcg_const_i32(rd));
+ tcg_gen_discard_i32(r_asi);
}
static inline void gen_stf_asi(int insn, int size, int rd)
{
- int asi, offset;
- TCGv r_asi, r_size, r_rd;
+ TCGv r_asi;
- r_asi = tcg_temp_new(TCG_TYPE_I32);
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_rd = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_size, size);
- tcg_gen_movi_i32(r_rd, rd);
- if (IS_IMM) {
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
- } else {
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_asi, asi);
- }
- tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd);
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
+ tcg_const_i32(rd));
+ tcg_gen_discard_i32(r_asi);
}
static inline void gen_swap_asi(int insn)
{
- int asi, offset;
- TCGv r_size, r_sign, r_temp;
+ TCGv r_temp, r_asi;
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_sign = tcg_temp_new(TCG_TYPE_I32);
r_temp = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_size, 4);
- tcg_gen_movi_i32(r_sign, 0);
- if (IS_IMM) {
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
- } else {
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(cpu_T[1], asi);
- }
- tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
- r_sign);
- tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
- tcg_gen_mov_i32(cpu_T[1], r_temp);
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi,
+ tcg_const_i32(4), tcg_const_i32(0));
+ tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi,
+ tcg_const_i32(4));
+ tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
+ tcg_gen_discard_i32(r_asi);
+ tcg_gen_discard_i32(r_temp);
}
static inline void gen_ldda_asi(int insn)
{
- int asi, offset;
- TCGv r_size, r_sign, r_dword;
+ TCGv r_asi;
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_sign = tcg_temp_new(TCG_TYPE_I32);
- r_dword = tcg_temp_new(TCG_TYPE_I64);
- tcg_gen_movi_i32(r_size, 8);
- tcg_gen_movi_i32(r_sign, 0);
- if (IS_IMM) {
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
- } else {
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(cpu_T[1], asi);
- }
- tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
- r_sign);
- tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
- tcg_gen_shri_i64(r_dword, r_dword, 32);
- tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], r_asi,
+ tcg_const_i32(8), tcg_const_i32(0));
+ tcg_gen_andi_i64(cpu_T[0], cpu_tmp64, 0xffffffffULL);
+ tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
+ tcg_gen_andi_i64(cpu_T[1], cpu_tmp64, 0xffffffffULL);
+ tcg_gen_discard_i32(r_asi);
+}
+
+static inline void gen_stda_asi(int insn, int rd)
+{
+ TCGv r_temp, r_asi;
+
+ r_temp = tcg_temp_new(TCG_TYPE_I32);
+ gen_movl_reg_TN(rd + 1, r_temp);
+ tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
+ r_temp);
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, r_asi,
+ tcg_const_i32(8));
+ tcg_gen_discard_i32(r_asi);
+ tcg_gen_discard_i32(r_temp);
}
static inline void gen_cas_asi(int insn, int rd)
{
- int asi, offset;
TCGv r_val1, r_asi;
r_val1 = tcg_temp_new(TCG_TYPE_I32);
- r_asi = tcg_temp_new(TCG_TYPE_I32);
gen_movl_reg_TN(rd, r_val1);
- if (IS_IMM) {
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
- } else {
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_asi, asi);
- }
+ r_asi = gen_get_asi(insn, cpu_T[0]);
tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
r_asi);
+ tcg_gen_discard_i32(r_asi);
+ tcg_gen_discard_i32(r_val1);
}
static inline void gen_casx_asi(int insn, int rd)
{
- int asi, offset;
- TCGv r_val1, r_asi;
+ TCGv r_asi;
- r_val1 = tcg_temp_new(TCG_TYPE_I64);
- r_asi = tcg_temp_new(TCG_TYPE_I32);
- gen_movl_reg_TN(rd, r_val1);
- if (IS_IMM) {
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
- } else {
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_asi, asi);
- }
- tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
+ gen_movl_reg_TN(rd, cpu_tmp64);
+ r_asi = gen_get_asi(insn, cpu_T[0]);
+ tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], cpu_tmp64, cpu_T[1],
r_asi);
+ tcg_gen_discard_i32(r_asi);
}
#elif !defined(CONFIG_USER_ONLY)
static inline void gen_ld_asi(int insn, int size, int sign)
{
int asi;
- TCGv r_size, r_sign, r_dword;
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_sign = tcg_temp_new(TCG_TYPE_I32);
- r_dword = tcg_temp_new(TCG_TYPE_I64);
- tcg_gen_movi_i32(r_size, size);
- tcg_gen_movi_i32(r_sign, sign);
asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(cpu_T[1], asi);
- tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
- r_sign);
- tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
+ tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
+ tcg_const_i32(size), tcg_const_i32(sign));
+ tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
}
static inline void gen_st_asi(int insn, int size)
{
int asi;
- TCGv r_dword, r_asi, r_size;
- r_dword = tcg_temp_new(TCG_TYPE_I64);
- tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
- r_asi = tcg_temp_new(TCG_TYPE_I32);
- r_size = tcg_temp_new(TCG_TYPE_I32);
+ tcg_gen_extu_tl_i64(cpu_tmp64, cpu_T[1]);
asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_asi, asi);
- tcg_gen_movi_i32(r_size, size);
- tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
+ tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
+ tcg_const_i32(size));
}
static inline void gen_swap_asi(int insn)
{
int asi;
- TCGv r_size, r_sign, r_temp;
+ TCGv r_temp;
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_sign = tcg_temp_new(TCG_TYPE_I32);
r_temp = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_size, 4);
- tcg_gen_movi_i32(r_sign, 0);
asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(cpu_T[1], asi);
- tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
- r_sign);
- tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
- tcg_gen_mov_i32(cpu_T[1], r_temp);
+ tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi),
+ tcg_const_i32(4), tcg_const_i32(0));
+ tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi),
+ tcg_const_i32(4));
+ tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
+ tcg_gen_discard_i32(r_temp);
}
static inline void gen_ldda_asi(int insn)
{
int asi;
- TCGv r_size, r_sign, r_dword;
- r_size = tcg_temp_new(TCG_TYPE_I32);
- r_sign = tcg_temp_new(TCG_TYPE_I32);
- r_dword = tcg_temp_new(TCG_TYPE_I64);
- tcg_gen_movi_i32(r_size, 8);
- tcg_gen_movi_i32(r_sign, 0);
asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(cpu_T[1], asi);
- tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
- r_sign);
- tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
- tcg_gen_shri_i64(r_dword, r_dword, 32);
- tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
+ tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
+ tcg_const_i32(8), tcg_const_i32(0));
+ tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
+ tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
+ tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
+}
+
+static inline void gen_stda_asi(int insn, int rd)
+{
+ int asi;
+ TCGv r_temp;
+
+ r_temp = tcg_temp_new(TCG_TYPE_I32);
+ gen_movl_reg_TN(rd + 1, r_temp);
+ tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1], r_temp);
+ asi = GET_FIELD(insn, 19, 26);
+ tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
+ tcg_const_i32(8));
}
#endif
static inline void gen_ldstub_asi(int insn)
{
int asi;
- TCGv r_dword, r_asi, r_size;
gen_ld_asi(insn, 1, 0);
- r_dword = tcg_temp_new(TCG_TYPE_I64);
- r_asi = tcg_temp_new(TCG_TYPE_I32);
- r_size = tcg_temp_new(TCG_TYPE_I32);
asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_dword, 0xff);
- tcg_gen_movi_i32(r_asi, asi);
- tcg_gen_movi_i32(r_size, 1);
- tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
+ tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xffULL),
+ tcg_const_i32(asi), tcg_const_i32(1));
}
#endif
target = sign_extend(target, 16);
target <<= 2;
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
do_branch_reg(dc, target, insn);
goto jmp_insn;
}
#endif
uint32_t value = GET_FIELD(insn, 10, 31);
tcg_gen_movi_tl(cpu_T[0], value << 10);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
#if defined(OPTIM)
}
#endif
/*CALL*/ {
target_long target = GET_FIELDs(insn, 2, 31) << 2;
- tcg_gen_movi_tl(cpu_T[0], dc->pc);
- gen_movl_T0_reg(15);
+ gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
target += dc->pc;
gen_mov_pc_npc(dc);
dc->npc = target;
int cond;
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) {
rs2 = GET_FIELD(insn, 25, 31);
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
#if defined(OPTIM)
if (rs2 != 0) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
gen_cond(r_cond, 0, cond);
#endif
tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
+ tcg_gen_discard_tl(r_cond);
}
gen_op_next_insn();
tcg_gen_exit_tb(0);
SPARCv8 manual, rdy on the
microSPARC II */
#endif
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, y));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */
- gen_op_rdccr();
- gen_movl_T0_reg(rd);
+ tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x3: /* V9 rdasi */
- gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x4: /* V9 rdtick */
{
offsetof(CPUState, tick));
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
r_tickptr);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
case 0x5: /* V9 rdpc */
tcg_gen_movi_tl(cpu_T[0], dc->pc);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x6: /* V9 rdfprs */
- gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0xf: /* V9 membar */
break; /* no effect */
case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x17: /* Tick compare */
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tick_cmpr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x18: /* System tick */
{
offsetof(CPUState, stick));
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
r_tickptr);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
case 0x19: /* System tick compare */
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, stick_cmpr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x10: /* Performance Control */
case 0x11: /* Performance Instrumentation Counter */
// gen_op_rdhtstate();
break;
case 3: // hintp
- gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 5: // htba
- gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 6: // hver
- gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 31: // hstick_cmpr
- gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
break;
default:
goto illegal_insn;
}
#endif
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
if (!supervisor(dc))
offsetof(CPUState, tsptr));
tcg_gen_ld_tl(cpu_T[0], r_tsptr,
offsetof(trap_state, tpc));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 1: // tnpc
offsetof(CPUState, tsptr));
tcg_gen_ld_tl(cpu_T[0], r_tsptr,
offsetof(trap_state, tnpc));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 2: // tstate
offsetof(CPUState, tsptr));
tcg_gen_ld_tl(cpu_T[0], r_tsptr,
offsetof(trap_state, tstate));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 3: // tt
offsetof(CPUState, tsptr));
tcg_gen_ld_i32(cpu_T[0], r_tsptr,
offsetof(trap_state, tt));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 4: // tick
offsetof(CPUState, tick));
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
r_tickptr);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
case 5: // tba
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
break;
case 6: // pstate
- gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 7: // tl
- gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 8: // pil
- gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 9: // cwp
- gen_op_rdcwp();
+ tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]);
break;
case 10: // cansave
- gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 11: // canrestore
- gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 12: // cleanwin
- gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 13: // otherwin
- gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 14: // wstate
- gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 16: // UA2005 gl
- gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 26: // UA2005 strand status
if (!hypervisor(dc))
goto priv_insn;
- gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
break;
case 31: // ver
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, version));
break;
case 15: // fq
default:
goto illegal_insn;
}
#else
- gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
+ tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
#endif
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
#ifdef TARGET_SPARC64
- gen_op_flushw();
+ tcg_gen_helper_0_0(helper_flushw);
#else
if (!supervisor(dc))
goto priv_insn;
- gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
- gen_movl_T0_reg(rd);
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
+ gen_movl_TN_reg(rd, cpu_T[0]);
#endif
break;
#endif
break;
case 0x5: /* fnegs */
gen_op_load_fpr_FT1(rs2);
- gen_op_fnegs();
+ tcg_gen_helper_0_0(helper_fnegs);
gen_op_store_FT0_fpr(rd);
break;
case 0x9: /* fabss */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fadds();
+ tcg_gen_helper_0_0(helper_fadds);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_faddd();
+ tcg_gen_helper_0_0(helper_faddd);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_faddq();
+ tcg_gen_helper_0_0(helper_faddq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fsubs();
+ tcg_gen_helper_0_0(helper_fsubs);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fsubd();
+ tcg_gen_helper_0_0(helper_fsubd);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fsubq();
+ tcg_gen_helper_0_0(helper_fsubq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fmuls();
+ tcg_gen_helper_0_0(helper_fmuls);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fmuld();
+ tcg_gen_helper_0_0(helper_fmuld);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fmulq();
+ tcg_gen_helper_0_0(helper_fmulq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fdivs();
+ tcg_gen_helper_0_0(helper_fdivs);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fdivd();
+ tcg_gen_helper_0_0(helper_fdivd);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fdivq();
+ tcg_gen_helper_0_0(helper_fdivq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fsmuld();
+ tcg_gen_helper_0_0(helper_fsmuld);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fdmulq();
+ tcg_gen_helper_0_0(helper_fdmulq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
case 0xc4:
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fitos();
+ tcg_gen_helper_0_0(helper_fitos);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
case 0xc6:
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fdtos();
+ tcg_gen_helper_0_0(helper_fdtos);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fqtos();
+ tcg_gen_helper_0_0(helper_fqtos);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
#endif
case 0xc8:
gen_op_load_fpr_FT1(rs2);
- gen_op_fitod();
+ tcg_gen_helper_0_0(helper_fitod);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0xc9:
gen_op_load_fpr_FT1(rs2);
- gen_op_fstod();
+ tcg_gen_helper_0_0(helper_fstod);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0xcb: /* fqtod */
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fqtod();
+ tcg_gen_helper_0_0(helper_fqtod);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0xcc: /* fitoq */
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_FT1(rs2);
- gen_op_fitoq();
+ tcg_gen_helper_0_0(helper_fitoq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
#else
case 0xcd: /* fstoq */
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_FT1(rs2);
- gen_op_fstoq();
+ tcg_gen_helper_0_0(helper_fstoq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
#else
case 0xce: /* fdtoq */
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fdtoq();
+ tcg_gen_helper_0_0(helper_fdtoq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
#else
case 0xd1:
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fstoi();
+ tcg_gen_helper_0_0(helper_fstoi);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
case 0xd2:
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fdtoi();
+ tcg_gen_helper_0_0(helper_fdtoi);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fqtoi();
+ tcg_gen_helper_0_0(helper_fqtoi);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
#endif
case 0x6: /* V9 fnegd */
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fnegd();
+ tcg_gen_helper_0_0(helper_fnegd);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x7: /* V9 fnegq */
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_op_fnegq();
+ tcg_gen_helper_0_0(helper_fnegq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
#else
case 0x81: /* V9 fstox */
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- gen_op_fstox();
+ tcg_gen_helper_0_0(helper_fstox);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x82: /* V9 fdtox */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fdtox();
+ tcg_gen_helper_0_0(helper_fdtox);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fqtox();
+ tcg_gen_helper_0_0(helper_fqtox);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x84: /* V9 fxtos */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fxtos();
+ tcg_gen_helper_0_0(helper_fxtos);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
case 0x88: /* V9 fxtod */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fxtod();
+ tcg_gen_helper_0_0(helper_fxtod);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
#if defined(CONFIG_USER_ONLY)
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- gen_op_fxtoq();
+ tcg_gen_helper_0_0(helper_fxtoq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
xop = GET_FIELD(insn, 18, 26);
#ifdef TARGET_SPARC64
if ((xop & 0x11f) == 0x005) { // V9 fmovsr
- TCGv r_zero;
int l1;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
cond = GET_FIELD_SP(insn, 14, 17);
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
+ tcg_const_tl(0), l1);
gen_op_load_fpr_FT0(rs2);
gen_op_store_FT0_fpr(rd);
gen_set_label(l1);
break;
} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
- TCGv r_zero;
int l1;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
cond = GET_FIELD_SP(insn, 14, 17);
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
+ tcg_const_tl(0), l1);
gen_op_load_fpr_DT0(DFPREG(rs2));
gen_op_store_DT0_fpr(DFPREG(rd));
gen_set_label(l1);
break;
} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
#if defined(CONFIG_USER_ONLY)
- TCGv r_zero;
int l1;
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
cond = GET_FIELD_SP(insn, 14, 17);
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
- tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
+ tcg_const_tl(0), l1);
gen_op_load_fpr_QT0(QFPREG(rs2));
gen_op_store_QT0_fpr(QFPREG(rd));
gen_set_label(l1);
#ifdef TARGET_SPARC64
#define FMOVCC(size_FDQ, fcc) \
{ \
- TCGv r_zero, r_cond; \
+ TCGv r_cond; \
int l1; \
\
l1 = gen_new_label(); \
- r_zero = tcg_const_tl(0); \
r_cond = tcg_temp_new(TCG_TYPE_TL); \
cond = GET_FIELD_SP(insn, 14, 17); \
gen_fcond(r_cond, fcc, cond); \
- tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
+ tcg_const_tl(0), l1); \
glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
gen_set_label(l1); \
+ tcg_gen_discard_tl(r_cond); \
}
case 0x001: /* V9 fmovscc %fcc0 */
FMOVCC(F, 0);
#undef FMOVCC
#define FMOVCC(size_FDQ, icc) \
{ \
- TCGv r_zero, r_cond; \
+ TCGv r_cond; \
int l1; \
\
l1 = gen_new_label(); \
- r_zero = tcg_const_tl(0); \
r_cond = tcg_temp_new(TCG_TYPE_TL); \
cond = GET_FIELD_SP(insn, 14, 17); \
gen_cond(r_cond, icc, cond); \
- tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
+ tcg_const_tl(0), l1); \
glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
gen_set_label(l1); \
+ tcg_gen_discard_tl(r_cond); \
}
case 0x101: /* V9 fmovscc %icc */
tcg_gen_movi_tl(cpu_T[0], (int)rs2);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T0(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[0]);
}
} else {
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
// or x, %g0, y -> mov T1, x; mov y, T1
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 != 0) {
- gen_movl_reg_T1(rs2);
- gen_op_or_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
#endif
#ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
} else if (xop == 0x26) { /* srl, V9 srlx */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
} else if (xop == 0x27) { /* sra, V9 srax */
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
}
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
#endif
} else if (xop < 0x36) {
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
if (xop < 0x20) {
switch (xop & ~0x10) {
if (xop & 0x10)
gen_op_add_T1_T0_cc();
else
- gen_op_add_T1_T0();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
break;
case 0x1:
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
break;
#ifdef TARGET_SPARC64
case 0xd: /* V9 udivx */
- gen_trap_ifdivzero_i64(cpu_T[1]);
+ gen_trap_ifdivzero_tl(cpu_T[1]);
tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
break;
#endif
case 0xe:
- gen_op_udiv_T1_T0();
+ tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);
if (xop & 0x10)
gen_op_div_cc();
break;
case 0xf:
- gen_op_sdiv_T1_T0();
+ tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);
if (xop & 0x10)
gen_op_div_cc();
break;
default:
goto illegal_insn;
}
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
} else {
switch (xop) {
case 0x20: /* taddcc */
gen_op_tadd_T1_T0_cc();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x21: /* tsubcc */
gen_op_tsub_T1_T0_cc();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x22: /* taddcctv */
save_state(dc);
gen_op_tadd_T1_T0_ccTV();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x23: /* tsubcctv */
save_state(dc);
gen_op_tsub_T1_T0_ccTV();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x24: /* mulscc */
gen_op_mulscc_T1_T0();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#ifndef TARGET_SPARC64
case 0x25: /* sll */
- tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
- tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_movl_T0_reg(rd);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
+ tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x26: /* srl */
- tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
- tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_movl_T0_reg(rd);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x27: /* sra */
- tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
- tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_movl_T0_reg(rd);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
+ tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#endif
case 0x30:
{
switch(rd) {
case 0: /* wry */
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, y));
break;
#ifndef TARGET_SPARC64
case 0x01 ... 0x0f: /* undefined in the
break;
#else
case 0x2: /* V9 wrccr */
- gen_op_xor_T1_T0();
- gen_op_wrccr();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]);
break;
case 0x3: /* V9 wrasi */
- gen_op_xor_T1_T0();
- gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
break;
case 0x6: /* V9 wrfprs */
- gen_op_xor_T1_T0();
- gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
break;
case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
{
TCGv r_tickptr;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState,
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
tick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, tick));
tcg_gen_helper_0_2(helper_tick_set_limit,
r_tickptr, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
case 0x18: /* System tick */
{
TCGv r_tickptr;
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
+ cpu_T[1]);
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, stick));
tcg_gen_helper_0_2(helper_tick_set_count,
r_tickptr, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
case 0x19: /* System tick compare */
{
TCGv r_tickptr;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState,
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
stick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, stick));
tcg_gen_helper_0_2(helper_tick_set_limit,
r_tickptr, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
#ifdef TARGET_SPARC64
switch (rd) {
case 0:
- gen_op_saved();
+ tcg_gen_helper_0_0(helper_saved);
break;
case 1:
- gen_op_restored();
+ tcg_gen_helper_0_0(helper_restored);
break;
case 2: /* UA2005 allclean */
case 3: /* UA2005 otherw */
goto illegal_insn;
}
#else
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
save_state(dc);
gen_op_next_insn();
{
if (!supervisor(dc))
goto priv_insn;
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#ifdef TARGET_SPARC64
switch (rd) {
case 0: // tpc
offsetof(CPUState, tsptr));
tcg_gen_st_tl(cpu_T[0], r_tsptr,
offsetof(trap_state, tpc));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 1: // tnpc
offsetof(CPUState, tsptr));
tcg_gen_st_tl(cpu_T[0], r_tsptr,
offsetof(trap_state, tnpc));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 2: // tstate
offsetof(CPUState, tsptr));
tcg_gen_st_tl(cpu_T[0], r_tsptr,
offsetof(trap_state, tstate));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 3: // tt
offsetof(CPUState, tsptr));
tcg_gen_st_i32(cpu_T[0], r_tsptr,
offsetof(trap_state, tt));
+ tcg_gen_discard_ptr(r_tsptr);
}
break;
case 4: // tick
offsetof(CPUState, tick));
tcg_gen_helper_0_2(helper_tick_set_count,
r_tickptr, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
case 5: // tba
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
break;
case 6: // pstate
save_state(dc);
dc->is_br = 1;
break;
case 7: // tl
- gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
break;
case 8: // pil
- gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
break;
case 9: // cwp
- gen_op_wrcwp();
+ tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]);
break;
case 10: // cansave
- gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
break;
case 11: // canrestore
- gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
break;
case 12: // cleanwin
- gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
break;
case 13: // otherwin
- gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
break;
case 14: // wstate
- gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
break;
case 16: // UA2005 gl
- gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
break;
case 26: // UA2005 strand status
if (!hypervisor(dc))
goto priv_insn;
- gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
break;
default:
goto illegal_insn;
}
#else
- tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
- gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
#endif
}
break;
#ifndef TARGET_SPARC64
if (!supervisor(dc))
goto priv_insn;
- gen_op_xor_T1_T0();
- gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
#else
if (!hypervisor(dc))
goto priv_insn;
- gen_op_xor_T1_T0();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
switch (rd) {
case 0: // hpstate
// XXX gen_op_wrhpstate();
// XXX gen_op_wrhtstate();
break;
case 3: // hintp
- gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
break;
case 5: // htba
- gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
break;
case 31: // hstick_cmpr
{
TCGv r_tickptr;
- gen_op_movtl_env_T0(offsetof(CPUSPARCState,
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
hstick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, hstick));
tcg_gen_helper_0_2(helper_tick_set_limit,
r_tickptr, cpu_T[0]);
+ tcg_gen_discard_ptr(r_tickptr);
}
break;
case 6: // hver readonly
tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 10);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
gen_set_label(l1);
+ tcg_gen_discard_tl(r_cond);
break;
}
case 0x2d: /* V9 sdivx */
gen_op_sdivx_T1_T0();
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x2e: /* V9 popc */
{
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 12);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
// XXX optimize: popc(constant)
}
else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
tcg_gen_helper_1_1(helper_popc, cpu_T[0],
cpu_T[1]);
- gen_movl_T0_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[0]);
}
case 0x2f: /* V9 movr */
{
int cond = GET_FIELD_SP(insn, 10, 12);
- TCGv r_zero;
int l1;
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
l1 = gen_new_label();
- r_zero = tcg_const_tl(0);
- tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
+ tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
+ tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 9);
- gen_movl_simm_T1(rs2);
+ tcg_gen_movi_tl(cpu_T[1], (int)rs2);
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
gen_set_label(l1);
break;
}
// XXX
goto illegal_insn;
case 0x010: /* VIS I array8 */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
- gen_op_array8();
- gen_movl_T0_reg(rd);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x012: /* VIS I array16 */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
- gen_op_array16();
- gen_movl_T0_reg(rd);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x014: /* VIS I array32 */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
- gen_op_array32();
- gen_movl_T0_reg(rd);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x018: /* VIS I alignaddr */
- gen_movl_reg_T0(rs1);
- gen_movl_reg_T1(rs2);
- gen_op_alignaddr();
- gen_movl_T0_reg(rd);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0],
+ cpu_T[1]);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x019: /* VIS II bmask */
case 0x01a: /* VIS I alignaddrl */
case 0x020: /* VIS I fcmple16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmple16();
+ tcg_gen_helper_0_0(helper_fcmple16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x022: /* VIS I fcmpne16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmpne16();
+ tcg_gen_helper_0_0(helper_fcmpne16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x024: /* VIS I fcmple32 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmple32();
+ tcg_gen_helper_0_0(helper_fcmple32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x026: /* VIS I fcmpne32 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmpne32();
+ tcg_gen_helper_0_0(helper_fcmpne32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x028: /* VIS I fcmpgt16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmpgt16();
+ tcg_gen_helper_0_0(helper_fcmpgt16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x02a: /* VIS I fcmpeq16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmpeq16();
+ tcg_gen_helper_0_0(helper_fcmpeq16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x02c: /* VIS I fcmpgt32 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmpgt32();
+ tcg_gen_helper_0_0(helper_fcmpgt32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x02e: /* VIS I fcmpeq32 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fcmpeq32();
+ tcg_gen_helper_0_0(helper_fcmpeq32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x031: /* VIS I fmul8x16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmul8x16();
+ tcg_gen_helper_0_0(helper_fmul8x16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x033: /* VIS I fmul8x16au */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmul8x16au();
+ tcg_gen_helper_0_0(helper_fmul8x16au);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x035: /* VIS I fmul8x16al */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmul8x16al();
+ tcg_gen_helper_0_0(helper_fmul8x16al);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x036: /* VIS I fmul8sux16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmul8sux16();
+ tcg_gen_helper_0_0(helper_fmul8sux16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x037: /* VIS I fmul8ulx16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmul8ulx16();
+ tcg_gen_helper_0_0(helper_fmul8ulx16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x038: /* VIS I fmuld8sux16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmuld8sux16();
+ tcg_gen_helper_0_0(helper_fmuld8sux16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x039: /* VIS I fmuld8ulx16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fmuld8ulx16();
+ tcg_gen_helper_0_0(helper_fmuld8ulx16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x03a: /* VIS I fpack32 */
case 0x048: /* VIS I faligndata */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_faligndata();
+ tcg_gen_helper_0_0(helper_faligndata);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x04b: /* VIS I fpmerge */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fpmerge();
+ tcg_gen_helper_0_0(helper_fpmerge);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x04c: /* VIS II bshuffle */
case 0x04d: /* VIS I fexpand */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fexpand();
+ tcg_gen_helper_0_0(helper_fexpand);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x050: /* VIS I fpadd16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fpadd16();
+ tcg_gen_helper_0_0(helper_fpadd16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x051: /* VIS I fpadd16s */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fpadd16s();
+ tcg_gen_helper_0_0(helper_fpadd16s);
gen_op_store_FT0_fpr(rd);
break;
case 0x052: /* VIS I fpadd32 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fpadd32();
+ tcg_gen_helper_0_0(helper_fpadd32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x053: /* VIS I fpadd32s */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fpadd32s();
+ tcg_gen_helper_0_0(helper_fpadd32s);
gen_op_store_FT0_fpr(rd);
break;
case 0x054: /* VIS I fpsub16 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fpsub16();
+ tcg_gen_helper_0_0(helper_fpsub16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x055: /* VIS I fpsub16s */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fpsub16s();
+ tcg_gen_helper_0_0(helper_fpsub16s);
gen_op_store_FT0_fpr(rd);
break;
case 0x056: /* VIS I fpsub32 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fpadd32();
+ tcg_gen_helper_0_0(helper_fpadd32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x057: /* VIS I fpsub32s */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fpsub32s();
+ tcg_gen_helper_0_0(helper_fpsub32s);
gen_op_store_FT0_fpr(rd);
break;
case 0x060: /* VIS I fzero */
- gen_op_movl_DT0_0();
+ tcg_gen_helper_0_0(helper_movl_DT0_0);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x061: /* VIS I fzeros */
- gen_op_movl_FT0_0();
+ tcg_gen_helper_0_0(helper_movl_FT0_0);
gen_op_store_FT0_fpr(rd);
break;
case 0x062: /* VIS I fnor */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fnor();
+ tcg_gen_helper_0_0(helper_fnor);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x063: /* VIS I fnors */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fnors();
+ tcg_gen_helper_0_0(helper_fnors);
gen_op_store_FT0_fpr(rd);
break;
case 0x064: /* VIS I fandnot2 */
gen_op_load_fpr_DT1(DFPREG(rs1));
gen_op_load_fpr_DT0(DFPREG(rs2));
- gen_op_fandnot();
+ tcg_gen_helper_0_0(helper_fandnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x065: /* VIS I fandnot2s */
gen_op_load_fpr_FT1(rs1);
gen_op_load_fpr_FT0(rs2);
- gen_op_fandnots();
+ tcg_gen_helper_0_0(helper_fandnots);
gen_op_store_FT0_fpr(rd);
break;
case 0x066: /* VIS I fnot2 */
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fnot();
+ tcg_gen_helper_0_0(helper_fnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x067: /* VIS I fnot2s */
gen_op_load_fpr_FT1(rs2);
- gen_op_fnot();
+ tcg_gen_helper_0_0(helper_fnot);
gen_op_store_FT0_fpr(rd);
break;
case 0x068: /* VIS I fandnot1 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fandnot();
+ tcg_gen_helper_0_0(helper_fandnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x069: /* VIS I fandnot1s */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fandnots();
+ tcg_gen_helper_0_0(helper_fandnots);
gen_op_store_FT0_fpr(rd);
break;
case 0x06a: /* VIS I fnot1 */
gen_op_load_fpr_DT1(DFPREG(rs1));
- gen_op_fnot();
+ tcg_gen_helper_0_0(helper_fnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x06b: /* VIS I fnot1s */
gen_op_load_fpr_FT1(rs1);
- gen_op_fnot();
+ tcg_gen_helper_0_0(helper_fnot);
gen_op_store_FT0_fpr(rd);
break;
case 0x06c: /* VIS I fxor */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fxor();
+ tcg_gen_helper_0_0(helper_fxor);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x06d: /* VIS I fxors */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fxors();
+ tcg_gen_helper_0_0(helper_fxors);
gen_op_store_FT0_fpr(rd);
break;
case 0x06e: /* VIS I fnand */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fnand();
+ tcg_gen_helper_0_0(helper_fnand);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x06f: /* VIS I fnands */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fnands();
+ tcg_gen_helper_0_0(helper_fnands);
gen_op_store_FT0_fpr(rd);
break;
case 0x070: /* VIS I fand */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fand();
+ tcg_gen_helper_0_0(helper_fand);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x071: /* VIS I fands */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fands();
+ tcg_gen_helper_0_0(helper_fands);
gen_op_store_FT0_fpr(rd);
break;
case 0x072: /* VIS I fxnor */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fxnor();
+ tcg_gen_helper_0_0(helper_fxnor);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x073: /* VIS I fxnors */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fxnors();
+ tcg_gen_helper_0_0(helper_fxnors);
gen_op_store_FT0_fpr(rd);
break;
case 0x074: /* VIS I fsrc1 */
case 0x076: /* VIS I fornot2 */
gen_op_load_fpr_DT1(DFPREG(rs1));
gen_op_load_fpr_DT0(DFPREG(rs2));
- gen_op_fornot();
+ tcg_gen_helper_0_0(helper_fornot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x077: /* VIS I fornot2s */
gen_op_load_fpr_FT1(rs1);
gen_op_load_fpr_FT0(rs2);
- gen_op_fornots();
+ tcg_gen_helper_0_0(helper_fornots);
gen_op_store_FT0_fpr(rd);
break;
case 0x078: /* VIS I fsrc2 */
case 0x07a: /* VIS I fornot1 */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_fornot();
+ tcg_gen_helper_0_0(helper_fornot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x07b: /* VIS I fornot1s */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fornots();
+ tcg_gen_helper_0_0(helper_fornots);
gen_op_store_FT0_fpr(rd);
break;
case 0x07c: /* VIS I for */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_op_for();
+ tcg_gen_helper_0_0(helper_for);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x07d: /* VIS I fors */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
- gen_op_fors();
+ tcg_gen_helper_0_0(helper_fors);
gen_op_store_FT0_fpr(rd);
break;
case 0x07e: /* VIS I fone */
- gen_op_movl_DT0_1();
+ tcg_gen_helper_0_0(helper_movl_DT0_1);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x07f: /* VIS I fones */
- gen_op_movl_FT0_1();
+ tcg_gen_helper_0_0(helper_movl_FT0_1);
gen_op_store_FT0_fpr(rd);
break;
case 0x080: /* VIS I shutdown */
} else if (xop == 0x39) { /* V9 return */
rs1 = GET_FIELD(insn, 13, 17);
save_state(dc);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
#if defined(OPTIM)
if (rs2) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
}
- gen_op_restore();
+ tcg_gen_helper_0_0(helper_restore);
gen_mov_pc_npc(dc);
gen_op_check_align_T0_3();
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
+ tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
dc->npc = DYNAMIC_PC;
goto jmp_insn;
#endif
} else {
rs1 = GET_FIELD(insn, 13, 17);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
#if defined(OPTIM)
if (rs2) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
{
if (rd != 0) {
tcg_gen_movi_tl(cpu_T[1], dc->pc);
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
}
gen_mov_pc_npc(dc);
gen_op_check_align_T0_3();
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
+ tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
dc->npc = DYNAMIC_PC;
}
goto jmp_insn;
goto priv_insn;
gen_mov_pc_npc(dc);
gen_op_check_align_T0_3();
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
+ tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
dc->npc = DYNAMIC_PC;
tcg_gen_helper_0_0(helper_rett);
}
break;
case 0x3c: /* save */
save_state(dc);
- gen_op_save();
- gen_movl_T0_reg(rd);
+ tcg_gen_helper_0_0(helper_save);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
case 0x3d: /* restore */
save_state(dc);
- gen_op_restore();
- gen_movl_T0_reg(rd);
+ tcg_gen_helper_0_0(helper_restore);
+ gen_movl_TN_reg(rd, cpu_T[0]);
break;
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
case 0x3e: /* V9 done/retry */
unsigned int xop = GET_FIELD(insn, 7, 12);
rs1 = GET_FIELD(insn, 13, 17);
save_state(dc);
- gen_movl_reg_T0(rs1);
+ gen_movl_reg_TN(rs1, cpu_T[0]);
if (xop == 0x3c || xop == 0x3e)
{
rs2 = GET_FIELD(insn, 27, 31);
- gen_movl_reg_T1(rs2);
+ gen_movl_reg_TN(rs2, cpu_T[1]);
}
else if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
#if defined(OPTIM)
if (rs2 != 0) {
#endif
- gen_movl_reg_T1(rs2);
- gen_op_add_T1_T0();
+ gen_movl_reg_TN(rs2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
#if defined(OPTIM)
}
#endif
if (rd & 1)
goto illegal_insn;
else {
- TCGv r_dword;
-
- r_dword = tcg_temp_new(TCG_TYPE_I64);
gen_op_check_align_T0_7();
ABI32_MASK(cpu_T[0]);
- tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
- tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
- gen_movl_T0_reg(rd + 1);
- tcg_gen_shri_i64(r_dword, r_dword, 32);
- tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
+ tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx);
+ tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffffffULL);
+ gen_movl_TN_reg(rd + 1, cpu_T[0]);
+ tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
+ tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffffffffULL);
}
break;
case 0x9: /* load signed byte */
tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
break;
case 0xd: /* ldstub -- XXX: should be atomically */
- tcg_gen_movi_i32(cpu_tmp0, 0xff);
ABI32_MASK(cpu_T[0]);
tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
- tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
+ tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_T[0], dc->mem_idx);
break;
case 0x0f: /* swap register with memory. Also atomically */
gen_op_check_align_T0_3();
- gen_movl_reg_T1(rd);
+ gen_movl_reg_TN(rd, cpu_T[1]);
ABI32_MASK(cpu_T[0]);
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
+ tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
- tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
+ tcg_gen_extu_i32_tl(cpu_T[1], cpu_tmp32);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x10: /* load word alternate */
goto illegal_insn;
gen_op_check_align_T0_7();
gen_ldda_asi(insn);
- gen_movl_T0_reg(rd + 1);
+ gen_movl_TN_reg(rd + 1, cpu_T[0]);
break;
case 0x19: /* load signed byte alternate */
#ifndef TARGET_SPARC64
goto priv_insn;
#endif
gen_op_check_align_T0_3();
- gen_movl_reg_T1(rd);
+ gen_movl_reg_TN(rd, cpu_T[1]);
gen_swap_asi(insn);
break;
default:
goto illegal_insn;
}
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
#ifdef TARGET_SPARC64
skip_move: ;
#endif
switch (xop) {
case 0x20: /* load fpreg */
gen_op_check_align_T0_3();
- gen_op_ldst(ldf);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUState, fpr[rd]));
break;
case 0x21: /* load fsr */
gen_op_check_align_T0_3();
- gen_op_ldst(ldf);
+ tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUState, ft0));
tcg_gen_helper_0_0(helper_ldfsr);
break;
case 0x22: /* load quad fpreg */
}
} else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
xop == 0xe || xop == 0x1e) {
- gen_movl_reg_T1(rd);
+ gen_movl_reg_TN(rd, cpu_T[1]);
switch (xop) {
case 0x4: /* store word */
gen_op_check_align_T0_3();
goto illegal_insn;
#ifndef __i386__
else {
- TCGv r_dword, r_low;
+ TCGv r_low;
gen_op_check_align_T0_7();
- r_dword = tcg_temp_new(TCG_TYPE_I64);
r_low = tcg_temp_new(TCG_TYPE_I32);
gen_movl_reg_TN(rd + 1, r_low);
- tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
+ tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
r_low);
- tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
+ tcg_gen_qemu_st64(cpu_tmp64, cpu_T[0], dc->mem_idx);
}
#else /* __i386__ */
gen_op_check_align_T0_7();
flush_T2(dc);
- gen_movl_reg_T2(rd + 1);
+ gen_movl_reg_TN(rd + 1, cpu_T[2]);
gen_op_ldst(std);
#endif /* __i386__ */
break;
if (rd & 1)
goto illegal_insn;
else {
- int asi;
- TCGv r_dword, r_temp, r_size;
-
gen_op_check_align_T0_7();
- r_dword = tcg_temp_new(TCG_TYPE_I64);
- r_temp = tcg_temp_new(TCG_TYPE_I32);
- r_size = tcg_temp_new(TCG_TYPE_I32);
- gen_movl_reg_TN(rd + 1, r_temp);
- tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
- r_temp);
-#ifdef TARGET_SPARC64
- if (IS_IMM) {
- int offset;
-
- offset = GET_FIELD(insn, 25, 31);
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
- tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi));
- } else {
-#endif
- asi = GET_FIELD(insn, 19, 26);
- tcg_gen_movi_i32(r_temp, asi);
-#ifdef TARGET_SPARC64
- }
-#endif
- tcg_gen_movi_i32(r_size, 8);
- tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size);
+ gen_stda_asi(insn, rd);
}
break;
#endif
if (gen_trap_ifnofpu(dc))
goto jmp_insn;
switch (xop) {
- case 0x24:
+ case 0x24: /* store fpreg */
gen_op_check_align_T0_3();
- gen_op_load_fpr_FT0(rd);
- gen_op_ldst(stf);
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUState, fpr[rd]));
+ tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
break;
case 0x25: /* stfsr, V9 stxfsr */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif
tcg_gen_helper_0_0(helper_stfsr);
- gen_op_ldst(stf);
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUState, ft0));
+ tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
break;
case 0x26:
#ifdef TARGET_SPARC64
case 0x3c: /* V9 casa */
gen_op_check_align_T0_3();
gen_cas_asi(insn, rd);
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
break;
case 0x3e: /* V9 casxa */
gen_op_check_align_T0_7();
gen_casx_asi(insn, rd);
- gen_movl_T1_reg(rd);
+ gen_movl_TN_reg(rd, cpu_T[1]);
break;
#else
case 0x34: /* stc */
return;
illegal_insn:
save_state(dc);
- gen_op_exception(TT_ILL_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
dc->is_br = 1;
return;
#if !defined(CONFIG_USER_ONLY)
priv_insn:
save_state(dc);
- gen_op_exception(TT_PRIV_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
dc->is_br = 1;
return;
nfpu_insn:
#ifndef TARGET_SPARC64
ncp_insn:
save_state(dc);
- gen_op_exception(TT_NCP_INSN);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
dc->is_br = 1;
return;
#endif
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
+ cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
+ cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
do {
if (env->nb_breakpoints > 0) {
/* if single step mode, we generate only one instruction and
generate an exception */
if (env->singlestep_enabled) {
- gen_jmp_im(dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
tcg_gen_exit_tb(0);
break;
}
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
- gen_branch(dc, dc->pc, dc->npc);
+ gen_goto_tb(dc, 0, dc->pc, dc->npc);
} else {
if (dc->pc != DYNAMIC_PC)
- gen_jmp_im(dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
save_npc(dc);
tcg_gen_exit_tb(0);
}
cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, cc_src),
"cc_src");
+ cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ offsetof(CPUState, cc_src2),
+ "cc_src2");
cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, cc_dst),
"cc_dst");
cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, fsr),
"fsr");
+ cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, pc),
+ "pc");
+ cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, npc),
+ "npc");
for (i = 1; i < 8; i++)
cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, gregs[i]),
projects / qemu.git / blobdiff