* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "sysbus.h"
-#include "qemu-timer.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
/* This device implements the per-cpu private timer and watchdog block
* which is used in both the ARM11MPCore and Cortex-A9MP.
QEMUTimer *timer;
qemu_irq irq;
MemoryRegion iomem;
-} timerblock;
+} TimerBlock;
typedef struct {
SysBusDevice busdev;
uint32_t num_cpu;
- timerblock timerblock[MAX_CPUS * 2];
- MemoryRegion iomem[2];
-} arm_mptimer_state;
+ TimerBlock timerblock[MAX_CPUS];
+ MemoryRegion iomem;
+} ARMMPTimerState;
-static inline int get_current_cpu(arm_mptimer_state *s)
+static inline int get_current_cpu(ARMMPTimerState *s)
{
- if (cpu_single_env->cpu_index >= s->num_cpu) {
+ CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
+
+ if (cpu_single_cpu->cpu_index >= s->num_cpu) {
hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
- s->num_cpu, cpu_single_env->cpu_index);
+ s->num_cpu, cpu_single_cpu->cpu_index);
}
- return cpu_single_env->cpu_index;
+ return cpu_single_cpu->cpu_index;
}
-static inline void timerblock_update_irq(timerblock *tb)
+static inline void timerblock_update_irq(TimerBlock *tb)
{
qemu_set_irq(tb->irq, tb->status);
}
/* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
-static inline uint32_t timerblock_scale(timerblock *tb)
+static inline uint32_t timerblock_scale(TimerBlock *tb)
{
return (((tb->control >> 8) & 0xff) + 1) * 10;
}
-static void timerblock_reload(timerblock *tb, int restart)
+static void timerblock_reload(TimerBlock *tb, int restart)
{
if (tb->count == 0) {
return;
static void timerblock_tick(void *opaque)
{
- timerblock *tb = (timerblock *)opaque;
+ TimerBlock *tb = (TimerBlock *)opaque;
tb->status = 1;
if (tb->control & 2) {
tb->count = tb->load;
timerblock_update_irq(tb);
}
-static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
+static uint64_t timerblock_read(void *opaque, hwaddr addr,
unsigned size)
{
- timerblock *tb = (timerblock *)opaque;
+ TimerBlock *tb = (TimerBlock *)opaque;
int64_t val;
- addr &= 0x1f;
switch (addr) {
case 0: /* Load */
return tb->load;
}
}
-static void timerblock_write(void *opaque, target_phys_addr_t addr,
+static void timerblock_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- timerblock *tb = (timerblock *)opaque;
+ TimerBlock *tb = (TimerBlock *)opaque;
int64_t old;
- addr &= 0x1f;
switch (addr) {
case 0: /* Load */
tb->load = value;
/* Wrapper functions to implement the "read timer/watchdog for
* the current CPU" memory regions.
*/
-static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
unsigned size)
{
- arm_mptimer_state *s = (arm_mptimer_state *)opaque;
+ ARMMPTimerState *s = (ARMMPTimerState *)opaque;
int id = get_current_cpu(s);
- return timerblock_read(&s->timerblock[id * 2], addr, size);
+ return timerblock_read(&s->timerblock[id], addr, size);
}
-static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
+static void arm_thistimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- arm_mptimer_state *s = (arm_mptimer_state *)opaque;
- int id = get_current_cpu(s);
- timerblock_write(&s->timerblock[id * 2], addr, value, size);
-}
-
-static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
- unsigned size)
-{
- arm_mptimer_state *s = (arm_mptimer_state *)opaque;
+ ARMMPTimerState *s = (ARMMPTimerState *)opaque;
int id = get_current_cpu(s);
- return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
-}
-
-static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
- uint64_t value, unsigned size)
-{
- arm_mptimer_state *s = (arm_mptimer_state *)opaque;
- int id = get_current_cpu(s);
- timerblock_write(&s->timerblock[id * 2 + 1], addr, value, size);
+ timerblock_write(&s->timerblock[id], addr, value, size);
}
static const MemoryRegionOps arm_thistimer_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static const MemoryRegionOps arm_thiswdog_ops = {
- .read = arm_thiswdog_read,
- .write = arm_thiswdog_write,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4,
- },
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
static const MemoryRegionOps timerblock_ops = {
.read = timerblock_read,
.write = timerblock_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void timerblock_reset(timerblock *tb)
+static void timerblock_reset(TimerBlock *tb)
{
tb->count = 0;
tb->load = 0;
tb->control = 0;
tb->status = 0;
tb->tick = 0;
+ if (tb->timer) {
+ qemu_del_timer(tb->timer);
+ }
}
static void arm_mptimer_reset(DeviceState *dev)
{
- arm_mptimer_state *s =
- FROM_SYSBUS(arm_mptimer_state, sysbus_from_qdev(dev));
+ ARMMPTimerState *s =
+ FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev));
int i;
- /* We reset every timer in the array, not just the ones we're using,
- * because vmsave will look at every array element.
- */
for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
timerblock_reset(&s->timerblock[i]);
}
static int arm_mptimer_init(SysBusDevice *dev)
{
- arm_mptimer_state *s = FROM_SYSBUS(arm_mptimer_state, dev);
+ ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev);
int i;
if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
}
- /* We implement one timer and one watchdog block per CPU, and
- * expose multiple MMIO regions:
+ /* We implement one timer block per CPU, and expose multiple MMIO regions:
* * region 0 is "timer for this core"
- * * region 1 is "watchdog for this core"
- * * region 2 is "timer for core 0"
- * * region 3 is "watchdog for core 0"
- * * region 4 is "timer for core 1"
- * * region 5 is "watchdog for core 1"
+ * * region 1 is "timer for core 0"
+ * * region 2 is "timer for core 1"
* and so on.
* The outgoing interrupt lines are
* * timer for core 0
- * * watchdog for core 0
* * timer for core 1
- * * watchdog for core 1
* and so on.
*/
- memory_region_init_io(&s->iomem[0], &arm_thistimer_ops, s,
+ memory_region_init_io(&s->iomem, &arm_thistimer_ops, s,
"arm_mptimer_timer", 0x20);
- sysbus_init_mmio(dev, &s->iomem[0]);
- memory_region_init_io(&s->iomem[1], &arm_thiswdog_ops, s,
- "arm_mptimer_wdog", 0x20);
- sysbus_init_mmio(dev, &s->iomem[1]);
- for (i = 0; i < (s->num_cpu * 2); i++) {
- timerblock *tb = &s->timerblock[i];
+ sysbus_init_mmio(dev, &s->iomem);
+ for (i = 0; i < s->num_cpu; i++) {
+ TimerBlock *tb = &s->timerblock[i];
tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
sysbus_init_irq(dev, &tb->irq);
memory_region_init_io(&tb->iomem, &timerblock_ops, tb,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
- VMSTATE_UINT32(count, timerblock),
- VMSTATE_UINT32(load, timerblock),
- VMSTATE_UINT32(control, timerblock),
- VMSTATE_UINT32(status, timerblock),
- VMSTATE_INT64(tick, timerblock),
+ VMSTATE_UINT32(count, TimerBlock),
+ VMSTATE_UINT32(load, TimerBlock),
+ VMSTATE_UINT32(control, TimerBlock),
+ VMSTATE_UINT32(status, TimerBlock),
+ VMSTATE_INT64(tick, TimerBlock),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_arm_mptimer = {
.name = "arm_mptimer",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
- VMSTATE_STRUCT_ARRAY(timerblock, arm_mptimer_state, (MAX_CPUS * 2),
- 1, vmstate_timerblock, timerblock),
+ VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
+ 2, vmstate_timerblock, TimerBlock),
VMSTATE_END_OF_LIST()
}
};
static Property arm_mptimer_properties[] = {
- DEFINE_PROP_UINT32("num-cpu", arm_mptimer_state, num_cpu, 0),
+ DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
DEFINE_PROP_END_OF_LIST()
};
dc->props = arm_mptimer_properties;
}
-static TypeInfo arm_mptimer_info = {
+static const TypeInfo arm_mptimer_info = {
.name = "arm_mptimer",
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(arm_mptimer_state),
+ .instance_size = sizeof(ARMMPTimerState),
.class_init = arm_mptimer_class_init,
};
projects / qemu.git / blobdiff