{
subpage_t *mmio = opaque;
unsigned int idx = SUBPAGE_IDX(addr);
+ uint64_t val;
+
MemoryRegionSection *section;
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
addr += mmio->base;
addr -= section->offset_within_address_space;
addr += section->offset_within_region;
- return io_mem_read(section->mr, addr, len);
+ io_mem_read(section->mr, addr, &val, len);
+ return val;
}
static void subpage_write(void *opaque, hwaddr addr,
io_mem_write(section->mr, addr, value, len);
}
+static bool subpage_accepts(void *opaque, hwaddr addr,
+ unsigned size, bool is_write)
+{
+ subpage_t *mmio = opaque;
+ unsigned int idx = SUBPAGE_IDX(addr);
+ MemoryRegionSection *section;
+#if defined(DEBUG_SUBPAGE)
+ printf("%s: subpage %p %c len %d addr " TARGET_FMT_plx
+ " idx %d\n", __func__, mmio,
+ is_write ? 'w' : 'r', len, addr, idx);
+#endif
+
+ section = &phys_sections[mmio->sub_section[idx]];
+ addr += mmio->base;
+ addr -= section->offset_within_address_space;
+ addr += section->offset_within_region;
+ return memory_region_access_valid(section->mr, addr, size, is_write);
+}
+
static const MemoryRegionOps subpage_ops = {
.read = subpage_read,
.write = subpage_write,
+ .valid.accepts = subpage_accepts,
.endianness = DEVICE_NATIVE_ENDIAN,
};
return 1;
}
-void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
+bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
int len, bool is_write)
{
hwaddr l;
uint8_t *ptr;
- uint32_t val;
+ uint64_t val;
hwaddr addr1;
MemoryRegionSection *section;
+ bool error = false;
while (len > 0) {
l = len;
if (l == 4) {
/* 32 bit write access */
val = ldl_p(buf);
- io_mem_write(section->mr, addr1, val, 4);
+ error |= io_mem_write(section->mr, addr1, val, 4);
} else if (l == 2) {
/* 16 bit write access */
val = lduw_p(buf);
- io_mem_write(section->mr, addr1, val, 2);
+ error |= io_mem_write(section->mr, addr1, val, 2);
} else {
/* 8 bit write access */
val = ldub_p(buf);
- io_mem_write(section->mr, addr1, val, 1);
+ error |= io_mem_write(section->mr, addr1, val, 1);
}
} else {
addr1 += memory_region_get_ram_addr(section->mr);
l = memory_access_size(l, addr1);
if (l == 4) {
/* 32 bit read access */
- val = io_mem_read(section->mr, addr1, 4);
+ error |= io_mem_read(section->mr, addr1, &val, 4);
stl_p(buf, val);
} else if (l == 2) {
/* 16 bit read access */
- val = io_mem_read(section->mr, addr1, 2);
+ error |= io_mem_read(section->mr, addr1, &val, 2);
stw_p(buf, val);
} else {
/* 8 bit read access */
- val = io_mem_read(section->mr, addr1, 1);
+ error |= io_mem_read(section->mr, addr1, &val, 1);
stb_p(buf, val);
}
} else {
buf += l;
addr += l;
}
+
+ return error;
}
-void address_space_write(AddressSpace *as, hwaddr addr,
+bool address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
- address_space_rw(as, addr, (uint8_t *)buf, len, true);
+ return address_space_rw(as, addr, (uint8_t *)buf, len, true);
}
-/**
- * address_space_read: read from an address space.
- *
- * @as: #AddressSpace to be accessed
- * @addr: address within that address space
- * @buf: buffer with the data transferred
- */
-void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
+bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
{
- address_space_rw(as, addr, buf, len, false);
+ return address_space_rw(as, addr, buf, len, false);
}
void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
- return address_space_rw(&address_space_memory, addr, buf, len, is_write);
+ address_space_rw(&address_space_memory, addr, buf, len, is_write);
}
/* used for ROM loading : can write in RAM and ROM */
}
}
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
+{
+ MemoryRegionSection *section;
+ hwaddr l, xlat;
+
+ while (len > 0) {
+ l = len;
+ section = address_space_translate(as, addr, &xlat, &l, is_write);
+ if (!memory_access_is_direct(section->mr, is_write)) {
+ l = memory_access_size(l, addr);
+ if (!memory_region_access_valid(section->mr, xlat, l, is_write)) {
+ return false;
+ }
+ }
+
+ len -= l;
+ addr += l;
+ }
+ return true;
+}
+
/* Map a physical memory region into a host virtual address.
* May map a subset of the requested range, given by and returned in *plen.
* May return NULL if resources needed to perform the mapping are exhausted.
enum device_endian endian)
{
uint8_t *ptr;
- uint32_t val;
+ uint64_t val;
MemoryRegionSection *section;
hwaddr l = 4;
hwaddr addr1;
false);
if (l < 4 || !memory_access_is_direct(section->mr, false)) {
/* I/O case */
- val = io_mem_read(section->mr, addr1, 4);
+ io_mem_read(section->mr, addr1, &val, 4);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
false);
if (l < 8 || !memory_access_is_direct(section->mr, false)) {
/* I/O case */
-
- /* XXX This is broken when device endian != cpu endian.
- Fix and add "endian" variable check */
-#ifdef TARGET_WORDS_BIGENDIAN
- val = io_mem_read(section->mr, addr1, 4) << 32;
- val |= io_mem_read(section->mr, addr1 + 4, 4);
+ io_mem_read(section->mr, addr1, &val, 8);
+#if defined(TARGET_WORDS_BIGENDIAN)
+ if (endian == DEVICE_LITTLE_ENDIAN) {
+ val = bswap64(val);
+ }
#else
- val = io_mem_read(section->mr, addr1, 4);
- val |= io_mem_read(section->mr, addr1 + 4, 4) << 32;
+ if (endian == DEVICE_BIG_ENDIAN) {
+ val = bswap64(val);
+ }
#endif
} else {
/* RAM case */
false);
if (l < 2 || !memory_access_is_direct(section->mr, false)) {
/* I/O case */
- val = io_mem_read(section->mr, addr1, 2);
+ io_mem_read(section->mr, addr1, &val, 2);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
projects / qemu.git / blobdiff