PPC: Bump MPIC up to 32 supported CPUs

[qemu.git] / hw / omap_i2c.c

diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
index 9915676b1ff6739e91cae92b1b8a7d12764b076e..11577b1eecaecf12fe71253f705c579d8a61a247 100644 (file)
--- a/hw/omap_i2c.c
+++ b/hw/omap_i2c.c
@@ -13,20 +13,16 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "hw.h"
 #include "i2c.h"
 #include "omap.h"
 
 struct omap_i2c_s {
-    target_phys_addr_t base;
     qemu_irq irq;
     qemu_irq drq[2];
-    i2c_slave slave;
     i2c_bus *bus;
 
     uint8_t revision;
@@ -57,65 +53,6 @@ static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
         qemu_set_irq(s->drq[1], (s->stat >> 4) & 1);           /* XRDY */
 }
 
-/* These are only stubs now.  */
-static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event)
-{
-    struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
-
-    if ((~s->control >> 15) & 1)                               /* I2C_EN */
-        return;
-
-    switch (event) {
-    case I2C_START_SEND:
-    case I2C_START_RECV:
-        s->stat |= 1 << 9;                                     /* AAS */
-        break;
-    case I2C_FINISH:
-        s->stat |= 1 << 2;                                     /* ARDY */
-        break;
-    case I2C_NACK:
-        s->stat |= 1 << 1;                                     /* NACK */
-        break;
-    }
-
-    omap_i2c_interrupts_update(s);
-}
-
-static int omap_i2c_rx(i2c_slave *i2c)
-{
-    struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
-    uint8_t ret = 0;
-
-    if ((~s->control >> 15) & 1)                               /* I2C_EN */
-        return -1;
-
-    if (s->txlen)
-        ret = s->fifo >> ((-- s->txlen) << 3) & 0xff;
-    else
-        s->stat |= 1 << 10;                                    /* XUDF */
-    s->stat |= 1 << 4;                                         /* XRDY */
-
-    omap_i2c_interrupts_update(s);
-    return ret;
-}
-
-static int omap_i2c_tx(i2c_slave *i2c, uint8_t data)
-{
-    struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
-
-    if ((~s->control >> 15) & 1)                               /* I2C_EN */
-        return 1;
-
-    if (s->rxlen < 4)
-        s->fifo |= data << ((s->rxlen ++) << 3);
-    else
-        s->stat |= 1 << 11;                                    /* ROVR */
-    s->stat |= 1 << 3;                                         /* RRDY */
-
-    omap_i2c_interrupts_update(s);
-    return 1;
-}
-
 static void omap_i2c_fifo_run(struct omap_i2c_s *s)
 {
     int ack = 1;
@@ -253,8 +190,9 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
             if (s->rxlen > 2)
                 s->fifo >>= 16;
             s->rxlen -= 2;
-        } else
-            /* XXX: remote access (qualifier) error - what's that?  */;
+        } else {
+            /* XXX: remote access (qualifier) error - what's that?  */
+        }
         if (!s->rxlen) {
             s->stat &= ~(1 << 3);                              /* RRDY */
             if (((s->control >> 10) & 1) &&                    /* MST */
@@ -395,6 +333,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
                             (~value >> 9) & 1);                        /* TRX */
             s->stat |= nack << 1;                              /* NACK */
             s->control &= ~(1 << 0);                           /* STT */
+            s->fifo = 0;
             if (nack)
                 s->control &= ~(1 << 1);                       /* STP */
             else {
@@ -407,7 +346,6 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
 
     case 0x28: /* I2C_OA */
         s->addr[0] = value & 0x3ff;
-        i2c_set_slave_address(&s->slave, value & 0x7f);
         break;
 
     case 0x2c: /* I2C_SA */
@@ -471,13 +409,13 @@ static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *omap_i2c_readfn[] = {
+static CPUReadMemoryFunc * const omap_i2c_readfn[] = {
     omap_badwidth_read16,
     omap_i2c_read,
     omap_badwidth_read16,
 };
 
-static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
+static CPUWriteMemoryFunc * const omap_i2c_writefn[] = {
     omap_i2c_writeb,   /* Only the last fifo write can be 8 bit.  */
     omap_i2c_write,
     omap_badwidth_write16,
@@ -488,23 +426,19 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
 {
     int iomemtype;
     struct omap_i2c_s *s = (struct omap_i2c_s *)
-            qemu_mallocz(sizeof(struct omap_i2c_s));
+            g_malloc0(sizeof(struct omap_i2c_s));
 
     /* TODO: set a value greater or equal to real hardware */
     s->revision = 0x11;
-    s->base = base;
     s->irq = irq;
     s->drq[0] = dma[0];
     s->drq[1] = dma[1];
-    s->slave.event = omap_i2c_event;
-    s->slave.recv = omap_i2c_rx;
-    s->slave.send = omap_i2c_tx;
-    s->bus = i2c_init_bus();
+    s->bus = i2c_init_bus(NULL, "i2c");
     omap_i2c_reset(s);
 
-    iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
-                    omap_i2c_writefn, s);
-    cpu_register_physical_memory(s->base, 0x800, iomemtype);
+    iomemtype = cpu_register_io_memory(omap_i2c_readfn,
+                    omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
+    cpu_register_physical_memory(base, 0x800, iomemtype);
 
     return s;
 }
@@ -514,21 +448,18 @@ struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
 {
     int iomemtype;
     struct omap_i2c_s *s = (struct omap_i2c_s *)
-            qemu_mallocz(sizeof(struct omap_i2c_s));
+            g_malloc0(sizeof(struct omap_i2c_s));
 
     s->revision = 0x34;
     s->irq = irq;
     s->drq[0] = dma[0];
     s->drq[1] = dma[1];
-    s->slave.event = omap_i2c_event;
-    s->slave.recv = omap_i2c_rx;
-    s->slave.send = omap_i2c_tx;
-    s->bus = i2c_init_bus();
+    s->bus = i2c_init_bus(NULL, "i2c");
     omap_i2c_reset(s);
 
-    iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
+    iomemtype = l4_register_io_memory(omap_i2c_readfn,
                     omap_i2c_writefn, s);
-    s->base = omap_l4_attach(ta, 0, iomemtype);
+    omap_l4_attach(ta, 0, iomemtype);
 
     return s;
 }