qom: Unify type registration

[qemu.git] / hw / cs4231.c

diff --git a/hw/cs4231.c b/hw/cs4231.c
index a5ba221bd8e5f6fb8e80ae05c708cd8873e5b42d..cfec1d9cd158402b35cf116f6b43236ed3e703f4 100644 (file)
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -21,11 +21,9 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include "hw.h"
-#include "sun4m.h"
 
-/* debug CS4231 */
-//#define DEBUG_CS
+#include "sysbus.h"
+#include "trace.h"
 
 /*
  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
@@ -36,25 +34,20 @@
 #define CS_MAXDREG (CS_DREGS - 1)
 
 typedef struct CSState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+    qemu_irq irq;
     uint32_t regs[CS_REGS];
     uint8_t dregs[CS_DREGS];
-    void *intctl;
 } CSState;
 
 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
 #define CS_VER 0xa0
 #define CS_CDC_VER 0x8a
 
-#ifdef DEBUG_CS
-#define DPRINTF(fmt, ...)                                       \
-    do { printf("CS: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...)
-#endif
-
-static void cs_reset(void *opaque)
+static void cs_reset(DeviceState *d)
 {
-    CSState *s = opaque;
+    CSState *s = container_of(d, CSState, busdev.qdev);
 
     memset(s->regs, 0, CS_REGS * 4);
     memset(s->dregs, 0, CS_DREGS);
@@ -62,7 +55,8 @@ static void cs_reset(void *opaque)
     s->dregs[25] = CS_VER;
 }
 
-static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
+                            unsigned size)
 {
     CSState *s = opaque;
     uint32_t saddr, ret;
@@ -78,27 +72,27 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
             ret = s->dregs[CS_RAP(s)];
             break;
         }
-        DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
+        trace_cs4231_mem_readl_dreg(CS_RAP(s), ret);
         break;
     default:
         ret = s->regs[saddr];
-        DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
+        trace_cs4231_mem_readl_reg(saddr, ret);
         break;
     }
     return ret;
 }
 
-static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void cs_mem_write(void *opaque, target_phys_addr_t addr,
+                         uint64_t val, unsigned size)
 {
     CSState *s = opaque;
     uint32_t saddr;
 
     saddr = addr >> 2;
-    DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
+    trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val);
     switch (saddr) {
     case 1:
-        DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
-                s->dregs[CS_RAP(s)], val);
+        trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val);
         switch(CS_RAP(s)) {
         case 11:
         case 25: // Read only
@@ -116,8 +110,9 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
     case 2: // Read only
         break;
     case 4:
-        if (val & 1)
-            cs_reset(s);
+        if (val & 1) {
+            cs_reset(&s->busdev.qdev);
+        }
         val &= 0x7f;
         s->regs[saddr] = val;
         break;
@@ -127,54 +122,60 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
     }
 }
 
-static CPUReadMemoryFunc *cs_mem_read[3] = {
-    cs_mem_readl,
-    cs_mem_readl,
-    cs_mem_readl,
+static const MemoryRegionOps cs_mem_ops = {
+    .read = cs_mem_read,
+    .write = cs_mem_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static CPUWriteMemoryFunc *cs_mem_write[3] = {
-    cs_mem_writel,
-    cs_mem_writel,
-    cs_mem_writel,
+static const VMStateDescription vmstate_cs4231 = {
+    .name ="cs4231",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField []) {
+        VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS),
+        VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS),
+        VMSTATE_END_OF_LIST()
+    }
 };
 
-static void cs_save(QEMUFile *f, void *opaque)
+static int cs4231_init1(SysBusDevice *dev)
 {
-    CSState *s = opaque;
-    unsigned int i;
+    CSState *s = FROM_SYSBUS(CSState, dev);
 
-    for (i = 0; i < CS_REGS; i++)
-        qemu_put_be32s(f, &s->regs[i]);
+    memory_region_init_io(&s->iomem, &cs_mem_ops, s, "cs4321", CS_SIZE);
+    sysbus_init_mmio(dev, &s->iomem);
+    sysbus_init_irq(dev, &s->irq);
 
-    qemu_put_buffer(f, s->dregs, CS_DREGS);
+    return 0;
 }
 
-static int cs_load(QEMUFile *f, void *opaque, int version_id)
-{
-    CSState *s = opaque;
-    unsigned int i;
-
-    if (version_id > 1)
-        return -EINVAL;
+static Property cs4231_properties[] = {
+    {.name = NULL},
+};
 
-    for (i = 0; i < CS_REGS; i++)
-        qemu_get_be32s(f, &s->regs[i]);
+static void cs4231_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 
-    qemu_get_buffer(f, s->dregs, CS_DREGS);
-    return 0;
+    k->init = cs4231_init1;
+    dc->reset = cs_reset;
+    dc->vmsd = &vmstate_cs4231;
+    dc->props = cs4231_properties;
 }
 
-void cs_init(target_phys_addr_t base, int irq, void *intctl)
-{
-    int cs_io_memory;
-    CSState *s;
-
-    s = qemu_mallocz(sizeof(CSState));
+static TypeInfo cs4231_info = {
+    .name          = "SUNW,CS4231",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(CSState),
+    .class_init    = cs4231_class_init,
+};
 
-    cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
-    cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
-    register_savevm("cs4231", base, 1, cs_save, cs_load, s);
-    qemu_register_reset(cs_reset, 0, s);
-    cs_reset(s);
+static void cs4231_register_types(void)
+{
+    type_register_static(&cs4231_info);
 }
+
+type_init(cs4231_register_types)