]> Git Repo - qemu.git/blobdiff - hw/char/xilinx_uartlite.c
char: use qemu_chr_fe* functions with CharBackend argument
[qemu.git] / hw / char / xilinx_uartlite.c
index 3766dc2c5b5c081d7cf7ce8e5034275466a005db..d6df64335d4103c95ac0fe321baaa00772d0832c 100644 (file)
@@ -55,7 +55,7 @@ typedef struct XilinxUARTLite {
     SysBusDevice parent_obj;
 
     MemoryRegion mmio;
-    CharDriverState *chr;
+    CharBackend chr;
     qemu_irq irq;
 
     uint8_t rx_fifo[8];
@@ -107,7 +107,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
                 s->rx_fifo_len--;
             uart_update_status(s);
             uart_update_irq(s);
-            qemu_chr_accept_input(s->chr);
+            qemu_chr_fe_accept_input(&s->chr);
             break;
 
         default:
@@ -143,11 +143,11 @@ uart_write(void *opaque, hwaddr addr,
             break;
 
         case R_TX:
-            if (s->chr)
+            if (s->chr.chr) {
                 /* XXX this blocks entire thread. Rewrite to use
                  * qemu_chr_fe_write and background I/O callbacks */
-                qemu_chr_fe_write_all(s->chr, &ch, 1);
-
+                qemu_chr_fe_write_all(&s->chr, &ch, 1);
+            }
             s->regs[addr] = value;
 
             /* hax.  */
@@ -213,8 +213,10 @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
 {
     XilinxUARTLite *s = XILINX_UARTLITE(dev);
 
-    if (s->chr)
-        qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
+    if (s->chr.chr) {
+        qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
+                                 uart_event, s, NULL);
+    }
 }
 
 static void xilinx_uartlite_init(Object *obj)
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