#if defined (TARGET_PPC64)
/* PowerPC 64 definitions */
-typedef uint64_t ppc_gpr_t;
-#define TARGET_GPR_BITS 64
#define TARGET_LONG_BITS 64
-#define REGX "%016" PRIx64
#define TARGET_PAGE_BITS 12
#else /* defined (TARGET_PPC64) */
/* PowerPC 32 definitions */
-#if (HOST_LONG_BITS >= 64)
-/* When using 64 bits temporary registers,
- * we can use 64 bits GPR with no extra cost
- * It's even an optimization as this will prevent
- * the compiler to do unuseful masking in the micro-ops.
- */
-typedef uint64_t ppc_gpr_t;
-#define TARGET_GPR_BITS 64
-#define REGX "%08" PRIx64
-#else /* (HOST_LONG_BITS >= 64) */
-typedef uint32_t ppc_gpr_t;
-#define TARGET_GPR_BITS 32
-#define REGX "%08" PRIx32
-#endif /* (HOST_LONG_BITS >= 64) */
-
#define TARGET_LONG_BITS 32
#if defined(TARGET_PPCEMB)
#include "cpu-defs.h"
+#define REGX "%016" PRIx64
#define ADDRX TARGET_FMT_lx
#define PADDRX TARGET_FMT_plx
/* MMU model */
typedef enum powerpc_mmu_t powerpc_mmu_t;
enum powerpc_mmu_t {
- POWERPC_MMU_UNKNOWN = 0,
+ POWERPC_MMU_UNKNOWN = 0x00000000,
/* Standard 32 bits PowerPC MMU */
- POWERPC_MMU_32B,
+ POWERPC_MMU_32B = 0x00000001,
/* PowerPC 6xx MMU with software TLB */
- POWERPC_MMU_SOFT_6xx,
+ POWERPC_MMU_SOFT_6xx = 0x00000002,
/* PowerPC 74xx MMU with software TLB */
- POWERPC_MMU_SOFT_74xx,
+ POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
- POWERPC_MMU_SOFT_4xx,
+ POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC 4xx MMU with software TLB and zones protections */
- POWERPC_MMU_SOFT_4xx_Z,
+ POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
/* PowerPC MMU in real mode only */
- POWERPC_MMU_REAL,
+ POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
- POWERPC_MMU_MPC8xx,
+ POWERPC_MMU_MPC8xx = 0x00000007,
/* BookE MMU model */
- POWERPC_MMU_BOOKE,
+ POWERPC_MMU_BOOKE = 0x00000008,
/* BookE FSL MMU model */
- POWERPC_MMU_BOOKE_FSL,
+ POWERPC_MMU_BOOKE_FSL = 0x00000009,
/* PowerPC 601 MMU model (specific BATs format) */
- POWERPC_MMU_601,
+ POWERPC_MMU_601 = 0x0000000A,
#if defined(TARGET_PPC64)
+#define POWERPC_MMU_64 0x00010000
/* 64 bits PowerPC MMU */
- POWERPC_MMU_64B,
+ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
+ /* 620 variant (no segment exceptions) */
+ POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
#endif /* defined(TARGET_PPC64) */
};
void (*hea_read)(void *opaque, int spr_num);
void (*hea_write)(void *opaque, int spr_num);
#endif
- const unsigned char *name;
+ const char *name;
};
/* Altivec registers (128 bits) */
/*****************************************************************************/
/* Machine state register bits definition */
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
+#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
#define MSR_SHV 60 /* hypervisor state hflags */
#define MSR_CM 31 /* Computation mode for BookE hflags */
#define msr_thv ((env->msr >> MSR_THV) & 1)
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
#define msr_vr ((env->msr >> MSR_VR) & 1)
-#define msr_spe ((env->msr >> MSR_SE) & 1)
+#define msr_spe ((env->msr >> MSR_SPE) & 1)
#define msr_ap ((env->msr >> MSR_AP) & 1)
#define msr_sa ((env->msr >> MSR_SA) & 1)
#define msr_key ((env->msr >> MSR_KEY) & 1)
#if defined(PPC_EMULATE_32BITS_HYPV)
#define MSR_HVB (1ULL << MSR_THV)
#define msr_hv msr_thv
-#define
#else
#define MSR_HVB (0ULL)
#define msr_hv (0)
#endif
enum {
- POWERPC_FLAG_NONE = 0x00000000,
+ POWERPC_FLAG_NONE = 0x00000000,
/* Flag for MSR bit 25 signification (VRE/SPE) */
- POWERPC_FLAG_SPE = 0x00000001,
- POWERPC_FLAG_VRE = 0x00000002,
+ POWERPC_FLAG_SPE = 0x00000001,
+ POWERPC_FLAG_VRE = 0x00000002,
/* Flag for MSR bit 17 signification (TGPR/CE) */
- POWERPC_FLAG_TGPR = 0x00000004,
- POWERPC_FLAG_CE = 0x00000008,
+ POWERPC_FLAG_TGPR = 0x00000004,
+ POWERPC_FLAG_CE = 0x00000008,
/* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
- POWERPC_FLAG_SE = 0x00000010,
- POWERPC_FLAG_DWE = 0x00000020,
- POWERPC_FLAG_UBLE = 0x00000040,
+ POWERPC_FLAG_SE = 0x00000010,
+ POWERPC_FLAG_DWE = 0x00000020,
+ POWERPC_FLAG_UBLE = 0x00000040,
/* Flag for MSR bit 9 signification (BE/DE) */
- POWERPC_FLAG_BE = 0x00000080,
- POWERPC_FLAG_DE = 0x00000100,
+ POWERPC_FLAG_BE = 0x00000080,
+ POWERPC_FLAG_DE = 0x00000100,
/* Flag for MSR bit 2 signification (PX/PMM) */
- POWERPC_FLAG_PX = 0x00000200,
- POWERPC_FLAG_PMM = 0x00000400,
+ POWERPC_FLAG_PX = 0x00000200,
+ POWERPC_FLAG_PMM = 0x00000400,
+ /* Flag for special features */
+ /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
+ POWERPC_FLAG_RTC_CLK = 0x00010000,
+ POWERPC_FLAG_BUS_CLK = 0x00020000,
};
/*****************************************************************************/
/* First are the most commonly used resources
* during translated code execution
*/
-#if (HOST_LONG_BITS == 32)
+#if TARGET_LONG_BITS > HOST_LONG_BITS
+ target_ulong t0, t1, t2;
+#endif
+#if !defined(TARGET_PPC64)
/* temporary fixed-point registers
- * used to emulate 64 bits registers on 32 bits hosts
+ * used to emulate 64 bits registers on 32 bits targets
*/
- uint64_t t0, t1, t2;
+ uint64_t t0_64, t1_64, t2_64;
#endif
ppc_avr_t avr0, avr1, avr2;
/* general purpose registers */
- ppc_gpr_t gpr[32];
+ target_ulong gpr[32];
#if !defined(TARGET_PPC64)
/* Storage for GPR MSB, used by the SPE extension */
- ppc_gpr_t gprh[32];
+ target_ulong gprh[32];
#endif
/* LR */
target_ulong lr;
/* CTR */
target_ulong ctr;
/* condition register */
- uint8_t crf[8];
+ uint32_t crf[8];
/* XER */
- /* XXX: We use only 5 fields, but we want to keep the structure aligned */
- uint8_t xer[8];
+ target_ulong xer;
/* Reservation address */
target_ulong reserve;
/* machine state register */
target_ulong msr;
/* temporary general purpose registers */
- ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
+ target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
/* Floating point execution context */
/* temporary float registers */
CPU_COMMON
- int halted; /* TRUE if the CPU is in suspend state */
-
int access_type; /* when a memory exception occurs, the access
type is stored here */
ppc_avr_t avr[32];
uint32_t vscr;
/* SPE registers */
- ppc_gpr_t spe_acc;
+ target_ulong spe_acc;
float_status spe_status;
uint32_t spe_fscr;
int bfd_mach;
uint32_t flags;
- int exception_index;
int error_code;
- int interrupt_request;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
/* This is the IRQ controller, which is implementation dependant
opc_handler_t *opcodes[0x40];
/* Those resources are used only in Qemu core */
- jmp_buf jmp_env;
- int user_mode_only; /* user mode only simulation */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
int mmu_idx; /* precomputed MMU index to speed up mem accesses */
/*****************************************************************************/
CPUPPCState *cpu_ppc_init (const char *cpu_model);
+void ppc_translate_init(void);
int cpu_ppc_exec (CPUPPCState *s);
void cpu_ppc_close (CPUPPCState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
-const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
+const ppc_def_t *cpu_ppc_find_by_name (const char *name);
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
/* Time-base and decrementer management */
#endif
#endif
+static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
+{
+ uint64_t gprv;
+
+ gprv = env->gpr[gprn];
+#if !defined(TARGET_PPC64)
+ if (env->flags & POWERPC_FLAG_SPE) {
+ /* If the CPU implements the SPE extension, we have to get the
+ * high bits of the GPR from the gprh storage area
+ */
+ gprv &= 0xFFFFFFFFULL;
+ gprv |= (uint64_t)env->gprh[gprn] << 32;
+ }
+#endif
+
+ return gprv;
+}
+
/* Device control registers */
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list
+#define CPU_SAVE_VERSION 3
+
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
return env->mmu_idx;
}
+#if defined(CONFIG_USER_ONLY)
+static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+{
+ int i;
+ if (newsp)
+ env->gpr[1] = newsp;
+ for (i = 7; i < 32; i++)
+ env->gpr[i] = 0;
+}
+#endif
+
+#define CPU_PC_FROM_TB(env, tb) env->nip = tb->pc
+
#include "cpu-all.h"
/*****************************************************************************/
-/* Registers definitions */
-#define XER_SO 31
-#define XER_OV 30
-#define XER_CA 29
-#define XER_CMP 8
-#define XER_BC 0
-#define xer_so env->xer[4]
-#define xer_ov env->xer[6]
-#define xer_ca env->xer[2]
-#define xer_cmp env->xer[1]
-#define xer_bc env->xer[0]
+/* CRF definitions */
+#define CRF_LT 3
+#define CRF_GT 2
+#define CRF_EQ 1
+#define CRF_SO 0
+
+/* XER definitions */
+#define XER_SO 31
+#define XER_OV 30
+#define XER_CA 29
+#define XER_CMP 8
+#define XER_BC 0
+#define xer_so ((env->xer >> XER_SO) & 1)
+#define xer_ov ((env->xer >> XER_OV) & 1)
+#define xer_ca ((env->xer >> XER_CA) & 1)
+#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
+#define xer_bc ((env->xer >> XER_BC) & 0x7F)
/* SPR definitions */
#define SPR_MQ (0x000)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
#define SPR_PERF3 (0x303)
+#define SPR_620_PMC1R (0x303)
#define SPR_RCPU_MI_RBA3 (0x303)
#define SPR_MPC_MI_EPN (0x303)
#define SPR_PERF4 (0x304)
+#define SPR_620_PMC2R (0x304)
#define SPR_PERF5 (0x305)
#define SPR_MPC_MI_TWC (0x305)
#define SPR_PERF6 (0x306)
#define SPR_RCPU_L2U_RBA2 (0x30A)
#define SPR_MPC_MD_AP (0x30A)
#define SPR_PERFB (0x30B)
+#define SPR_620_MMCR0R (0x30B)
#define SPR_RCPU_L2U_RBA3 (0x30B)
#define SPR_MPC_MD_EPN (0x30B)
#define SPR_PERFC (0x30C)
#define SPR_UPERF1 (0x311)
#define SPR_UPERF2 (0x312)
#define SPR_UPERF3 (0x313)
+#define SPR_620_PMC1W (0x313)
#define SPR_UPERF4 (0x314)
+#define SPR_620_PMC2W (0x314)
#define SPR_UPERF5 (0x315)
#define SPR_UPERF6 (0x316)
#define SPR_UPERF7 (0x317)
#define SPR_UPERF9 (0x319)
#define SPR_UPERFA (0x31A)
#define SPR_UPERFB (0x31B)
+#define SPR_620_MMCR0W (0x31B)
#define SPR_UPERFC (0x31C)
#define SPR_UPERFD (0x31D)
#define SPR_UPERFE (0x31E)
#define SPR_440_CCR1 (0x378)
#define SPR_DCRIPR (0x37B)
#define SPR_PPR (0x380)
+#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
+#define SPR_750_GQR1 (0x391)
#define SPR_440_DNV1 (0x391)
+#define SPR_750_GQR2 (0x392)
#define SPR_440_DNV2 (0x392)
+#define SPR_750_GQR3 (0x393)
#define SPR_440_DNV3 (0x393)
+#define SPR_750_GQR4 (0x394)
#define SPR_440_DTV0 (0x394)
+#define SPR_750_GQR5 (0x395)
#define SPR_440_DTV1 (0x395)
+#define SPR_750_GQR6 (0x396)
#define SPR_440_DTV2 (0x396)
+#define SPR_750_GQR7 (0x397)
#define SPR_440_DTV3 (0x397)
+#define SPR_750_THRM4 (0x398)
+#define SPR_750CL_HID2 (0x398)
#define SPR_440_DVLIM (0x398)
+#define SPR_750_WPAR (0x399)
#define SPR_440_IVLIM (0x399)
+#define SPR_750_DMAU (0x39A)
+#define SPR_750_DMAL (0x39B)
#define SPR_440_RSTCFG (0x39B)
#define SPR_BOOKE_DCDBTRL (0x39C)
#define SPR_BOOKE_DCDBTRH (0x39D)
#define SPR_40x_EVPR (0x3D6)
#define SPR_L3PM (0x3D7)
#define SPR_403_CDBCR (0x3D7)
-#define SPR_L3OHCR (0x3D8)
+#define SPR_L3ITCR0 (0x3D8)
#define SPR_TCR (0x3D8)
#define SPR_40x_TSR (0x3D8)
#define SPR_IBR (0x3DA)
#define SPR_40x_SRR2 (0x3DE)
#define SPR_SER (0x3DF)
#define SPR_40x_SRR3 (0x3DF)
-#define SPR_L3ITCR0 (0x3E8)
+#define SPR_L3OHCR (0x3E8)
#define SPR_L3ITCR1 (0x3E9)
#define SPR_L3ITCR2 (0x3EA)
#define SPR_L3ITCR3 (0x3EB)
#define SPR_Exxx_L1CSR0 (0x3F2)
#define SPR_ICTRL (0x3F3)
#define SPR_HID2 (0x3F3)
+#define SPR_750CL_HID4 (0x3F3)
#define SPR_Exxx_L1CSR1 (0x3F3)
#define SPR_440_DBDR (0x3F3)
#define SPR_LDSTDB (0x3F4)
+#define SPR_750_TDCL (0x3F4)
#define SPR_40x_IAC1 (0x3F4)
#define SPR_MMUCSR0 (0x3F4)
#define SPR_DABR (0x3F5)
#define SPR_MSSCR0 (0x3F6)
#define SPR_970_HID5 (0x3F6)
#define SPR_MSSSR0 (0x3F7)
+#define SPR_MSSCR1 (0x3F7)
#define SPR_DABRX (0x3F7)
#define SPR_40x_DAC2 (0x3F7)
#define SPR_MMUCFG (0x3F7)
#define SPR_LDSTCR (0x3F8)
#define SPR_L2PMCR (0x3F8)
-#define SPR_750_HID2 (0x3F8)
-#define SPR_620_HID8 (0x3F8)
+#define SPR_750FX_HID2 (0x3F8)
+#define SPR_620_BUSCSR (0x3F8)
#define SPR_Exxx_L1FINV0 (0x3F8)
#define SPR_L2CR (0x3F9)
-#define SPR_620_HID9 (0x3F9)
+#define SPR_620_L2CR (0x3F9)
#define SPR_L3CR (0x3FA)
+#define SPR_750_TDCH (0x3FA)
#define SPR_IABR2 (0x3FA)
#define SPR_40x_DCCR (0x3FA)
+#define SPR_620_L2SR (0x3FA)
#define SPR_ICTC (0x3FB)
#define SPR_40x_ICCR (0x3FB)
#define SPR_THRM1 (0x3FC)
projects / qemu.git / blobdiff