target-arm: Move cache ID register setup to cpu specific init fns

[qemu.git] / target-arm / cpu.c

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 333f7fc1616e2d678c3adf16ae313d31a297d437..8259a0df43e962a8020fc9c9da4648cdde4dfd3d 100644 (file)
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -270,6 +270,10 @@ static void cortex_a8_initfn(Object *obj)
     cpu->id_isar2 = 0x21232031;
     cpu->id_isar3 = 0x11112131;
     cpu->id_isar4 = 0x00111142;
+    cpu->clidr = (1 << 27) | (2 << 24) | 3;
+    cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
+    cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
+    cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 }
 
 static void cortex_a9_initfn(Object *obj)
@@ -304,6 +308,9 @@ static void cortex_a9_initfn(Object *obj)
     cpu->id_isar2 = 0x21232041;
     cpu->id_isar3 = 0x11112131;
     cpu->id_isar4 = 0x00111142;
+    cpu->clidr = (1 << 27) | (1 << 24) | 3;
+    cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
+    cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 }
 
 static void cortex_a15_initfn(Object *obj)
@@ -336,6 +343,10 @@ static void cortex_a15_initfn(Object *obj)
     cpu->id_isar2 = 0x21232041;
     cpu->id_isar3 = 0x11112131;
     cpu->id_isar4 = 0x10011142;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 }
 
 static void ti925t_initfn(Object *obj)