lm32: add Milkymist TMU2 support

[qemu.git] / hw / sbi.c

diff --git a/hw/sbi.c b/hw/sbi.c
index 101fba5ae6edf631c3e5e90b29cc5b4aac0d9fec..53f66f2c5ea4a32167c91c3e8e5d1dcf565570e7 100644 (file)
--- a/hw/sbi.c
+++ b/hw/sbi.c
@@ -22,9 +22,6 @@
  * THE SOFTWARE.
  */
 
-#include "hw.h"
-#include "sun4m.h"
-#include "console.h"
 #include "sysbus.h"
 
 //#define DEBUG_IRQ
@@ -84,46 +81,32 @@ static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
     }
 }
 
-static CPUReadMemoryFunc *sbi_mem_read[3] = {
+static CPUReadMemoryFunc * const sbi_mem_read[3] = {
     NULL,
     NULL,
     sbi_mem_readl,
 };
 
-static CPUWriteMemoryFunc *sbi_mem_write[3] = {
+static CPUWriteMemoryFunc * const sbi_mem_write[3] = {
     NULL,
     NULL,
     sbi_mem_writel,
 };
 
-static void sbi_save(QEMUFile *f, void *opaque)
-{
-    SBIState *s = opaque;
-    unsigned int i;
-
-    for (i = 0; i < MAX_CPUS; i++) {
-        qemu_put_be32s(f, &s->intreg_pending[i]);
-    }
-}
-
-static int sbi_load(QEMUFile *f, void *opaque, int version_id)
-{
-    SBIState *s = opaque;
-    unsigned int i;
-
-    if (version_id != 1)
-        return -EINVAL;
-
-    for (i = 0; i < MAX_CPUS; i++) {
-        qemu_get_be32s(f, &s->intreg_pending[i]);
+static const VMStateDescription vmstate_sbi = {
+    .name ="sbi",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField []) {
+        VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),
+        VMSTATE_END_OF_LIST()
     }
+};
 
-    return 0;
-}
-
-static void sbi_reset(void *opaque)
+static void sbi_reset(DeviceState *d)
 {
-    SBIState *s = opaque;
+    SBIState *s = container_of(d, SBIState, busdev.qdev);
     unsigned int i;
 
     for (i = 0; i < MAX_CPUS; i++) {
@@ -131,27 +114,7 @@ static void sbi_reset(void *opaque)
     }
 }
 
-DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
-{
-    DeviceState *dev;
-    SysBusDevice *s;
-    unsigned int i;
-
-    dev = qdev_create(NULL, "sbi");
-    qdev_init(dev);
-
-    s = sysbus_from_qdev(dev);
-
-    for (i = 0; i < MAX_CPUS; i++) {
-        sysbus_connect_irq(s, i, *parent_irq[i]);
-    }
-
-    sysbus_mmio_map(s, 0, addr);
-
-    return dev;
-}
-
-static void sbi_init1(SysBusDevice *dev)
+static int sbi_init1(SysBusDevice *dev)
 {
     SBIState *s = FROM_SYSBUS(SBIState, dev);
     int sbi_io_memory;
@@ -162,18 +125,19 @@ static void sbi_init1(SysBusDevice *dev)
         sysbus_init_irq(dev, &s->cpu_irqs[i]);
     }
 
-    sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
+    sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s,
+                                           DEVICE_NATIVE_ENDIAN);
     sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory);
 
-    register_savevm("sbi", -1, 1, sbi_save, sbi_load, s);
-    qemu_register_reset(sbi_reset, s);
-    sbi_reset(s);
+    return 0;
 }
 
 static SysBusDeviceInfo sbi_info = {
     .init = sbi_init1,
     .qdev.name  = "sbi",
     .qdev.size  = sizeof(SBIState),
+    .qdev.vmsd  = &vmstate_sbi,
+    .qdev.reset = sbi_reset,
 };
 
 static void sbi_register_devices(void)