* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sun4m.h"
/* debug iommu */
//#define DEBUG_IOMMU
#define DPRINTF(fmt, args...)
#endif
-#define IOMMU_NREGS (3*4096/4)
+#define IOMMU_NREGS (4*4096/4)
#define IOMMU_CTRL (0x0000 >> 2)
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
#define IOMMU_AFSR (0x1000 >> 2)
#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
-#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
-#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
-#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
+#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
+ transaction */
+#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
+ 12.8 us. */
+#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
+ acknowledge */
#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
-#define IOMMU_AFSR_RESV 0x00f00000 /* Reserved, forced to 0x8 by hardware */
+#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
+ hardware */
#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
+#define IOMMU_AFSR_MASK 0xff0fffff
#define IOMMU_AFAR (0x1004 >> 2)
#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
-#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
+#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
+ bypass enabled */
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
#define IOMMU_ARBEN_MASK 0x001f0000
#define IOMMU_MID 0x00000008
+#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
+#define IOMMU_MASK_ID_MASK 0x00ffffff
+
+#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
+#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
+
/* The format of an iopte in the page tables */
-#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
-#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
+#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
+#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
+ Viking/MXCC) */
#define IOPTE_WRITE 0x00000004 /* Writeable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */
uint32_t regs[IOMMU_NREGS];
target_phys_addr_t iostart;
uint32_t version;
+ qemu_irq irq;
} IOMMUState;
-static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
{
IOMMUState *s = opaque;
target_phys_addr_t saddr;
+ uint32_t ret;
saddr = (addr - s->addr) >> 2;
switch (saddr) {
default:
- DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
- return s->regs[saddr];
+ ret = s->regs[saddr];
+ break;
+ case IOMMU_AFAR:
+ case IOMMU_AFSR:
+ ret = s->regs[saddr];
+ qemu_irq_lower(s->irq);
break;
}
- return 0;
+ DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
+ return ret;
}
-static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
{
IOMMUState *s = opaque;
target_phys_addr_t saddr;
DPRINTF("page flush %x\n", val);
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
break;
+ case IOMMU_AFAR:
+ s->regs[saddr] = val;
+ qemu_irq_lower(s->irq);
+ break;
+ case IOMMU_AFSR:
+ s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
+ qemu_irq_lower(s->irq);
+ break;
case IOMMU_SBCFG0:
case IOMMU_SBCFG1:
case IOMMU_SBCFG2:
// addresses, fault cause and address stored to MMU/IOMMU
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
break;
+ case IOMMU_MASK_ID:
+ s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
+ break;
default:
s->regs[saddr] = val;
break;
}
static CPUReadMemoryFunc *iommu_mem_read[3] = {
- iommu_mem_readw,
- iommu_mem_readw,
- iommu_mem_readw,
+ NULL,
+ NULL,
+ iommu_mem_readl,
};
static CPUWriteMemoryFunc *iommu_mem_write[3] = {
- iommu_mem_writew,
- iommu_mem_writew,
- iommu_mem_writew,
+ NULL,
+ NULL,
+ iommu_mem_writel,
};
static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
return ret;
}
-static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
- target_phys_addr_t addr,
+static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
uint32_t pte)
{
uint32_t tmppte;
return pa;
}
-static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write)
+static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
+ int is_write)
{
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
- s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | (8 << 20) |
+ s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
IOMMU_AFSR_FAV;
if (!is_write)
s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
s->regs[IOMMU_AFAR] = addr;
+ qemu_irq_raise(s->irq);
}
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
iommu_bad_addr(opaque, page, is_write);
return;
}
- phys_addr = iommu_translate_pa(opaque, addr, flags);
+ phys_addr = iommu_translate_pa(addr, flags);
if (is_write) {
if (!(flags & IOPTE_WRITE)) {
iommu_bad_addr(opaque, page, is_write);
s->iostart = 0;
s->regs[IOMMU_CTRL] = s->version;
s->regs[IOMMU_ARBEN] = IOMMU_MID;
+ s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
+ s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
+ qemu_irq_lower(s->irq);
}
-void *iommu_init(target_phys_addr_t addr, uint32_t version)
+void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
{
IOMMUState *s;
int iommu_io_memory;
s->addr = addr;
s->version = version;
+ s->irq = irq;
- iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
+ iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
+ iommu_mem_write, s);
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
iommu_reset(s);
return s;
}
-
projects / qemu.git / blobdiff