target/xtensa: add parity/ECC option SRs

[qemu.git] / target / xtensa / translate.c

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index c626583cd952aebaecdd8da6e11172266e463578..63a90fdd17dc9ce0774c956c1b60c54e34341aed 100644 (file)
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -35,6 +35,7 @@
 #include "disas/disas.h"
 #include "tcg-op.h"
 #include "qemu/log.h"
 #include "disas/disas.h"
 #include "tcg-op.h"
 #include "qemu/log.h"

+#include "qemu/qemu-print.h"

 #include "sysemu/sysemu.h"
 #include "exec/cpu_ldst.h"
 #include "exec/semihost.h"
 #include "sysemu/sysemu.h"
 #include "exec/cpu_ldst.h"
 #include "exec/semihost.h"


@@ -53,7 +54,7 @@ struct DisasContext {
     uint32_t pc;
     int cring;
     int ring;
     uint32_t pc;
     int cring;
     int ring;

-    uint32_t lbeg;
+    uint32_t lbeg_off;

     uint32_t lend;
 
     bool sar_5bit;
     uint32_t lend;
 
     bool sar_5bit;


@@ -62,6 +63,8 @@ struct DisasContext {
     TCGv_i32 sar_m32;
 
     unsigned window;
     TCGv_i32 sar_m32;
 
     unsigned window;

+    unsigned callinc;
+    bool cwoe;

 
     bool debug;
     bool icount;
 
     bool debug;
     bool icount;


@@ -69,7 +72,7 @@ struct DisasContext {
 
     unsigned cpenable;
 
 
     unsigned cpenable;
 

-    uint32_t *raw_arg;
+    uint32_t op_flags;

     xtensa_insnbuf insnbuf;
     xtensa_insnbuf slotbuf;
 };
     xtensa_insnbuf insnbuf;
     xtensa_insnbuf slotbuf;
 };


@@ -77,132 +80,52 @@ struct DisasContext {
 static TCGv_i32 cpu_pc;
 static TCGv_i32 cpu_R[16];
 static TCGv_i32 cpu_FR[16];
 static TCGv_i32 cpu_pc;
 static TCGv_i32 cpu_R[16];
 static TCGv_i32 cpu_FR[16];

+static TCGv_i32 cpu_MR[4];
+static TCGv_i32 cpu_BR[16];
+static TCGv_i32 cpu_BR4[4];
+static TCGv_i32 cpu_BR8[2];

 static TCGv_i32 cpu_SR[256];
 static TCGv_i32 cpu_UR[256];
 static TCGv_i32 cpu_SR[256];
 static TCGv_i32 cpu_UR[256];

+static TCGv_i32 cpu_windowbase_next;
+
+static GHashTable *xtensa_regfile_table;

 
 #include "exec/gen-icount.h"
 
 
 #include "exec/gen-icount.h"
 

-typedef struct XtensaReg {
-    const char *name;
-    uint64_t opt_bits;
-    enum {
-        SR_R = 1,
-        SR_W = 2,
-        SR_X = 4,
-        SR_RW = 3,
-        SR_RWX = 7,
-    } access;
-} XtensaReg;
-
-#define XTENSA_REG_ACCESS(regname, opt, acc) { \
-        .name = (regname), \
-        .opt_bits = XTENSA_OPTION_BIT(opt), \
-        .access = (acc), \
-    }
+static char *sr_name[256];
+static char *ur_name[256];
+
+void xtensa_collect_sr_names(const XtensaConfig *config)
+{
+    xtensa_isa isa = config->isa;
+    int n = xtensa_isa_num_sysregs(isa);
+    int i;

 
 

-#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
+    for (i = 0; i < n; ++i) {
+        int sr = xtensa_sysreg_number(isa, i);

 
 

-#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
-        .name = (regname), \
-        .opt_bits = (opt), \
-        .access = (acc), \
-    }
+        if (sr >= 0 && sr < 256) {
+            const char *name = xtensa_sysreg_name(isa, i);
+            char **pname =
+                (xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr;

 
 

-#define XTENSA_REG_BITS(regname, opt) \
-    XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
-
-static const XtensaReg sregnames[256] = {
-    [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
-    [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
-    [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
-    [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
-    [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
-    [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
-    [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
-    [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
-    [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
-    [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
-    [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
-    [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
-    [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
-    [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
-    [WINDOW_START] = XTENSA_REG("WINDOW_START",
-            XTENSA_OPTION_WINDOWED_REGISTER),
-    [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
-    [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL),
-    [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
-    [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
-    [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
-    [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
-    [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL),
-    [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
-    [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
-    [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG),
-    [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
-    [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
-    [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
-    [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
-    [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
-    [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
-    [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
-    [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
-    [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
-    [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
-    [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
-    [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
-            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
-            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
-            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
-            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
-            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
-            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
-    [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
-    [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
-    [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
-    [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
-    [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
-    [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
-    [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
-    [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
-    [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
-    [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
-    [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
-    [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
-    [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
-    [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
-    [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
-            XTENSA_OPTION_TIMER_INTERRUPT),
-    [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
-            XTENSA_OPTION_TIMER_INTERRUPT),
-    [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
-    [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
-    [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
-    [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
-};
+            if (*pname) {
+                if (strstr(*pname, name) == NULL) {
+                    char *new_name =
+                        malloc(strlen(*pname) + strlen(name) + 2);

 
 

-static const XtensaReg uregnames[256] = {
-    [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL),
-    [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
-    [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
-    [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
-};
+                    strcpy(new_name, *pname);
+                    strcat(new_name, "/");
+                    strcat(new_name, name);
+                    free(*pname);
+                    *pname = new_name;
+                }
+            } else {
+                *pname = strdup(name);
+            }
+        }
+    }
+}

 
 void xtensa_translate_init(void)
 {
 
 void xtensa_translate_init(void)
 {


@@ -218,6 +141,15 @@ void xtensa_translate_init(void)
         "f8", "f9", "f10", "f11",
         "f12", "f13", "f14", "f15",
     };
         "f8", "f9", "f10", "f11",
         "f12", "f13", "f14", "f15",
     };

+    static const char * const mregnames[] = {
+        "m0", "m1", "m2", "m3",
+    };
+    static const char * const bregnames[] = {
+        "b0", "b1", "b2", "b3",
+        "b4", "b5", "b6", "b7",
+        "b8", "b9", "b10", "b11",
+        "b12", "b13", "b14", "b15",
+    };

     int i;
 
     cpu_pc = tcg_global_mem_new_i32(cpu_env,
     int i;
 
     cpu_pc = tcg_global_mem_new_i32(cpu_env,


@@ -225,31 +157,85 @@ void xtensa_translate_init(void)
 
     for (i = 0; i < 16; i++) {
         cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
 
     for (i = 0; i < 16; i++) {
         cpu_R[i] = tcg_global_mem_new_i32(cpu_env,

-                offsetof(CPUXtensaState, regs[i]),
-                regnames[i]);
+                                          offsetof(CPUXtensaState, regs[i]),
+                                          regnames[i]);

     }
 
     for (i = 0; i < 16; i++) {
         cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
     }
 
     for (i = 0; i < 16; i++) {
         cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,

-                offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
-                fregnames[i]);
+                                           offsetof(CPUXtensaState,
+                                                    fregs[i].f32[FP_F32_LOW]),
+                                           fregnames[i]);
+    }
+
+    for (i = 0; i < 4; i++) {
+        cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
+                                           offsetof(CPUXtensaState,
+                                                    sregs[MR + i]),
+                                           mregnames[i]);
+    }
+
+    for (i = 0; i < 16; i++) {
+        cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
+                                           offsetof(CPUXtensaState,
+                                                    sregs[BR]),
+                                           bregnames[i]);
+        if (i % 4 == 0) {
+            cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
+                                                    offsetof(CPUXtensaState,
+                                                             sregs[BR]),
+                                                    bregnames[i]);
+        }
+        if (i % 8 == 0) {
+            cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
+                                                    offsetof(CPUXtensaState,
+                                                             sregs[BR]),
+                                                    bregnames[i]);
+        }

     }
 
     for (i = 0; i < 256; ++i) {
     }
 
     for (i = 0; i < 256; ++i) {

-        if (sregnames[i].name) {
+        if (sr_name[i]) {

             cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
             cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,

-                    offsetof(CPUXtensaState, sregs[i]),
-                    sregnames[i].name);
+                                               offsetof(CPUXtensaState,
+                                                        sregs[i]),
+                                               sr_name[i]);

         }
     }
 
     for (i = 0; i < 256; ++i) {
         }
     }
 
     for (i = 0; i < 256; ++i) {

-        if (uregnames[i].name) {
+        if (ur_name[i]) {

             cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
             cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,

-                    offsetof(CPUXtensaState, uregs[i]),
-                    uregnames[i].name);
+                                               offsetof(CPUXtensaState,
+                                                        uregs[i]),
+                                               ur_name[i]);

         }
     }
         }
     }

+
+    cpu_windowbase_next =
+        tcg_global_mem_new_i32(cpu_env,
+                               offsetof(CPUXtensaState, windowbase_next),
+                               "windowbase_next");
+}
+
+void **xtensa_get_regfile_by_name(const char *name)
+{
+    if (xtensa_regfile_table == NULL) {
+        xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal);
+        g_hash_table_insert(xtensa_regfile_table,
+                            (void *)"AR", (void *)cpu_R);
+        g_hash_table_insert(xtensa_regfile_table,
+                            (void *)"MR", (void *)cpu_MR);
+        g_hash_table_insert(xtensa_regfile_table,
+                            (void *)"FR", (void *)cpu_FR);
+        g_hash_table_insert(xtensa_regfile_table,
+                            (void *)"BR", (void *)cpu_BR);
+        g_hash_table_insert(xtensa_regfile_table,
+                            (void *)"BR4", (void *)cpu_BR4);
+        g_hash_table_insert(xtensa_regfile_table,
+                            (void *)"BR8", (void *)cpu_BR8);
+    }
+    return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name);

 }
 
 static inline bool option_enabled(DisasContext *dc, int opt)
 }
 
 static inline bool option_enabled(DisasContext *dc, int opt)


@@ -349,17 +335,20 @@ static bool gen_check_privilege(DisasContext *dc)
     return false;
 }
 
     return false;
 }
 

-static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
+static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask)

 {
 {

-    if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
-            !(dc->cpenable & (1 << cp))) {
-        gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
+    cp_mask &= ~dc->cpenable;
+
+    if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) {
+        gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask));

         dc->base.is_jmp = DISAS_NORETURN;
         return false;
     }
     return true;
 }
 
         dc->base.is_jmp = DISAS_NORETURN;
         return false;
     }
     return true;
 }
 

+static int gen_postprocess(DisasContext *dc, int slot);
+

 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
 {
     tcg_gen_mov_i32(cpu_pc, dest);
 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
 {
     tcg_gen_mov_i32(cpu_pc, dest);


@@ -369,6 +358,9 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
     if (dc->base.singlestep_enabled) {
         gen_exception(dc, EXCP_DEBUG);
     } else {
     if (dc->base.singlestep_enabled) {
         gen_exception(dc, EXCP_DEBUG);
     } else {

+        if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
+            slot = gen_postprocess(dc, slot);
+        }

         if (slot >= 0) {
             tcg_gen_goto_tb(slot);
             tcg_gen_exit_tb(dc->base.tb, slot);
         if (slot >= 0) {
             tcg_gen_goto_tb(slot);
             tcg_gen_exit_tb(dc->base.tb, slot);


@@ -384,15 +376,19 @@ static void gen_jump(DisasContext *dc, TCGv dest)
     gen_jump_slot(dc, dest, -1);
 }
 
     gen_jump_slot(dc, dest, -1);
 }
 

-static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
+static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot)

 {
 {

-    TCGv_i32 tmp = tcg_const_i32(dest);
-#ifndef CONFIG_USER_ONLY

     if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
     if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {

-        slot = -1;
+        return -1;
+    } else {
+        return slot;

     }
     }

-#endif
-    gen_jump_slot(dc, tmp, slot);
+}
+
+static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
+{
+    TCGv_i32 tmp = tcg_const_i32(dest);
+    gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));

     tcg_temp_free(tmp);
 }
 
     tcg_temp_free(tmp);
 }
 


@@ -409,33 +405,18 @@ static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
     gen_jump_slot(dc, dest, slot);
 }
 
     gen_jump_slot(dc, dest, slot);
 }
 

-static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
-{
-    gen_callw_slot(dc, callinc, dest, -1);
-}
-
-static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
-{
-    TCGv_i32 tmp = tcg_const_i32(dest);
-#ifndef CONFIG_USER_ONLY
-    if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
-        slot = -1;
-    }
-#endif
-    gen_callw_slot(dc, callinc, tmp, slot);
-    tcg_temp_free(tmp);
-}
-

 static bool gen_check_loop_end(DisasContext *dc, int slot)
 {
 static bool gen_check_loop_end(DisasContext *dc, int slot)
 {

-    if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
-            !(dc->base.tb->flags & XTENSA_TBFLAG_EXCM) &&
-            dc->base.pc_next == dc->lend) {
+    if (dc->base.pc_next == dc->lend) {

         TCGLabel *label = gen_new_label();
 
         tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
         tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
         TCGLabel *label = gen_new_label();
 
         tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
         tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);

-        gen_jumpi(dc, dc->lbeg, slot);
+        if (dc->lbeg_off) {
+            gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot);
+        } else {
+            gen_jump(dc, cpu_SR[LBEG]);
+        }

         gen_set_label(label);
         gen_jumpi(dc, dc->base.pc_next, -1);
         return true;
         gen_set_label(label);
         gen_jumpi(dc, dc->base.pc_next, -1);
         return true;


@@ -469,491 +450,422 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond,
     tcg_temp_free(tmp);
 }
 
     tcg_temp_free(tmp);
 }
 

-static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
+static bool test_ill_sr(DisasContext *dc, const OpcodeArg arg[],
+                        const uint32_t par[])

 {
 {

-    if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
-        if (sregnames[sr].name) {
-            qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
-        } else {
-            qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
-        }
-        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
-        return false;
-    } else if (!(sregnames[sr].access & access)) {
-        static const char * const access_text[] = {
-            [SR_R] = "rsr",
-            [SR_W] = "wsr",
-            [SR_X] = "xsr",
-        };
-        assert(access < ARRAY_SIZE(access_text) && access_text[access]);
-        qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
-                      access_text[access]);
-        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
-        return false;
-    }
-    return true;
+    return !xtensa_option_enabled(dc->config, par[1]);

 }
 
 }
 

-#ifndef CONFIG_USER_ONLY
-static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
+static bool test_ill_ccompare(DisasContext *dc, const OpcodeArg arg[],
+                              const uint32_t par[])

 {
 {

-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_start();
-    }
-    gen_helper_update_ccount(cpu_env);
-    tcg_gen_mov_i32(d, cpu_SR[sr]);
-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_end();
-        return true;
-    }
-    return false;
-}
+    unsigned n = par[0] - CCOMPARE;

 
 

-static bool gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
-{
-    tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
-    tcg_gen_or_i32(d, d, cpu_SR[sr]);
-    tcg_gen_andi_i32(d, d, 0xfffffffc);
-    return false;
+    return test_ill_sr(dc, arg, par) || n >= dc->config->nccompare;

 }
 }

-#endif

 
 

-static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
+static bool test_ill_dbreak(DisasContext *dc, const OpcodeArg arg[],
+                            const uint32_t par[])

 {
 {

-    static bool (* const rsr_handler[256])(DisasContext *dc,
-            TCGv_i32 d, uint32_t sr) = {
-#ifndef CONFIG_USER_ONLY
-        [CCOUNT] = gen_rsr_ccount,
-        [INTSET] = gen_rsr_ccount,
-        [PTEVADDR] = gen_rsr_ptevaddr,
-#endif
-    };
+    unsigned n = MAX_NDBREAK;

 
 

-    if (rsr_handler[sr]) {
-        return rsr_handler[sr](dc, d, sr);
-    } else {
-        tcg_gen_mov_i32(d, cpu_SR[sr]);
-        return false;
+    if (par[0] >= DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) {
+        n = par[0] - DBREAKA;
+    }
+    if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) {
+        n = par[0] - DBREAKC;

     }
     }

+    return test_ill_sr(dc, arg, par) || n >= dc->config->ndbreak;

 }
 
 }
 

-static bool gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static bool test_ill_ibreak(DisasContext *dc, const OpcodeArg arg[],
+                            const uint32_t par[])

 {
 {

-    gen_helper_wsr_lbeg(cpu_env, s);
-    gen_jumpi_check_loop_end(dc, 0);
-    return false;
-}
+    unsigned n = par[0] - IBREAKA;

 
 

-static bool gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
-{
-    gen_helper_wsr_lend(cpu_env, s);
-    gen_jumpi_check_loop_end(dc, 0);
-    return false;
+    return test_ill_sr(dc, arg, par) || n >= dc->config->nibreak;

 }
 
 }
 

-static bool gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static bool test_ill_hpi(DisasContext *dc, const OpcodeArg arg[],
+                         const uint32_t par[])

 {
 {

-    tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
-    if (dc->sar_m32_5bit) {
-        tcg_gen_discard_i32(dc->sar_m32);
+    unsigned n = MAX_NLEVEL + 1;
+
+    if (par[0] >= EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) {
+        n = par[0] - EXCSAVE1 + 1;

     }
     }

-    dc->sar_5bit = false;
-    dc->sar_m32_5bit = false;
-    return false;
+    if (par[0] >= EPC1 && par[0] < EPC1 + MAX_NLEVEL) {
+        n = par[0] - EPC1 + 1;
+    }
+    if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) {
+        n = par[0] - EPS2 + 2;
+    }
+    return test_ill_sr(dc, arg, par) || n > dc->config->nlevel;

 }
 
 }
 

-static bool gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_load_store_alignment(DisasContext *dc, int shift,
+        TCGv_i32 addr, bool no_hw_alignment)

 {
 {

-    tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
-    return false;
+    if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
+        tcg_gen_andi_i32(addr, addr, ~0 << shift);
+    } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
+            no_hw_alignment) {
+        TCGLabel *label = gen_new_label();
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
+        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
+        gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
+        gen_set_label(label);
+        tcg_temp_free(tmp);
+    }

 }
 
 }
 

-static bool gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+#ifndef CONFIG_USER_ONLY
+static void gen_waiti(DisasContext *dc, uint32_t imm4)

 {
 {

-    tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
-}
+    TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
+    TCGv_i32 intlevel = tcg_const_i32(imm4);

 
 

-static bool gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
-{
-    tcg_gen_ext8s_i32(cpu_SR[sr], s);
-    return false;
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();
+    }
+    gen_helper_waiti(cpu_env, pc, intlevel);
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_end();
+    }
+    tcg_temp_free(pc);
+    tcg_temp_free(intlevel);

 }
 }

+#endif

 
 

-#ifndef CONFIG_USER_ONLY
-static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static bool gen_window_check(DisasContext *dc, uint32_t mask)

 {
 {

-    gen_helper_wsr_windowbase(cpu_env, v);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
-}
+    unsigned r = 31 - clz32(mask);

 
 

-static bool gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
+    if (r / 4 > dc->window) {
+        TCGv_i32 pc = tcg_const_i32(dc->pc);
+        TCGv_i32 w = tcg_const_i32(r / 4);
+
+        gen_helper_window_check(cpu_env, pc, w);
+        dc->base.is_jmp = DISAS_NORETURN;
+        return false;
+    }

     return true;
 }
 
     return true;
 }
 

-static bool gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)

 {
 {

-    tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
-    return false;
+    TCGv_i32 m = tcg_temp_new_i32();
+
+    if (hi) {
+        (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
+    } else {
+        (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
+    }
+    return m;

 }
 
 }
 

-static bool gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[])

 {
 {

-    gen_helper_wsr_rasid(cpu_env, v);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
+    TCGLabel *label = gen_new_label();
+
+    tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label);
+    gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
+    gen_set_label(label);

 }
 
 }
 

-static bool gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)

 {
 {

-    tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
-    return false;
+    return xtensa_isa_length_from_chars(dc->config->isa, &op0);

 }
 
 }
 

-static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static int gen_postprocess(DisasContext *dc, int slot)

 {
 {

-    gen_helper_wsr_ibreakenable(cpu_env, v);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
+    uint32_t op_flags = dc->op_flags;
+
+#ifndef CONFIG_USER_ONLY
+    if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
+        if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+            gen_io_start();
+        }
+        gen_helper_check_interrupts(cpu_env);
+        if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+            gen_io_end();
+        }
+    }
+#endif
+    if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
+        gen_helper_sync_windowbase(cpu_env);
+    }
+    if (op_flags & XTENSA_OP_EXIT_TB_M1) {
+        slot = -1;
+    }
+    return slot;

 }
 
 }
 

-static bool gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+struct opcode_arg_copy {
+    uint32_t resource;
+    void *temp;
+    OpcodeArg *arg;
+};
+
+struct opcode_arg_info {
+    uint32_t resource;
+    int index;
+};
+
+struct slot_prop {
+    XtensaOpcodeOps *ops;
+    OpcodeArg arg[MAX_OPCODE_ARGS];
+    struct opcode_arg_info in[MAX_OPCODE_ARGS];
+    struct opcode_arg_info out[MAX_OPCODE_ARGS];
+    unsigned n_in;
+    unsigned n_out;
+    uint32_t op_flags;
+};
+
+enum resource_type {
+    RES_REGFILE,
+    RES_STATE,
+    RES_MAX,
+};
+
+static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n)

 {
 {

-    gen_helper_wsr_memctl(cpu_env, v);
-    return false;
+    assert(r < RES_MAX && g < 256 && n < 65536);
+    return (r << 24) | (g << 16) | n;

 }
 
 }
 

-static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static enum resource_type get_resource_type(uint32_t resource)

 {
 {

-    tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
-    return false;
+    return resource >> 24;

 }
 
 }
 

-static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+/*
+ * a depends on b if b must be executed before a,
+ * because a's side effects will destroy b's inputs.
+ */
+static bool op_depends_on(const struct slot_prop *a,
+                          const struct slot_prop *b)

 {
 {

-    unsigned id = sr - IBREAKA;
+    unsigned i = 0;
+    unsigned j = 0;

 
 

-    if (id < dc->config->nibreak) {
-        TCGv_i32 tmp = tcg_const_i32(id);
-        gen_helper_wsr_ibreaka(cpu_env, tmp, v);
-        tcg_temp_free(tmp);
-        gen_jumpi_check_loop_end(dc, 0);
+    if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
+        return true;
+    }
+    if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
+        (b->op_flags & XTENSA_OP_LOAD_STORE)) {

         return true;
     }
         return true;
     }

+    while (i < a->n_out && j < b->n_in) {
+        if (a->out[i].resource < b->in[j].resource) {
+            ++i;
+        } else if (a->out[i].resource > b->in[j].resource) {
+            ++j;
+        } else {
+            return true;
+        }
+    }

     return false;
 }
 
     return false;
 }
 

-static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+/*
+ * Try to break a dependency on b, append temporary register copy records
+ * to the end of copy and update n_copy in case of success.
+ * This is not always possible: e.g. control flow must always be the last,
+ * load/store must be first and state dependencies are not supported yet.
+ */
+static bool break_dependency(struct slot_prop *a,
+                             struct slot_prop *b,
+                             struct opcode_arg_copy *copy,
+                             unsigned *n_copy)

 {
 {

-    unsigned id = sr - DBREAKA;
+    unsigned i = 0;
+    unsigned j = 0;
+    unsigned n = *n_copy;
+    bool rv = false;

 
 

-    if (id < dc->config->ndbreak) {
-        TCGv_i32 tmp = tcg_const_i32(id);
-        gen_helper_wsr_dbreaka(cpu_env, tmp, v);
-        tcg_temp_free(tmp);
+    if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
+        return false;

     }
     }

-    return false;
-}
-
-static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    unsigned id = sr - DBREAKC;
+    if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
+        (b->op_flags & XTENSA_OP_LOAD_STORE)) {
+        return false;
+    }
+    while (i < a->n_out && j < b->n_in) {
+        if (a->out[i].resource < b->in[j].resource) {
+            ++i;
+        } else if (a->out[i].resource > b->in[j].resource) {
+            ++j;
+        } else {
+            int index = b->in[j].index;

 
 

-    if (id < dc->config->ndbreak) {
-        TCGv_i32 tmp = tcg_const_i32(id);
-        gen_helper_wsr_dbreakc(cpu_env, tmp, v);
-        tcg_temp_free(tmp);
+            if (get_resource_type(a->out[i].resource) != RES_REGFILE ||
+                index < 0) {
+                return false;
+            }
+            copy[n].resource = b->in[j].resource;
+            copy[n].arg = b->arg + index;
+            ++n;
+            ++j;
+            rv = true;
+        }

     }
     }

-    return false;
+    *n_copy = n;
+    return rv;

 }
 
 }
 

-static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
-}
+/*
+ * Calculate evaluation order for slot opcodes.
+ * Build opcode order graph and output its nodes in topological sort order.
+ * An edge a -> b in the graph means that opcode a must be followed by
+ * opcode b.
+ */
+static bool tsort(struct slot_prop *slot,
+                  struct slot_prop *sorted[],
+                  unsigned n,
+                  struct opcode_arg_copy *copy,
+                  unsigned *n_copy)
+{
+    struct tsnode {
+        unsigned n_in_edge;
+        unsigned n_out_edge;
+        unsigned out_edge[MAX_INSN_SLOTS];
+    } node[MAX_INSN_SLOTS];
+
+    unsigned in[MAX_INSN_SLOTS];
+    unsigned i, j;
+    unsigned n_in = 0;
+    unsigned n_out = 0;
+    unsigned n_edge = 0;
+    unsigned in_idx = 0;
+    unsigned node_idx = 0;
+
+    for (i = 0; i < n; ++i) {
+        node[i].n_in_edge = 0;
+        node[i].n_out_edge = 0;
+    }
+
+    for (i = 0; i < n; ++i) {
+        unsigned n_out_edge = 0;
+
+        for (j = 0; j < n; ++j) {
+            if (i != j && op_depends_on(slot + j, slot + i)) {
+                node[i].out_edge[n_out_edge] = j;
+                ++node[j].n_in_edge;
+                ++n_out_edge;
+                ++n_edge;
+            }
+        }
+        node[i].n_out_edge = n_out_edge;
+    }

 
 

-static void gen_check_interrupts(DisasContext *dc)
-{
-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_start();
+    for (i = 0; i < n; ++i) {
+        if (!node[i].n_in_edge) {
+            in[n_in] = i;
+            ++n_in;
+        }

     }
     }

-    gen_helper_check_interrupts(cpu_env);
-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_end();
+
+again:
+    for (; in_idx < n_in; ++in_idx) {
+        i = in[in_idx];
+        sorted[n_out] = slot + i;
+        ++n_out;
+        for (j = 0; j < node[i].n_out_edge; ++j) {
+            --n_edge;
+            if (--node[node[i].out_edge[j]].n_in_edge == 0) {
+                in[n_in] = node[i].out_edge[j];
+                ++n_in;
+            }
+        }
+    }
+    if (n_edge) {
+        for (; node_idx < n; ++node_idx) {
+            struct tsnode *cnode = node + node_idx;
+
+            if (cnode->n_in_edge) {
+                for (j = 0; j < cnode->n_out_edge; ++j) {
+                    unsigned k = cnode->out_edge[j];
+
+                    if (break_dependency(slot + k, slot + node_idx,
+                                         copy, n_copy) &&
+                        --node[k].n_in_edge == 0) {
+                        in[n_in] = k;
+                        ++n_in;
+                        --n_edge;
+                        cnode->out_edge[j] =
+                            cnode->out_edge[cnode->n_out_edge - 1];
+                        --cnode->n_out_edge;
+                        goto again;
+                    }
+                }
+            }
+        }
+    }
+    return n_edge == 0;
+}
+
+static void opcode_add_resource(struct slot_prop *op,
+                                uint32_t resource, char direction,
+                                int index)
+{
+    switch (direction) {
+    case 'm':
+    case 'i':
+        assert(op->n_in < ARRAY_SIZE(op->in));
+        op->in[op->n_in].resource = resource;
+        op->in[op->n_in].index = index;
+        ++op->n_in;
+        /* fall through */
+    case 'o':
+        if (direction == 'm' || direction == 'o') {
+            assert(op->n_out < ARRAY_SIZE(op->out));
+            op->out[op->n_out].resource = resource;
+            op->out[op->n_out].index = index;
+            ++op->n_out;
+        }
+        break;
+    default:
+        g_assert_not_reached();

     }
 }
 
     }
 }
 

-static bool gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static int resource_compare(const void *a, const void *b)

 {
 {

-    tcg_gen_andi_i32(cpu_SR[sr], v,
-            dc->config->inttype_mask[INTTYPE_SOFTWARE]);
-    gen_check_interrupts(dc);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
+    const struct opcode_arg_info *pa = a;
+    const struct opcode_arg_info *pb = b;
+
+    return pa->resource < pb->resource ?
+        -1 : (pa->resource > pb->resource ? 1 : 0);

 }
 
 }
 

-static bool gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static int arg_copy_compare(const void *a, const void *b)

 {
 {

-    TCGv_i32 tmp = tcg_temp_new_i32();
+    const struct opcode_arg_copy *pa = a;
+    const struct opcode_arg_copy *pb = b;

 
 

-    tcg_gen_andi_i32(tmp, v,
-            dc->config->inttype_mask[INTTYPE_EDGE] |
-            dc->config->inttype_mask[INTTYPE_NMI] |
-            dc->config->inttype_mask[INTTYPE_SOFTWARE]);
-    tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
-    tcg_temp_free(tmp);
-    gen_check_interrupts(dc);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
+    return pa->resource < pb->resource ?
+        -1 : (pa->resource > pb->resource ? 1 : 0);

 }
 
 }
 

-static bool gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)

 {
 {

-    tcg_gen_mov_i32(cpu_SR[sr], v);
-    gen_check_interrupts(dc);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
-}
-
-static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
-        PS_UM | PS_EXCM | PS_INTLEVEL;
-
-    if (option_enabled(dc, XTENSA_OPTION_MMU)) {
-        mask |= PS_RING;
-    }
-    tcg_gen_andi_i32(cpu_SR[sr], v, mask);
-    gen_check_interrupts(dc);
-    /* This can change mmu index and tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
-}
-
-static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_start();
-    }
-    gen_helper_wsr_ccount(cpu_env, v);
-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_end();
-        gen_jumpi_check_loop_end(dc, 0);
-        return true;
-    }
-    return false;
-}
-
-static bool gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    if (dc->icount) {
-        tcg_gen_mov_i32(dc->next_icount, v);
-    } else {
-        tcg_gen_mov_i32(cpu_SR[sr], v);
-    }
-    return false;
-}
-
-static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
-}
-
-static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
-{
-    uint32_t id = sr - CCOMPARE;
-    bool ret = false;
-
-    if (id < dc->config->nccompare) {
-        uint32_t int_bit = 1 << dc->config->timerint[id];
-        TCGv_i32 tmp = tcg_const_i32(id);
-
-        tcg_gen_mov_i32(cpu_SR[sr], v);
-        tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
-        if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-            gen_io_start();
-        }
-        gen_helper_update_ccompare(cpu_env, tmp);
-        if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-            gen_io_end();
-            gen_jumpi_check_loop_end(dc, 0);
-            ret = true;
-        }
-        tcg_temp_free(tmp);
-    }
-    return ret;
-}
-#else
-static void gen_check_interrupts(DisasContext *dc)
-{
-}
-#endif
-
-static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
-{
-    static bool (* const wsr_handler[256])(DisasContext *dc,
-            uint32_t sr, TCGv_i32 v) = {
-        [LBEG] = gen_wsr_lbeg,
-        [LEND] = gen_wsr_lend,
-        [SAR] = gen_wsr_sar,
-        [BR] = gen_wsr_br,
-        [LITBASE] = gen_wsr_litbase,
-        [ACCHI] = gen_wsr_acchi,
-#ifndef CONFIG_USER_ONLY
-        [WINDOW_BASE] = gen_wsr_windowbase,
-        [WINDOW_START] = gen_wsr_windowstart,
-        [PTEVADDR] = gen_wsr_ptevaddr,
-        [RASID] = gen_wsr_rasid,
-        [ITLBCFG] = gen_wsr_tlbcfg,
-        [DTLBCFG] = gen_wsr_tlbcfg,
-        [IBREAKENABLE] = gen_wsr_ibreakenable,
-        [MEMCTL] = gen_wsr_memctl,
-        [ATOMCTL] = gen_wsr_atomctl,
-        [IBREAKA] = gen_wsr_ibreaka,
-        [IBREAKA + 1] = gen_wsr_ibreaka,
-        [DBREAKA] = gen_wsr_dbreaka,
-        [DBREAKA + 1] = gen_wsr_dbreaka,
-        [DBREAKC] = gen_wsr_dbreakc,
-        [DBREAKC + 1] = gen_wsr_dbreakc,
-        [CPENABLE] = gen_wsr_cpenable,
-        [INTSET] = gen_wsr_intset,
-        [INTCLEAR] = gen_wsr_intclear,
-        [INTENABLE] = gen_wsr_intenable,
-        [PS] = gen_wsr_ps,
-        [CCOUNT] = gen_wsr_ccount,
-        [ICOUNT] = gen_wsr_icount,
-        [ICOUNTLEVEL] = gen_wsr_icountlevel,
-        [CCOMPARE] = gen_wsr_ccompare,
-        [CCOMPARE + 1] = gen_wsr_ccompare,
-        [CCOMPARE + 2] = gen_wsr_ccompare,
-#endif
-    };
-
-    if (wsr_handler[sr]) {
-        return wsr_handler[sr](dc, sr, s);
-    } else {
-        tcg_gen_mov_i32(cpu_SR[sr], s);
-        return false;
-    }
-}
-
-static void gen_wur(uint32_t ur, TCGv_i32 s)
-{
-    switch (ur) {
-    case FCR:
-        gen_helper_wur_fcr(cpu_env, s);
-        break;
-
-    case FSR:
-        tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
-        break;
-
-    default:
-        tcg_gen_mov_i32(cpu_UR[ur], s);
-        break;
-    }
-}
-
-static void gen_load_store_alignment(DisasContext *dc, int shift,
-        TCGv_i32 addr, bool no_hw_alignment)
-{
-    if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
-        tcg_gen_andi_i32(addr, addr, ~0 << shift);
-    } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
-            no_hw_alignment) {
-        TCGLabel *label = gen_new_label();
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
-        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
-        gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
-        gen_set_label(label);
-        tcg_temp_free(tmp);
-    }
-}
-
-#ifndef CONFIG_USER_ONLY
-static void gen_waiti(DisasContext *dc, uint32_t imm4)
-{
-    TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
-    TCGv_i32 intlevel = tcg_const_i32(imm4);
-
-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_start();
-    }
-    gen_helper_waiti(cpu_env, pc, intlevel);
-    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-        gen_io_end();
-    }
-    tcg_temp_free(pc);
-    tcg_temp_free(intlevel);
-    gen_jumpi_check_loop_end(dc, 0);
-}
-#endif
-
-static bool gen_window_check1(DisasContext *dc, unsigned r1)
-{
-    if (r1 / 4 > dc->window) {
-        TCGv_i32 pc = tcg_const_i32(dc->pc);
-        TCGv_i32 w = tcg_const_i32(r1 / 4);
-
-        gen_helper_window_check(cpu_env, pc, w);
-        dc->base.is_jmp = DISAS_NORETURN;
-        return false;
-    }
-    return true;
-}
-
-static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
-{
-    return gen_window_check1(dc, r1 > r2 ? r1 : r2);
-}
-
-static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
-        unsigned r3)
-{
-    return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
-}
-
-static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
-{
-    TCGv_i32 m = tcg_temp_new_i32();
-
-    if (hi) {
-        (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
-    } else {
-        (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
-    }
-    return m;
-}
-
-static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)
-{
-    return xtensa_isa_length_from_chars(dc->config->isa, &op0);
-}
-
-static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
-{
-    xtensa_isa isa = dc->config->isa;
-    unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)};
-    unsigned len = xtensa_op0_insn_len(dc, b[0]);
-    xtensa_format fmt;
-    int slot, slots;
-    unsigned i;
+    xtensa_isa isa = dc->config->isa;
+    unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)};
+    unsigned len = xtensa_op0_insn_len(dc, b[0]);
+    xtensa_format fmt;
+    int slot, slots;
+    unsigned i;
+    uint32_t op_flags = 0;
+    struct slot_prop slot_prop[MAX_INSN_SLOTS];
+    struct slot_prop *ordered[MAX_INSN_SLOTS];
+    struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS];
+    unsigned n_arg_copy = 0;
+    uint32_t debug_cause = 0;
+    uint32_t windowed_register = 0;
+    uint32_t coprocessor = 0;

 
     if (len == XTENSA_UNDEFINED) {
         qemu_log_mask(LOG_GUEST_ERROR,
 
     if (len == XTENSA_UNDEFINED) {
         qemu_log_mask(LOG_GUEST_ERROR,


@@ -964,13 +876,6 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
     }
 
     dc->base.pc_next = dc->pc + len;
     }
 
     dc->base.pc_next = dc->pc + len;

-    if (xtensa_option_enabled(dc->config, XTENSA_OPTION_LOOP) &&
-        dc->lbeg == dc->pc &&
-        ((dc->pc ^ (dc->base.pc_next - 1)) & -dc->config->inst_fetch_width)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "unaligned first instruction of a loop (pc = %08x)\n",
-                      dc->pc);
-    }

     for (i = 1; i < len; ++i) {
         b[i] = cpu_ldub_code(env, dc->pc + i);
     }
     for (i = 1; i < len; ++i) {
         b[i] = cpu_ldub_code(env, dc->pc + i);
     }


@@ -987,12 +892,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
     for (slot = 0; slot < slots; ++slot) {
         xtensa_opcode opc;
         int opnd, vopnd, opnds;
     for (slot = 0; slot < slots; ++slot) {
         xtensa_opcode opc;
         int opnd, vopnd, opnds;

-        uint32_t raw_arg[MAX_OPCODE_ARGS];
-        uint32_t arg[MAX_OPCODE_ARGS];
+        OpcodeArg *arg = slot_prop[slot].arg;

         XtensaOpcodeOps *ops;
 
         XtensaOpcodeOps *ops;
 

-        dc->raw_arg = raw_arg;
-

         xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf);
         opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf);
         if (opc == XTENSA_UNDEFINED) {
         xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf);
         opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf);
         if (opc == XTENSA_UNDEFINED) {


@@ -1005,33 +907,219 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
         opnds = xtensa_opcode_num_operands(isa, opc);
 
         for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
         opnds = xtensa_opcode_num_operands(isa, opc);
 
         for (opnd = vopnd = 0; opnd < opnds; ++opnd) {

+            void **register_file = NULL;
+
+            if (xtensa_operand_is_register(isa, opc, opnd)) {
+                xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
+
+                register_file = dc->config->regfile[rf];
+
+                if (rf == dc->config->a_regfile) {
+                    uint32_t v;
+
+                    xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
+                                             dc->slotbuf, &v);
+                    xtensa_operand_decode(isa, opc, opnd, &v);
+                    windowed_register |= 1u << v;
+                }
+            }

             if (xtensa_operand_is_visible(isa, opc, opnd)) {
                 uint32_t v;
 
                 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
                                          dc->slotbuf, &v);
                 xtensa_operand_decode(isa, opc, opnd, &v);
             if (xtensa_operand_is_visible(isa, opc, opnd)) {
                 uint32_t v;
 
                 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
                                          dc->slotbuf, &v);
                 xtensa_operand_decode(isa, opc, opnd, &v);

-                raw_arg[vopnd] = v;
+                arg[vopnd].raw_imm = v;

                 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
                     xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc);
                 }
                 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
                     xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc);
                 }

-                arg[vopnd] = v;
+                arg[vopnd].imm = v;
+                if (register_file) {
+                    arg[vopnd].in = register_file[v];
+                    arg[vopnd].out = register_file[v];
+                }

                 ++vopnd;
             }
         }
         ops = dc->config->opcode_ops[opc];
                 ++vopnd;
             }
         }
         ops = dc->config->opcode_ops[opc];

+        slot_prop[slot].ops = ops;
+

         if (ops) {
         if (ops) {

-            ops->translate(dc, arg, ops->par);
+            op_flags |= ops->op_flags;

         } else {
         } else {

-            qemu_log_mask(LOG_GUEST_ERROR,
+            qemu_log_mask(LOG_UNIMP,

                           "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
                           xtensa_opcode_name(isa, opc), slot, dc->pc);
                           "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
                           xtensa_opcode_name(isa, opc), slot, dc->pc);

+            op_flags |= XTENSA_OP_ILL;
+        }
+        if ((op_flags & XTENSA_OP_ILL) ||
+            (ops && ops->test_ill && ops->test_ill(dc, arg, ops->par))) {
+            gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
+            return;
+        }
+        if (ops->op_flags & XTENSA_OP_DEBUG_BREAK) {
+            debug_cause |= ops->par[0];
+        }
+        if (ops->test_overflow) {
+            windowed_register |= ops->test_overflow(dc, arg, ops->par);
+        }
+        coprocessor |= ops->coprocessor;
+
+        if (slots > 1) {
+            slot_prop[slot].n_in = 0;
+            slot_prop[slot].n_out = 0;
+            slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE;
+
+            opnds = xtensa_opcode_num_operands(isa, opc);
+
+            for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
+                bool visible = xtensa_operand_is_visible(isa, opc, opnd);
+
+                if (xtensa_operand_is_register(isa, opc, opnd)) {
+                    xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
+                    uint32_t v = 0;
+
+                    xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
+                                             dc->slotbuf, &v);
+                    xtensa_operand_decode(isa, opc, opnd, &v);
+                    opcode_add_resource(slot_prop + slot,
+                                        encode_resource(RES_REGFILE, rf, v),
+                                        xtensa_operand_inout(isa, opc, opnd),
+                                        visible ? vopnd : -1);
+                }
+                if (visible) {
+                    ++vopnd;
+                }
+            }
+
+            opnds = xtensa_opcode_num_stateOperands(isa, opc);
+
+            for (opnd = 0; opnd < opnds; ++opnd) {
+                xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd);
+
+                opcode_add_resource(slot_prop + slot,
+                                    encode_resource(RES_STATE, 0, state),
+                                    xtensa_stateOperand_inout(isa, opc, opnd),
+                                    -1);
+            }
+            if (xtensa_opcode_is_branch(isa, opc) ||
+                xtensa_opcode_is_jump(isa, opc) ||
+                xtensa_opcode_is_loop(isa, opc) ||
+                xtensa_opcode_is_call(isa, opc)) {
+                slot_prop[slot].op_flags |= XTENSA_OP_CONTROL_FLOW;
+            }
+
+            qsort(slot_prop[slot].in, slot_prop[slot].n_in,
+                  sizeof(slot_prop[slot].in[0]), resource_compare);
+            qsort(slot_prop[slot].out, slot_prop[slot].n_out,
+                  sizeof(slot_prop[slot].out[0]), resource_compare);
+        }
+    }
+
+    if (slots > 1) {
+        if (!tsort(slot_prop, ordered, slots, arg_copy, &n_arg_copy)) {
+            qemu_log_mask(LOG_UNIMP,
+                          "Circular resource dependencies (pc = %08x)\n",
+                          dc->pc);

             gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
             return;
         }
             gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
             return;
         }

+    } else {
+        ordered[0] = slot_prop + 0;
+    }
+
+    if ((op_flags & XTENSA_OP_PRIVILEGED) &&
+        !gen_check_privilege(dc)) {
+        return;
+    }
+
+    if (op_flags & XTENSA_OP_SYSCALL) {
+        gen_exception_cause(dc, SYSCALL_CAUSE);
+        return;
+    }
+
+    if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) {
+        gen_debug_exception(dc, debug_cause);
+        return;
+    }
+
+    if (windowed_register && !gen_window_check(dc, windowed_register)) {
+        return;
+    }
+
+    if (op_flags & XTENSA_OP_UNDERFLOW) {
+        TCGv_i32 tmp = tcg_const_i32(dc->pc);
+
+        gen_helper_test_underflow_retw(cpu_env, tmp);
+        tcg_temp_free(tmp);
+    }
+
+    if (op_flags & XTENSA_OP_ALLOCA) {
+        TCGv_i32 tmp = tcg_const_i32(dc->pc);
+
+        gen_helper_movsp(cpu_env, tmp);
+        tcg_temp_free(tmp);
+    }
+
+    if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
+        return;
+    }
+
+    if (n_arg_copy) {
+        uint32_t resource;
+        void *temp;
+        unsigned j;
+
+        qsort(arg_copy, n_arg_copy, sizeof(*arg_copy), arg_copy_compare);
+        for (i = j = 0; i < n_arg_copy; ++i) {
+            if (i == 0 || arg_copy[i].resource != resource) {
+                resource = arg_copy[i].resource;
+                temp = tcg_temp_local_new();
+                tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
+                arg_copy[i].temp = temp;
+
+                if (i != j) {
+                    arg_copy[j] = arg_copy[i];
+                }
+                ++j;
+            }
+            arg_copy[i].arg->in = temp;
+        }
+        n_arg_copy = j;
+    }
+
+    if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
+        for (slot = 0; slot < slots; ++slot) {
+            if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
+                gen_zero_check(dc, slot_prop[slot].arg);
+            }
+        }
+    }
+
+    dc->op_flags = op_flags;
+
+    for (slot = 0; slot < slots; ++slot) {
+        struct slot_prop *pslot = ordered[slot];
+        XtensaOpcodeOps *ops = pslot->ops;
+
+        ops->translate(dc, pslot->arg, ops->par);

     }
     }

+
+    for (i = 0; i < n_arg_copy; ++i) {
+        tcg_temp_free(arg_copy[i].temp);
+    }
+

     if (dc->base.is_jmp == DISAS_NEXT) {
     if (dc->base.is_jmp == DISAS_NEXT) {

-        gen_check_loop_end(dc, 0);
+        gen_postprocess(dc, 0);
+        dc->op_flags = 0;
+        if (op_flags & XTENSA_OP_EXIT_TB_M1) {
+            /* Change in mmu index, memory mapping or tb->flags; exit tb */
+            gen_jumpi_check_loop_end(dc, -1);
+        } else if (op_flags & XTENSA_OP_EXIT_TB_0) {
+            gen_jumpi_check_loop_end(dc, 0);
+        } else {
+            gen_check_loop_end(dc, 0);
+        }

     }
     dc->pc = dc->base.pc_next;
 }
     }
     dc->pc = dc->base.pc_next;
 }


@@ -1066,14 +1154,19 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
     dc->pc = dc->base.pc_first;
     dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
     dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
     dc->pc = dc->base.pc_first;
     dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
     dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;

-    dc->lbeg = env->sregs[LBEG];
-    dc->lend = env->sregs[LEND];
+    dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >>
+        XTENSA_CSBASE_LBEG_OFF_SHIFT;
+    dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) +
+        (dc->base.pc_first & TARGET_PAGE_MASK);

     dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
     dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
     dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
         XTENSA_TBFLAG_CPENABLE_SHIFT;
     dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
                  XTENSA_TBFLAG_WINDOW_SHIFT);
     dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
     dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
     dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
         XTENSA_TBFLAG_CPENABLE_SHIFT;
     dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
                  XTENSA_TBFLAG_WINDOW_SHIFT);

+    dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
+    dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >>
+                   XTENSA_TBFLAG_CALLINC_SHIFT);

 
     if (dc->config->isa) {
         dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
 
     if (dc->config->isa) {
         dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);


@@ -1208,66 +1301,63 @@ static const TranslatorOps xtensa_translator_ops = {
     .disas_log          = xtensa_tr_disas_log,
 };
 
     .disas_log          = xtensa_tr_disas_log,
 };
 

-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)

 {
     DisasContext dc = {};
 {
     DisasContext dc = {};

-    translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb);
+    translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);

 }
 
 }
 

-void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
-                           fprintf_function cpu_fprintf, int flags)
+void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)

 {
     XtensaCPU *cpu = XTENSA_CPU(cs);
     CPUXtensaState *env = &cpu->env;
 {
     XtensaCPU *cpu = XTENSA_CPU(cs);
     CPUXtensaState *env = &cpu->env;

+    xtensa_isa isa = env->config->isa;

     int i, j;
 
     int i, j;
 

-    cpu_fprintf(f, "PC=%08x\n\n", env->pc);
-
-    for (i = j = 0; i < 256; ++i) {
-        if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
-            cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
-                    (j++ % 4) == 3 ? '\n' : ' ');
-        }
-    }
+    qemu_fprintf(f, "PC=%08x\n\n", env->pc);

 
 

-    cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
+    for (i = j = 0; i < xtensa_isa_num_sysregs(isa); ++i) {
+        const uint32_t *reg =
+            xtensa_sysreg_is_user(isa, i) ? env->uregs : env->sregs;
+        int regno = xtensa_sysreg_number(isa, i);

 
 

-    for (i = j = 0; i < 256; ++i) {
-        if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
-            cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
-                    (j++ % 4) == 3 ? '\n' : ' ');
+        if (regno >= 0) {
+            qemu_fprintf(f, "%12s=%08x%c",
+                         xtensa_sysreg_name(isa, i),
+                         reg[regno],
+                         (j++ % 4) == 3 ? '\n' : ' ');

         }
     }
 
         }
     }
 

-    cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
+    qemu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");

 
     for (i = 0; i < 16; ++i) {
 
     for (i = 0; i < 16; ++i) {

-        cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
-                (i % 4) == 3 ? '\n' : ' ');
+        qemu_fprintf(f, " A%02d=%08x%c",
+                     i, env->regs[i], (i % 4) == 3 ? '\n' : ' ');

     }
 
     xtensa_sync_phys_from_window(env);
     }
 
     xtensa_sync_phys_from_window(env);

-    cpu_fprintf(f, "\n");
+    qemu_fprintf(f, "\n");

 
     for (i = 0; i < env->config->nareg; ++i) {
 
     for (i = 0; i < env->config->nareg; ++i) {

-        cpu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]);
+        qemu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]);

         if (i % 4 == 3) {
             bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0;
             bool cw = env->sregs[WINDOW_BASE] == i / 4;
 
         if (i % 4 == 3) {
             bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0;
             bool cw = env->sregs[WINDOW_BASE] == i / 4;
 

-            cpu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' ');
+            qemu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' ');

         }
     }
 
     if ((flags & CPU_DUMP_FPU) &&
         xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
         }
     }
 
     if ((flags & CPU_DUMP_FPU) &&
         xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {

-        cpu_fprintf(f, "\n");
+        qemu_fprintf(f, "\n");

 
         for (i = 0; i < 16; ++i) {
 
         for (i = 0; i < 16; ++i) {

-            cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
-                    float32_val(env->fregs[i].f32[FP_F32_LOW]),
-                    *(float *)(env->fregs[i].f32 + FP_F32_LOW),
-                    (i % 2) == 1 ? '\n' : ' ');
+            qemu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
+                         float32_val(env->fregs[i].f32[FP_F32_LOW]),
+                         *(float *)(env->fregs[i].f32 + FP_F32_LOW),
+                         (i % 2) == 1 ? '\n' : ' ');

         }
     }
 }
         }
     }
 }


@@ -1278,172 +1368,134 @@ void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
     env->pc = data[0];
 }
 
     env->pc = data[0];
 }
 

-static int compare_opcode_ops(const void *a, const void *b)
-{
-    return strcmp((const char *)a,
-                  ((const XtensaOpcodeOps *)b)->name);
-}
-
-XtensaOpcodeOps *
-xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
-                       const char *name)
-{
-    return bsearch(name, t->opcode, t->num_opcodes,
-                   sizeof(XtensaOpcodeOps), compare_opcode_ops);
-}
-
-static void translate_abs(DisasContext *dc, const uint32_t arg[],
+static void translate_abs(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 zero = tcg_const_i32(0);
-        TCGv_i32 neg = tcg_temp_new_i32();
+    TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 neg = tcg_temp_new_i32();

 
 

-        tcg_gen_neg_i32(neg, cpu_R[arg[1]]);
-        tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]],
-                            cpu_R[arg[1]], zero, cpu_R[arg[1]], neg);
-        tcg_temp_free(neg);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_neg_i32(neg, arg[1].in);
+    tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out,
+                        arg[1].in, zero, arg[1].in, neg);
+    tcg_temp_free(neg);
+    tcg_temp_free(zero);

 }
 
 }
 

-static void translate_add(DisasContext *dc, const uint32_t arg[],
+static void translate_add(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_add_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_addi(DisasContext *dc, const uint32_t arg[],
+static void translate_addi(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    tcg_gen_addi_i32(arg[0].out, arg[1].in, arg[2].imm);

 }
 
 }
 

-static void translate_addx(DisasContext *dc, const uint32_t arg[],
+static void translate_addx(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
-        tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
+    tcg_gen_add_i32(arg[0].out, tmp, arg[2].in);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_all(DisasContext *dc, const uint32_t arg[],
+static void translate_all(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
     uint32_t shift = par[1];
                           const uint32_t par[])
 {
     uint32_t shift = par[1];

-    TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]);
+    TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm);

     TCGv_i32 tmp = tcg_temp_new_i32();
 
     TCGv_i32 tmp = tcg_temp_new_i32();
 

-    tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
+    tcg_gen_and_i32(tmp, arg[1].in, mask);

     if (par[0]) {
     if (par[0]) {

-        tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]);
+        tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm);

     } else {
         tcg_gen_add_i32(tmp, tmp, mask);
     }
     } else {
         tcg_gen_add_i32(tmp, tmp, mask);
     }

-    tcg_gen_shri_i32(tmp, tmp, arg[1] + shift);
-    tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
-                        tmp, arg[0], 1);
+    tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift);
+    tcg_gen_deposit_i32(arg[0].out, arg[0].out,
+                        tmp, arg[0].imm, 1);

     tcg_temp_free(mask);
     tcg_temp_free(tmp);
 }
 
     tcg_temp_free(mask);
     tcg_temp_free(tmp);
 }
 

-static void translate_and(DisasContext *dc, const uint32_t arg[],
+static void translate_and(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_and_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_ball(DisasContext *dc, const uint32_t arg[],
+static void translate_ball(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
-        gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
+    gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_bany(DisasContext *dc, const uint32_t arg[],
+static void translate_bany(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
-        gen_brcondi(dc, par[0], tmp, 0, arg[2]);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
+    gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_b(DisasContext *dc, const uint32_t arg[],
+static void translate_b(DisasContext *dc, const OpcodeArg arg[],

                         const uint32_t par[])
 {
                         const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm);

 }
 
 }
 

-static void translate_bb(DisasContext *dc, const uint32_t arg[],
+static void translate_bb(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])
 {
                          const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {

 #ifdef TARGET_WORDS_BIGENDIAN
 #ifdef TARGET_WORDS_BIGENDIAN

-        TCGv_i32 bit = tcg_const_i32(0x80000000u);
+    TCGv_i32 bit = tcg_const_i32(0x80000000u);

 #else
 #else

-        TCGv_i32 bit = tcg_const_i32(0x00000001u);
+    TCGv_i32 bit = tcg_const_i32(0x00000001u);

 #endif
 #endif

-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f);
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_andi_i32(tmp, arg[1].in, 0x1f);

 #ifdef TARGET_WORDS_BIGENDIAN
 #ifdef TARGET_WORDS_BIGENDIAN

-        tcg_gen_shr_i32(bit, bit, tmp);
+    tcg_gen_shr_i32(bit, bit, tmp);

 #else
 #else

-        tcg_gen_shl_i32(bit, bit, tmp);
+    tcg_gen_shl_i32(bit, bit, tmp);

 #endif
 #endif

-        tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit);
-        gen_brcondi(dc, par[0], tmp, 0, arg[2]);
-        tcg_temp_free(tmp);
-        tcg_temp_free(bit);
-    }
+    tcg_gen_and_i32(tmp, arg[0].in, bit);
+    gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
+    tcg_temp_free(tmp);
+    tcg_temp_free(bit);

 }
 
 }
 

-static void translate_bbi(DisasContext *dc, const uint32_t arg[],
+static void translate_bbi(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 tmp = tcg_temp_new_i32();

 #ifdef TARGET_WORDS_BIGENDIAN
 #ifdef TARGET_WORDS_BIGENDIAN

-        tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]);
+    tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);

 #else
 #else

-        tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]);
+    tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);

 #endif
 #endif

-        gen_brcondi(dc, par[0], tmp, 0, arg[2]);
-        tcg_temp_free(tmp);
-    }
+    gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_bi(DisasContext *dc, const uint32_t arg[],
+static void translate_bi(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])
 {
                          const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]);
-    }
+    gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm);

 }
 
 }
 

-static void translate_bz(DisasContext *dc, const uint32_t arg[],
+static void translate_bz(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])
 {
                          const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]);
-    }
+    gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm);

 }
 
 enum {
 }
 
 enum {


@@ -1454,7 +1506,7 @@ enum {
     BOOLEAN_XOR,
 };
 
     BOOLEAN_XOR,
 };
 

-static void translate_boolean(DisasContext *dc, const uint32_t arg[],
+static void translate_boolean(DisasContext *dc, const OpcodeArg arg[],

                               const uint32_t par[])
 {
     static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = {
                               const uint32_t par[])
 {
     static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = {


@@ -1468,285 +1520,249 @@ static void translate_boolean(DisasContext *dc, const uint32_t arg[],
     TCGv_i32 tmp1 = tcg_temp_new_i32();
     TCGv_i32 tmp2 = tcg_temp_new_i32();
 
     TCGv_i32 tmp1 = tcg_temp_new_i32();
     TCGv_i32 tmp2 = tcg_temp_new_i32();
 

-    tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]);
-    tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]);
+    tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm);
+    tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm);

     op[par[0]](tmp1, tmp1, tmp2);
     op[par[0]](tmp1, tmp1, tmp2);

-    tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1);
+    tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1);

     tcg_temp_free(tmp1);
     tcg_temp_free(tmp2);
 }
 
     tcg_temp_free(tmp1);
     tcg_temp_free(tmp2);
 }
 

-static void translate_bp(DisasContext *dc, const uint32_t arg[],
+static void translate_bp(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
 
                          const uint32_t par[])
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
 

-    tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]);
-    gen_brcondi(dc, par[0], tmp, 0, arg[1]);
+    tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm);
+    gen_brcondi(dc, par[0], tmp, 0, arg[1].imm);

     tcg_temp_free(tmp);
 }
 
     tcg_temp_free(tmp);
 }
 

-static void translate_break(DisasContext *dc, const uint32_t arg[],
-                            const uint32_t par[])
-{
-    if (dc->debug) {
-        gen_debug_exception(dc, par[0]);
-    }
-}
-
-static void translate_call0(DisasContext *dc, const uint32_t arg[],
+static void translate_call0(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
     tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
                             const uint32_t par[])
 {
     tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);

-    gen_jumpi(dc, arg[0], 0);
+    gen_jumpi(dc, arg[0].imm, 0);

 }
 
 }
 

-static void translate_callw(DisasContext *dc, const uint32_t arg[],
+static void translate_callw(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check1(dc, par[0] << 2)) {
-        gen_callwi(dc, par[0], arg[0], 0);
-    }
+    TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
+    gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0));
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_callx0(DisasContext *dc, const uint32_t arg[],
+static void translate_callx0(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
-        gen_jump(dc, tmp);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_mov_i32(tmp, arg[0].in);
+    tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
+    gen_jump(dc, tmp);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_callxw(DisasContext *dc, const uint32_t arg[],
+static void translate_callxw(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], par[0] << 2)) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 tmp = tcg_temp_new_i32();

 
 

-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        gen_callw(dc, par[0], tmp);
-        tcg_temp_free(tmp);
-    }
+    tcg_gen_mov_i32(tmp, arg[0].in);
+    gen_callw_slot(dc, par[0], tmp, -1);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_clamps(DisasContext *dc, const uint32_t arg[],
+static void translate_clamps(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]);
-        TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1);
+    TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2].imm);
+    TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2].imm) - 1);

 
 

-        tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]);
-        tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2);
-        tcg_temp_free(tmp1);
-        tcg_temp_free(tmp2);
-    }
+    tcg_gen_smax_i32(tmp1, tmp1, arg[1].in);
+    tcg_gen_smin_i32(arg[0].out, tmp1, tmp2);
+    tcg_temp_free(tmp1);
+    tcg_temp_free(tmp2);

 }
 
 }
 

-static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[],
+static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[],

                                     const uint32_t par[])
 {
     /* TODO: GPIO32 may be a part of coprocessor */
                                     const uint32_t par[])
 {
     /* TODO: GPIO32 may be a part of coprocessor */

-    tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0]));
+    tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm));

 }
 
 }
 

-static void translate_const16(DisasContext *dc, const uint32_t arg[],
+static void translate_const16(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 c = tcg_const_i32(arg[1]);
+    TCGv_i32 c = tcg_const_i32(arg[1].imm);

 
 

-        tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16);
-        tcg_temp_free(c);
-    }
+    tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16);
+    tcg_temp_free(c);

 }
 
 }
 

-/* par[0]: privileged, par[1]: check memory access */
-static void translate_dcache(DisasContext *dc, const uint32_t arg[],
+static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if ((!par[0] || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0]) && par[1]) {
-        TCGv_i32 addr = tcg_temp_new_i32();
-        TCGv_i32 res = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 res = tcg_temp_new_i32();

 
 

-        tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
-        tcg_gen_qemu_ld8u(res, addr, dc->cring);
-        tcg_temp_free(addr);
-        tcg_temp_free(res);
-    }
+    tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
+    tcg_gen_qemu_ld8u(res, addr, dc->cring);
+    tcg_temp_free(addr);
+    tcg_temp_free(res);

 }
 
 }
 

-static void translate_depbits(DisasContext *dc, const uint32_t arg[],
+static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],

                               const uint32_t par[])
 {
                               const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]],
-                            arg[2], arg[3]);
+    tcg_gen_deposit_i32(arg[1].out, arg[1].in, arg[0].in,
+                        arg[2].imm, arg[3].imm);
+}
+
+static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[],
+                           const uint32_t par[])
+{
+    if (arg[0].imm > 3 || !dc->cwoe) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "Illegal entry instruction(pc = %08x)\n", dc->pc);
+        return true;
+    } else {
+        return false;

     }
 }
 
     }
 }
 

-static void translate_entry(DisasContext *dc, const uint32_t arg[],
+static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[],
+                                    const uint32_t par[])
+{
+    return 1 << (dc->callinc * 4);
+}
+
+static void translate_entry(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
     TCGv_i32 pc = tcg_const_i32(dc->pc);
                             const uint32_t par[])
 {
     TCGv_i32 pc = tcg_const_i32(dc->pc);

-    TCGv_i32 s = tcg_const_i32(arg[0]);
-    TCGv_i32 imm = tcg_const_i32(arg[1]);
+    TCGv_i32 s = tcg_const_i32(arg[0].imm);
+    TCGv_i32 imm = tcg_const_i32(arg[1].imm);

     gen_helper_entry(cpu_env, pc, s, imm);
     tcg_temp_free(imm);
     tcg_temp_free(s);
     tcg_temp_free(pc);
     gen_helper_entry(cpu_env, pc, s, imm);
     tcg_temp_free(imm);
     tcg_temp_free(s);
     tcg_temp_free(pc);

-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);

 }
 
 }
 

-static void translate_extui(DisasContext *dc, const uint32_t arg[],
+static void translate_extui(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        int maskimm = (1 << arg[3]) - 1;
+    int maskimm = (1 << arg[3].imm) - 1;

 
 

-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]);
-        tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm);
+    tcg_gen_andi_i32(arg[0].out, tmp, maskimm);
+    tcg_temp_free(tmp);

 }
 
 }
 

-/* par[0]: privileged, par[1]: check memory access */
-static void translate_icache(DisasContext *dc, const uint32_t arg[],
+static void translate_icache(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if ((!par[0] || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0]) && par[1]) {

 #ifndef CONFIG_USER_ONLY
 #ifndef CONFIG_USER_ONLY

-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();

 
 

-        tcg_gen_movi_i32(cpu_pc, dc->pc);
-        tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
-        gen_helper_itlb_hit_test(cpu_env, addr);
-        tcg_temp_free(addr);
+    tcg_gen_movi_i32(cpu_pc, dc->pc);
+    tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
+    gen_helper_itlb_hit_test(cpu_env, addr);
+    tcg_temp_free(addr);

 #endif
 #endif

-    }

 }
 
 }
 

-static void translate_itlb(DisasContext *dc, const uint32_t arg[],
+static void translate_itlb(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check1(dc, arg[0])) {

 #ifndef CONFIG_USER_ONLY
 #ifndef CONFIG_USER_ONLY

-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
+    TCGv_i32 dtlb = tcg_const_i32(par[0]);

 
 

-        gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb);
-        /* This could change memory mapping, so exit tb */
-        gen_jumpi_check_loop_end(dc, -1);
-        tcg_temp_free(dtlb);
+    gen_helper_itlb(cpu_env, arg[0].in, dtlb);
+    tcg_temp_free(dtlb);

 #endif
 #endif

-    }

 }
 
 }
 

-static void translate_ill(DisasContext *dc, const uint32_t arg[],
-                          const uint32_t par[])
-{
-    gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
-}
-
-static void translate_j(DisasContext *dc, const uint32_t arg[],
+static void translate_j(DisasContext *dc, const OpcodeArg arg[],

                         const uint32_t par[])
 {
                         const uint32_t par[])
 {

-    gen_jumpi(dc, arg[0], 0);
+    gen_jumpi(dc, arg[0].imm, 0);

 }
 
 }
 

-static void translate_jx(DisasContext *dc, const uint32_t arg[],
+static void translate_jx(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])
 {
                          const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        gen_jump(dc, cpu_R[arg[0]]);
-    }
+    gen_jump(dc, arg[0].in);

 }
 
 }
 

-static void translate_l32e(DisasContext *dc, const uint32_t arg[],
+static void translate_l32e(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();

 
 

-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
-        tcg_temp_free(addr);
-    }
+    tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
+    gen_load_store_alignment(dc, 2, addr, false);
+    tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, MO_TEUL);
+    tcg_temp_free(addr);

 }
 
 }
 

-static void translate_ldst(DisasContext *dc, const uint32_t arg[],
+static void translate_ldst(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();

 
 

-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        if (par[0] & MO_SIZE) {
-            gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]);
+    tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
+    if (par[0] & MO_SIZE) {
+        gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]);
+    }
+    if (par[2]) {
+        if (par[1]) {
+            tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);

         }
         }

-        if (par[2]) {
-            if (par[1]) {
-                tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);
-            }
-            tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
-        } else {
-            tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
-            if (par[1]) {
-                tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
-            }
+        tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, par[0]);
+    } else {
+        tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, par[0]);
+        if (par[1]) {
+            tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);

         }
         }

-        tcg_temp_free(addr);

     }
     }

+    tcg_temp_free(addr);

 }
 
 }
 

-static void translate_l32r(DisasContext *dc, const uint32_t arg[],
+static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp;
+    TCGv_i32 tmp;

 
 

-        if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
-            tmp = tcg_const_i32(dc->raw_arg[1] - 1);
-            tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
-        } else {
-            tmp = tcg_const_i32(arg[1]);
-        }
-        tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring);
-        tcg_temp_free(tmp);
+    if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
+        tmp = tcg_const_i32(arg[1].raw_imm - 1);
+        tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
+    } else {
+        tmp = tcg_const_i32(arg[1].imm);

     }
     }

+    tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_loop(DisasContext *dc, const uint32_t arg[],
+static void translate_loop(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        uint32_t lend = arg[1];
-        TCGv_i32 tmp = tcg_const_i32(lend);
-
-        tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1);
-        tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
-        gen_helper_wsr_lend(cpu_env, tmp);
-        tcg_temp_free(tmp);
+    uint32_t lend = arg[1].imm;

 
 

-        if (par[0] != TCG_COND_NEVER) {
-            TCGLabel *label = gen_new_label();
-            tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label);
-            gen_jumpi(dc, lend, 1);
-            gen_set_label(label);
-        }
+    tcg_gen_subi_i32(cpu_SR[LCOUNT], arg[0].in, 1);
+    tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
+    tcg_gen_movi_i32(cpu_SR[LEND], lend);

 
 

-        gen_jumpi(dc, dc->base.pc_next, 0);
+    if (par[0] != TCG_COND_NEVER) {
+        TCGLabel *label = gen_new_label();
+        tcg_gen_brcondi_i32(par[0], arg[0].in, 0, label);
+        gen_jumpi(dc, lend, 1);
+        gen_set_label(label);

     }
     }

+
+    gen_jumpi(dc, dc->base.pc_next, 0);

 }
 
 enum {
 }
 
 enum {


@@ -1767,499 +1783,418 @@ enum {
     MAC16_XH = 0x2,
 };
 
     MAC16_XH = 0x2,
 };
 

-enum {
-    MAC16_AA,
-    MAC16_AD,
-    MAC16_DA,
-    MAC16_DD,
-
-    MAC16_XD = 0x1,
-    MAC16_DX = 0x2,
-};
-
-static void translate_mac16(DisasContext *dc, const uint32_t arg[],
+static void translate_mac16(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
     int op = par[0];
                             const uint32_t par[])
 {
     int op = par[0];

-    bool is_m1_sr = par[1] & MAC16_DX;
-    bool is_m2_sr = par[1] & MAC16_XD;
-    unsigned half = par[2];
-    uint32_t ld_offset = par[3];
+    unsigned half = par[1];
+    uint32_t ld_offset = par[2];

     unsigned off = ld_offset ? 2 : 0;
     unsigned off = ld_offset ? 2 : 0;

-    uint32_t ar[3] = {0};
-    unsigned n_ar = 0;
-
-    if (op != MAC16_NONE) {
-        if (!is_m1_sr) {
-            ar[n_ar++] = arg[off];
-        }
-        if (!is_m2_sr) {
-            ar[n_ar++] = arg[off + 1];
-        }
-    }
+    TCGv_i32 vaddr = tcg_temp_new_i32();
+    TCGv_i32 mem32 = tcg_temp_new_i32();

 
     if (ld_offset) {
 
     if (ld_offset) {

-        ar[n_ar++] = arg[1];
+        tcg_gen_addi_i32(vaddr, arg[1].in, ld_offset);
+        gen_load_store_alignment(dc, 2, vaddr, false);
+        tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);

     }
     }

-
-    if (gen_window_check3(dc, ar[0], ar[1], ar[2])) {
-        TCGv_i32 vaddr = tcg_temp_new_i32();
-        TCGv_i32 mem32 = tcg_temp_new_i32();
-
-        if (ld_offset) {
-            tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset);
-            gen_load_store_alignment(dc, 2, vaddr, false);
-            tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
-        }
-        if (op != MAC16_NONE) {
-            TCGv_i32 m1 = gen_mac16_m(is_m1_sr ?
-                                      cpu_SR[MR + arg[off]] :
-                                      cpu_R[arg[off]],
-                                      half & MAC16_HX, op == MAC16_UMUL);
-            TCGv_i32 m2 = gen_mac16_m(is_m2_sr ?
-                                      cpu_SR[MR + arg[off + 1]] :
-                                      cpu_R[arg[off + 1]],
-                                      half & MAC16_XH, op == MAC16_UMUL);
-
-            if (op == MAC16_MUL || op == MAC16_UMUL) {
-                tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
-                if (op == MAC16_UMUL) {
-                    tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
-                } else {
-                    tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
-                }
+    if (op != MAC16_NONE) {
+        TCGv_i32 m1 = gen_mac16_m(arg[off].in,
+                                  half & MAC16_HX, op == MAC16_UMUL);
+        TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in,
+                                  half & MAC16_XH, op == MAC16_UMUL);
+
+        if (op == MAC16_MUL || op == MAC16_UMUL) {
+            tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
+            if (op == MAC16_UMUL) {
+                tcg_gen_movi_i32(cpu_SR[ACCHI], 0);

             } else {
             } else {

-                TCGv_i32 lo = tcg_temp_new_i32();
-                TCGv_i32 hi = tcg_temp_new_i32();
-
-                tcg_gen_mul_i32(lo, m1, m2);
-                tcg_gen_sari_i32(hi, lo, 31);
-                if (op == MAC16_MULA) {
-                    tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     lo, hi);
-                } else {
-                    tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     lo, hi);
-                }
-                tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
-
-                tcg_temp_free_i32(lo);
-                tcg_temp_free_i32(hi);
+                tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);

             }
             }

-            tcg_temp_free(m1);
-            tcg_temp_free(m2);
-        }
-        if (ld_offset) {
-            tcg_gen_mov_i32(cpu_R[arg[1]], vaddr);
-            tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32);
+        } else {
+            TCGv_i32 lo = tcg_temp_new_i32();
+            TCGv_i32 hi = tcg_temp_new_i32();
+
+            tcg_gen_mul_i32(lo, m1, m2);
+            tcg_gen_sari_i32(hi, lo, 31);
+            if (op == MAC16_MULA) {
+                tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 lo, hi);
+            } else {
+                tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 lo, hi);
+            }
+            tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
+
+            tcg_temp_free_i32(lo);
+            tcg_temp_free_i32(hi);

         }
         }

-        tcg_temp_free(vaddr);
-        tcg_temp_free(mem32);
+        tcg_temp_free(m1);
+        tcg_temp_free(m2);

     }
     }

+    if (ld_offset) {
+        tcg_gen_mov_i32(arg[1].out, vaddr);
+        tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32);
+    }
+    tcg_temp_free(vaddr);
+    tcg_temp_free(mem32);

 }
 
 }
 

-static void translate_memw(DisasContext *dc, const uint32_t arg[],
+static void translate_memw(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
     tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
 }
 
                            const uint32_t par[])
 {
     tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
 }
 

-static void translate_smin(DisasContext *dc, const uint32_t arg[],
+static void translate_smin(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_smin_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_umin(DisasContext *dc, const uint32_t arg[],
+static void translate_umin(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_umin_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_smax(DisasContext *dc, const uint32_t arg[],
+static void translate_smax(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_smax_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_umax(DisasContext *dc, const uint32_t arg[],
+static void translate_umax(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_umax_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_mov(DisasContext *dc, const uint32_t arg[],
+static void translate_mov(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_mov_i32(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_movcond(DisasContext *dc, const uint32_t arg[],
+static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],

                               const uint32_t par[])
 {
                               const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 zero = tcg_const_i32(0);

 
 

-        tcg_gen_movcond_i32(par[0], cpu_R[arg[0]],
-                            cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_movcond_i32(par[0], arg[0].out,
+                        arg[2].in, zero, arg[1].in, arg[0].in);
+    tcg_temp_free(zero);

 }
 
 }
 

-static void translate_movi(DisasContext *dc, const uint32_t arg[],
+static void translate_movi(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]);
-    }
+    tcg_gen_movi_i32(arg[0].out, arg[1].imm);

 }
 
 }
 

-static void translate_movp(DisasContext *dc, const uint32_t arg[],
+static void translate_movp(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 zero = tcg_const_i32(0);
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 tmp = tcg_temp_new_i32();

 
 

-        tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
-        tcg_gen_movcond_i32(par[0],
-                            cpu_R[arg[0]], tmp, zero,
-                            cpu_R[arg[1]], cpu_R[arg[0]]);
-        tcg_temp_free(tmp);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
+    tcg_gen_movcond_i32(par[0],
+                        arg[0].out, tmp, zero,
+                        arg[1].in, arg[0].in);
+    tcg_temp_free(tmp);
+    tcg_temp_free(zero);

 }
 
 }
 

-static void translate_movsp(DisasContext *dc, const uint32_t arg[],
+static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 pc = tcg_const_i32(dc->pc);
-        gen_helper_movsp(cpu_env, pc);
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-        tcg_temp_free(pc);
-    }
+    tcg_gen_mov_i32(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_mul16(DisasContext *dc, const uint32_t arg[],
+static void translate_mul16(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 v1 = tcg_temp_new_i32();
-        TCGv_i32 v2 = tcg_temp_new_i32();
+    TCGv_i32 v1 = tcg_temp_new_i32();
+    TCGv_i32 v2 = tcg_temp_new_i32();

 
 

-        if (par[0]) {
-            tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]);
-            tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]);
-        } else {
-            tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]);
-            tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]);
-        }
-        tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2);
-        tcg_temp_free(v2);
-        tcg_temp_free(v1);
+    if (par[0]) {
+        tcg_gen_ext16s_i32(v1, arg[1].in);
+        tcg_gen_ext16s_i32(v2, arg[2].in);
+    } else {
+        tcg_gen_ext16u_i32(v1, arg[1].in);
+        tcg_gen_ext16u_i32(v2, arg[2].in);

     }
     }

+    tcg_gen_mul_i32(arg[0].out, v1, v2);
+    tcg_temp_free(v2);
+    tcg_temp_free(v1);

 }
 
 }
 

-static void translate_mull(DisasContext *dc, const uint32_t arg[],
+static void translate_mull(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_mul_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_mulh(DisasContext *dc, const uint32_t arg[],
+static void translate_mulh(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 lo = tcg_temp_new();
+    TCGv_i32 lo = tcg_temp_new();

 
 

-        if (par[0]) {
-            tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-        } else {
-            tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-        }
-        tcg_temp_free(lo);
+    if (par[0]) {
+        tcg_gen_muls2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
+    } else {
+        tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in);

     }
     }

+    tcg_temp_free(lo);

 }
 
 }
 

-static void translate_neg(DisasContext *dc, const uint32_t arg[],
+static void translate_neg(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_neg_i32(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_nop(DisasContext *dc, const uint32_t arg[],
+static void translate_nop(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
 }
 
                           const uint32_t par[])
 {
 }
 

-static void translate_nsa(DisasContext *dc, const uint32_t arg[],
+static void translate_nsa(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_clrsb_i32(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_nsau(DisasContext *dc, const uint32_t arg[],
+static void translate_nsau(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32);
-    }
+    tcg_gen_clzi_i32(arg[0].out, arg[1].in, 32);

 }
 
 }
 

-static void translate_or(DisasContext *dc, const uint32_t arg[],
+static void translate_or(DisasContext *dc, const OpcodeArg arg[],

                          const uint32_t par[])
 {
                          const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_or_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_ptlb(DisasContext *dc, const uint32_t arg[],
+static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {

 #ifndef CONFIG_USER_ONLY
 #ifndef CONFIG_USER_ONLY

-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
+    TCGv_i32 dtlb = tcg_const_i32(par[0]);

 
 

-        tcg_gen_movi_i32(cpu_pc, dc->pc);
-        gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
-        tcg_temp_free(dtlb);
+    tcg_gen_movi_i32(cpu_pc, dc->pc);
+    gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
+    tcg_temp_free(dtlb);

 #endif
 #endif

-    }

 }
 
 }
 

-static void gen_zero_check(DisasContext *dc, const uint32_t arg[])
-{
-    TCGLabel *label = gen_new_label();
-
-    tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label);
-    gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
-    gen_set_label(label);
-}
-
-static void translate_quos(DisasContext *dc, const uint32_t arg[],
+static void translate_quos(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGLabel *label1 = gen_new_label();
-        TCGLabel *label2 = gen_new_label();
-
-        gen_zero_check(dc, arg);
-
-        tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000,
-                            label1);
-        tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff,
-                            label1);
-        tcg_gen_movi_i32(cpu_R[arg[0]],
-                         par[0] ? 0x80000000 : 0);
-        tcg_gen_br(label2);
-        gen_set_label(label1);
-        if (par[0]) {
-            tcg_gen_div_i32(cpu_R[arg[0]],
-                            cpu_R[arg[1]], cpu_R[arg[2]]);
-        } else {
-            tcg_gen_rem_i32(cpu_R[arg[0]],
-                            cpu_R[arg[1]], cpu_R[arg[2]]);
-        }
-        gen_set_label(label2);
+    TCGLabel *label1 = gen_new_label();
+    TCGLabel *label2 = gen_new_label();
+
+    tcg_gen_brcondi_i32(TCG_COND_NE, arg[1].in, 0x80000000,
+                        label1);
+    tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0xffffffff,
+                        label1);
+    tcg_gen_movi_i32(arg[0].out,
+                     par[0] ? 0x80000000 : 0);
+    tcg_gen_br(label2);
+    gen_set_label(label1);
+    if (par[0]) {
+        tcg_gen_div_i32(arg[0].out,
+                        arg[1].in, arg[2].in);
+    } else {
+        tcg_gen_rem_i32(arg[0].out,
+                        arg[1].in, arg[2].in);

     }
     }

+    gen_set_label(label2);

 }
 
 }
 

-static void translate_quou(DisasContext *dc, const uint32_t arg[],
+static void translate_quou(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        gen_zero_check(dc, arg);
-        if (par[0]) {
-            tcg_gen_divu_i32(cpu_R[arg[0]],
-                             cpu_R[arg[1]], cpu_R[arg[2]]);
-        } else {
-            tcg_gen_remu_i32(cpu_R[arg[0]],
-                             cpu_R[arg[1]], cpu_R[arg[2]]);
-        }
-    }
+    tcg_gen_divu_i32(arg[0].out,
+                     arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_read_impwire(DisasContext *dc, const uint32_t arg[],
+static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[],

                                    const uint32_t par[])
 {
                                    const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        /* TODO: GPIO32 may be a part of coprocessor */
-        tcg_gen_movi_i32(cpu_R[arg[0]], 0);
-    }
+    /* TODO: GPIO32 may be a part of coprocessor */
+    tcg_gen_movi_i32(arg[0].out, 0);

 }
 
 }
 

-static void translate_rer(DisasContext *dc, const uint32_t arg[],
+static void translate_remu(DisasContext *dc, const OpcodeArg arg[],
+                           const uint32_t par[])
+{
+    tcg_gen_remu_i32(arg[0].out,
+                     arg[1].in, arg[2].in);
+}
+
+static void translate_rer(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]);
-    }
+    gen_helper_rer(arg[0].out, cpu_env, arg[1].in);

 }
 
 }
 

-static void translate_ret(DisasContext *dc, const uint32_t arg[],
+static void translate_ret(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
     gen_jump(dc, cpu_R[0]);
 }
 
                           const uint32_t par[])
 {
     gen_jump(dc, cpu_R[0]);
 }
 

-static void translate_retw(DisasContext *dc, const uint32_t arg[],
+static bool test_ill_retw(DisasContext *dc, const OpcodeArg arg[],
+                          const uint32_t par[])
+{
+    if (!dc->cwoe) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "Illegal retw instruction(pc = %08x)\n", dc->pc);
+        return true;
+    } else {
+        TCGv_i32 tmp = tcg_const_i32(dc->pc);
+
+        gen_helper_test_ill_retw(cpu_env, tmp);
+        tcg_temp_free(tmp);
+        return false;
+    }
+}
+
+static void translate_retw(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    TCGv_i32 tmp = tcg_const_i32(dc->pc);
-    gen_helper_retw(tmp, cpu_env, tmp);
+    TCGv_i32 tmp = tcg_const_i32(1);
+    tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
+    tcg_gen_andc_i32(cpu_SR[WINDOW_START],
+                     cpu_SR[WINDOW_START], tmp);
+    tcg_gen_movi_i32(tmp, dc->pc);
+    tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
+    gen_helper_retw(cpu_env, cpu_R[0]);

     gen_jump(dc, tmp);
     tcg_temp_free(tmp);
 }
 
     gen_jump(dc, tmp);
     tcg_temp_free(tmp);
 }
 

-static void translate_rfde(DisasContext *dc, const uint32_t arg[],
+static void translate_rfde(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_check_privilege(dc)) {
-        gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);
-    }
+    gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);

 }
 
 }
 

-static void translate_rfe(DisasContext *dc, const uint32_t arg[],
+static void translate_rfe(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_check_privilege(dc)) {
-        tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
-        gen_check_interrupts(dc);
-        gen_jump(dc, cpu_SR[EPC1]);
-    }
+    tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
+    gen_jump(dc, cpu_SR[EPC1]);

 }
 
 }
 

-static void translate_rfi(DisasContext *dc, const uint32_t arg[],
+static void translate_rfi(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_check_privilege(dc)) {
-        tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]);
-        gen_check_interrupts(dc);
-        gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]);
-    }
+    tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0].imm - 2]);
+    gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]);

 }
 
 }
 

-static void translate_rfw(DisasContext *dc, const uint32_t arg[],
+static void translate_rfw(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_check_privilege(dc)) {
-        TCGv_i32 tmp = tcg_const_i32(1);
+    TCGv_i32 tmp = tcg_const_i32(1);

 
 

-        tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
-        tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
+    tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
+    tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);

 
 

-        if (par[0]) {
-            tcg_gen_andc_i32(cpu_SR[WINDOW_START],
-                             cpu_SR[WINDOW_START], tmp);
-        } else {
-            tcg_gen_or_i32(cpu_SR[WINDOW_START],
-                           cpu_SR[WINDOW_START], tmp);
-        }
-
-        gen_helper_restore_owb(cpu_env);
-        gen_check_interrupts(dc);
-        gen_jump(dc, cpu_SR[EPC1]);
-
-        tcg_temp_free(tmp);
+    if (par[0]) {
+        tcg_gen_andc_i32(cpu_SR[WINDOW_START],
+                         cpu_SR[WINDOW_START], tmp);
+    } else {
+        tcg_gen_or_i32(cpu_SR[WINDOW_START],
+                       cpu_SR[WINDOW_START], tmp);

     }
     }

+
+    tcg_temp_free(tmp);
+    gen_helper_restore_owb(cpu_env);
+    gen_jump(dc, cpu_SR[EPC1]);

 }
 
 }
 

-static void translate_rotw(DisasContext *dc, const uint32_t arg[],
+static void translate_rotw(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_check_privilege(dc)) {
-        TCGv_i32 tmp = tcg_const_i32(arg[0]);
-        gen_helper_rotw(cpu_env, tmp);
-        tcg_temp_free(tmp);
-        /* This can change tb->flags, so exit tb */
-        gen_jumpi_check_loop_end(dc, -1);
-    }
+    tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0].imm);

 }
 
 }
 

-static void translate_rsil(DisasContext *dc, const uint32_t arg[],
+static void translate_rsil(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check1(dc, arg[0])) {
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]);
-        tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
-        tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]);
-        gen_check_interrupts(dc);
-        gen_jumpi_check_loop_end(dc, 0);
-    }
+    tcg_gen_mov_i32(arg[0].out, cpu_SR[PS]);
+    tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
+    tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm);

 }
 
 }
 

-static void translate_rsr(DisasContext *dc, const uint32_t arg[],
+static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_check_sr(dc, par[0], SR_R) &&
-        (par[0] < 64 || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0])) {
-        if (gen_rsr(dc, cpu_R[arg[0]], par[0])) {
-            gen_jumpi_check_loop_end(dc, 0);
-        }
+    tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+}
+
+static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
+                                 const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();

     }
     }

+    gen_helper_update_ccount(cpu_env);
+    tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_end();
+    }
+#endif

 }
 
 }
 

-static void translate_rtlb(DisasContext *dc, const uint32_t arg[],
+static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[],
+                                   const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    TCGv_i32 tmp = tcg_temp_new_i32();
+
+    tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10);
+    tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]);
+    tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc);
+    tcg_temp_free(tmp);
+#endif
+}
+
+static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

+#ifndef CONFIG_USER_ONLY

     static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1,
                                    TCGv_i32 a2) = {
     static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1,
                                    TCGv_i32 a2) = {

-#ifndef CONFIG_USER_ONLY

         gen_helper_rtlb0,
         gen_helper_rtlb1,
         gen_helper_rtlb0,
         gen_helper_rtlb1,

-#endif

     };
     };

+    TCGv_i32 dtlb = tcg_const_i32(par[0]);

 
 

-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
-
-        helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
-        tcg_temp_free(dtlb);
-    }
+    helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
+    tcg_temp_free(dtlb);
+#endif

 }
 
 }
 

-static void translate_rur(DisasContext *dc, const uint32_t arg[],
+static void translate_rur(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        if (uregnames[par[0]].name) {
-            tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]);
-        } else {
-            qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]);
-        }
-    }
+    tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]);

 }
 
 }
 

-static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[],
+static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[],

                                     const uint32_t par[])
 {
     /* TODO: GPIO32 may be a part of coprocessor */
                                     const uint32_t par[])
 {
     /* TODO: GPIO32 may be a part of coprocessor */

-    tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]);
+    tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm);

 }
 
 #ifdef CONFIG_USER_ONLY
 }
 
 #ifdef CONFIG_USER_ONLY


@@ -2276,81 +2211,78 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
 }
 #endif
 
 }
 #endif
 

-static void translate_s32c1i(DisasContext *dc, const uint32_t arg[],
+static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp = tcg_temp_local_new_i32();
-        TCGv_i32 addr = tcg_temp_local_new_i32();
-
-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, true);
-        gen_check_atomctl(dc, addr);
-        tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1],
-                                   tmp, dc->cring, MO_TEUL);
-        tcg_temp_free(addr);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_local_new_i32();
+    TCGv_i32 addr = tcg_temp_local_new_i32();
+
+    tcg_gen_mov_i32(tmp, arg[0].in);
+    tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
+    gen_load_store_alignment(dc, 2, addr, true);
+    gen_check_atomctl(dc, addr);
+    tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1],
+                               tmp, dc->cring, MO_TEUL);
+    tcg_temp_free(addr);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_s32e(DisasContext *dc, const uint32_t arg[],
+static void translate_s32e(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();

 
 

-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
-        tcg_temp_free(addr);
-    }
+    tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
+    gen_load_store_alignment(dc, 2, addr, false);
+    tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, MO_TEUL);
+    tcg_temp_free(addr);

 }
 
 }
 

-static void translate_salt(DisasContext *dc, const uint32_t arg[],
+static void translate_salt(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_setcond_i32(par[0],
-                            cpu_R[arg[0]],
-                            cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_setcond_i32(par[0],
+                        arg[0].out,
+                        arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_sext(DisasContext *dc, const uint32_t arg[],
+static void translate_sext(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        int shift = 31 - arg[2];
+    int shift = 31 - arg[2].imm;

 
 

-        if (shift == 24) {
-            tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-        } else if (shift == 16) {
-            tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-        } else {
-            TCGv_i32 tmp = tcg_temp_new_i32();
-            tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift);
-            tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift);
-            tcg_temp_free(tmp);
-        }
+    if (shift == 24) {
+        tcg_gen_ext8s_i32(arg[0].out, arg[1].in);
+    } else if (shift == 16) {
+        tcg_gen_ext16s_i32(arg[0].out, arg[1].in);
+    } else {
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        tcg_gen_shli_i32(tmp, arg[1].in, shift);
+        tcg_gen_sari_i32(arg[0].out, tmp, shift);
+        tcg_temp_free(tmp);

     }
 }
 
     }
 }
 

-static void translate_simcall(DisasContext *dc, const uint32_t arg[],
-                              const uint32_t par[])
+static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[],
+                             const uint32_t par[])

 {
 {

-#ifndef CONFIG_USER_ONLY
-    if (semihosting_enabled()) {
-        if (gen_check_privilege(dc)) {
-            gen_helper_simcall(cpu_env);
-        }
-    } else
+#ifdef CONFIG_USER_ONLY
+    bool ill = true;
+#else
+    bool ill = !semihosting_enabled();

 #endif
 #endif

-    {
+    if (ill) {

         qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
         qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");

-        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

     }
     }

+    return ill;
+}
+
+static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
+                              const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    gen_helper_simcall(cpu_env);
+#endif

 }
 
 /*
 }
 
 /*


@@ -2361,280 +2293,468 @@ static void translate_simcall(DisasContext *dc, const uint32_t arg[],
                     TCGv_i64 tmp = tcg_temp_new_i64(); \
                     tcg_gen_extu_i32_i64(tmp, reg); \
                     tcg_gen_##cmd##_i64(v, v, tmp); \
                     TCGv_i64 tmp = tcg_temp_new_i64(); \
                     tcg_gen_extu_i32_i64(tmp, reg); \
                     tcg_gen_##cmd##_i64(v, v, tmp); \

-                    tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \
+                    tcg_gen_extrl_i64_i32(arg[0].out, v); \

                     tcg_temp_free_i64(v); \
                     tcg_temp_free_i64(tmp); \
                 } while (0)
 
 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
 
                     tcg_temp_free_i64(v); \
                     tcg_temp_free_i64(tmp); \
                 } while (0)
 
 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
 

-static void translate_sll(DisasContext *dc, const uint32_t arg[],
+static void translate_sll(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (dc->sar_m32_5bit) {
-            tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32);
-        } else {
-            TCGv_i64 v = tcg_temp_new_i64();
-            TCGv_i32 s = tcg_const_i32(32);
-            tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
-            tcg_gen_andi_i32(s, s, 0x3f);
-            tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
-            gen_shift_reg(shl, s);
-            tcg_temp_free(s);
-        }
+    if (dc->sar_m32_5bit) {
+        tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32);
+    } else {
+        TCGv_i64 v = tcg_temp_new_i64();
+        TCGv_i32 s = tcg_const_i32(32);
+        tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
+        tcg_gen_andi_i32(s, s, 0x3f);
+        tcg_gen_extu_i32_i64(v, arg[1].in);
+        gen_shift_reg(shl, s);
+        tcg_temp_free(s);

     }
 }
 
     }
 }
 

-static void translate_slli(DisasContext *dc, const uint32_t arg[],
+static void translate_slli(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (arg[2] == 32) {
-            qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
-                          arg[0], arg[1]);
-        }
-        tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f);
+    if (arg[2].imm == 32) {
+        qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
+                      arg[0].imm, arg[1].imm);

     }
     }

+    tcg_gen_shli_i32(arg[0].out, arg[1].in, arg[2].imm & 0x1f);

 }
 
 }
 

-static void translate_sra(DisasContext *dc, const uint32_t arg[],
+static void translate_sra(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (dc->sar_m32_5bit) {
-            tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
-        } else {
-            TCGv_i64 v = tcg_temp_new_i64();
-            tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]);
-            gen_shift(sar);
-        }
+    if (dc->sar_m32_5bit) {
+        tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
+    } else {
+        TCGv_i64 v = tcg_temp_new_i64();
+        tcg_gen_ext_i32_i64(v, arg[1].in);
+        gen_shift(sar);

     }
 }
 
     }
 }
 

-static void translate_srai(DisasContext *dc, const uint32_t arg[],
+static void translate_srai(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    tcg_gen_sari_i32(arg[0].out, arg[1].in, arg[2].imm);

 }
 
 }
 

-static void translate_src(DisasContext *dc, const uint32_t arg[],
+static void translate_src(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i64 v = tcg_temp_new_i64();
-        tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]);
-        gen_shift(shr);
-    }
+    TCGv_i64 v = tcg_temp_new_i64();
+    tcg_gen_concat_i32_i64(v, arg[2].in, arg[1].in);
+    gen_shift(shr);

 }
 
 }
 

-static void translate_srl(DisasContext *dc, const uint32_t arg[],
+static void translate_srl(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (dc->sar_m32_5bit) {
-            tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
-        } else {
-            TCGv_i64 v = tcg_temp_new_i64();
-            tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
-            gen_shift(shr);
-        }
+    if (dc->sar_m32_5bit) {
+        tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
+    } else {
+        TCGv_i64 v = tcg_temp_new_i64();
+        tcg_gen_extu_i32_i64(v, arg[1].in);
+        gen_shift(shr);

     }
 }
 
 #undef gen_shift
 #undef gen_shift_reg
 
     }
 }
 
 #undef gen_shift
 #undef gen_shift_reg
 

-static void translate_srli(DisasContext *dc, const uint32_t arg[],
+static void translate_srli(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    tcg_gen_shri_i32(arg[0].out, arg[1].in, arg[2].imm);

 }
 
 }
 

-static void translate_ssa8b(DisasContext *dc, const uint32_t arg[],
+static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
-        gen_left_shift_sar(dc, tmp);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, arg[0].in, 3);
+    gen_left_shift_sar(dc, tmp);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_ssa8l(DisasContext *dc, const uint32_t arg[],
+static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
-        gen_right_shift_sar(dc, tmp);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, arg[0].in, 3);
+    gen_right_shift_sar(dc, tmp);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_ssai(DisasContext *dc, const uint32_t arg[],
+static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    TCGv_i32 tmp = tcg_const_i32(arg[0]);
+    TCGv_i32 tmp = tcg_const_i32(arg[0].imm);

     gen_right_shift_sar(dc, tmp);
     tcg_temp_free(tmp);
 }
 
     gen_right_shift_sar(dc, tmp);
     tcg_temp_free(tmp);
 }
 

-static void translate_ssl(DisasContext *dc, const uint32_t arg[],
+static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        gen_left_shift_sar(dc, cpu_R[arg[0]]);
-    }
+    gen_left_shift_sar(dc, arg[0].in);

 }
 
 }
 

-static void translate_ssr(DisasContext *dc, const uint32_t arg[],
+static void translate_ssr(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        gen_right_shift_sar(dc, cpu_R[arg[0]]);
-    }
+    gen_right_shift_sar(dc, arg[0].in);

 }
 
 }
 

-static void translate_sub(DisasContext *dc, const uint32_t arg[],
+static void translate_sub(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_subx(DisasContext *dc, const uint32_t arg[],
+static void translate_subx(DisasContext *dc, const OpcodeArg arg[],

                            const uint32_t par[])
 {
                            const uint32_t par[])
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
-        tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
-        tcg_temp_free(tmp);
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
+    tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in);
+    tcg_temp_free(tmp);
+}
+
+static void translate_waiti(DisasContext *dc, const OpcodeArg arg[],
+                            const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    gen_waiti(dc, arg[0].imm);
+#endif
+}
+
+static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[],
+                           const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    TCGv_i32 dtlb = tcg_const_i32(par[0]);
+
+    gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
+    tcg_temp_free(dtlb);
+#endif
+}
+
+static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
+                          const uint32_t par[])
+{
+    gen_helper_wer(cpu_env, arg[0].in, arg[1].in);
+}
+
+static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
+                                     const uint32_t par[])
+{
+    /* TODO: GPIO32 may be a part of coprocessor */
+    tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in);
+}
+
+static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
+                          const uint32_t par[])
+{
+    tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
+}
+
+static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
+                               const uint32_t par[])
+{
+    tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
+}
+
+static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
+                                const uint32_t par[])
+{
+    tcg_gen_ext8s_i32(cpu_SR[par[0]], arg[0].in);
+}
+
+static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
+                                   const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    uint32_t id = par[0] - CCOMPARE;
+    TCGv_i32 tmp = tcg_const_i32(id);
+
+    assert(id < dc->config->nccompare);
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();

     }
     }

+    tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
+    gen_helper_update_ccompare(cpu_env, tmp);
+    tcg_temp_free(tmp);
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_end();
+    }
+#endif

 }
 
 }
 

-static void translate_syscall(DisasContext *dc, const uint32_t arg[],
-                              const uint32_t par[])
+static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[],
+                                 const uint32_t par[])

 {
 {

-    gen_exception_cause(dc, SYSCALL_CAUSE);
+#ifndef CONFIG_USER_ONLY
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();
+    }
+    gen_helper_wsr_ccount(cpu_env, arg[0].in);
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_end();
+    }
+#endif

 }
 
 }
 

-static void translate_waiti(DisasContext *dc, const uint32_t arg[],
-                            const uint32_t par[])
+static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
+                                  const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    unsigned id = par[0] - DBREAKA;
+    TCGv_i32 tmp = tcg_const_i32(id);
+
+    assert(id < dc->config->ndbreak);
+    gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
+    tcg_temp_free(tmp);
+#endif
+}
+
+static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
+                                  const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    unsigned id = par[0] - DBREAKC;
+    TCGv_i32 tmp = tcg_const_i32(id);
+
+    assert(id < dc->config->ndbreak);
+    gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
+    tcg_temp_free(tmp);
+#endif
+}
+
+static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
+                                  const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    unsigned id = par[0] - IBREAKA;
+    TCGv_i32 tmp = tcg_const_i32(id);
+
+    assert(id < dc->config->nibreak);
+    gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
+    tcg_temp_free(tmp);
+#endif
+}
+
+static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[],
+                                       const uint32_t par[])

 {
 {

-    if (gen_check_privilege(dc)) {

 #ifndef CONFIG_USER_ONLY
 #ifndef CONFIG_USER_ONLY

-        gen_waiti(dc, arg[0]);
+    gen_helper_wsr_ibreakenable(cpu_env, arg[0].in);

 #endif
 #endif

+}
+
+static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[],
+                                 const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    if (dc->icount) {
+        tcg_gen_mov_i32(dc->next_icount, arg[0].in);
+    } else {
+        tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);

     }
     }

+#endif

 }
 
 }
 

-static void translate_wtlb(DisasContext *dc, const uint32_t arg[],
-                           const uint32_t par[])
+static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[],
+                                   const uint32_t par[])

 {
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {

 #ifndef CONFIG_USER_ONLY
 #ifndef CONFIG_USER_ONLY

-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
+    gen_helper_intclear(cpu_env, arg[0].in);
+#endif
+}

 
 

-        gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb);
-        /* This could change memory mapping, so exit tb */
-        gen_jumpi_check_loop_end(dc, -1);
-        tcg_temp_free(dtlb);
+static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[],
+                                 const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    gen_helper_intset(cpu_env, arg[0].in);

 #endif
 #endif

+}
+
+static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[],
+                                 const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wsr_memctl(cpu_env, arg[0].in);
+#endif
+}
+
+static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[],
+                             const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
+        PS_UM | PS_EXCM | PS_INTLEVEL;
+
+    if (option_enabled(dc, XTENSA_OPTION_MMU)) {
+        mask |= PS_RING;

     }
     }

+    tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask);
+#endif

 }
 
 }
 

-static void translate_wer(DisasContext *dc, const uint32_t arg[],
-                          const uint32_t par[])
+static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[],
+                                const uint32_t par[])

 {
 {

-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]);
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wsr_rasid(cpu_env, arg[0].in);
+#endif
+}
+
+static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[],
+                              const uint32_t par[])
+{
+    tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f);
+    if (dc->sar_m32_5bit) {
+        tcg_gen_discard_i32(dc->sar_m32);

     }
     }

+    dc->sar_5bit = false;
+    dc->sar_m32_5bit = false;
+}
+
+static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg[],
+                                     const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    tcg_gen_mov_i32(cpu_windowbase_next, arg[0].in);
+#endif
+}
+
+static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg arg[],
+                                      const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+    tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in,
+                     (1 << dc->config->nareg / 4) - 1);
+#endif
+}
+
+static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
+                          const uint32_t par[])
+{
+    tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
+}
+
+static void translate_wur_fcr(DisasContext *dc, const OpcodeArg arg[],
+                              const uint32_t par[])
+{
+    gen_helper_wur_fcr(cpu_env, arg[0].in);

 }
 
 }
 

-static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[],
-                                     const uint32_t par[])
+static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[],
+                              const uint32_t par[])

 {
 {

-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        /* TODO: GPIO32 may be a part of coprocessor */
-        tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);

 }
 
 }
 

-static void translate_wsr(DisasContext *dc, const uint32_t arg[],
+static void translate_xor(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_check_sr(dc, par[0], SR_W) &&
-        (par[0] < 64 || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0])) {
-        gen_wsr(dc, par[0], cpu_R[arg[0]]);
-    }
+    tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_wur(DisasContext *dc, const uint32_t arg[],
+static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],

                           const uint32_t par[])
 {
                           const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0])) {
-        if (uregnames[par[0]].name) {
-            gen_wur(par[0], cpu_R[arg[0]]);
-        } else {
-            qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]);
-        }
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+
+    tcg_gen_mov_i32(tmp, arg[0].in);
+    tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+    tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_xor(DisasContext *dc, const uint32_t arg[],
-                          const uint32_t par[])
+static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
+                               const uint32_t par[])

 {
 {

-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+
+    tcg_gen_mov_i32(tmp, arg[0].in);
+    tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+    tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
+    tcg_temp_free(tmp);

 }
 
 }
 

-static void translate_xsr(DisasContext *dc, const uint32_t arg[],
-                          const uint32_t par[])
+static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
+                                 const uint32_t par[])

 {
 {

-    if (gen_check_sr(dc, par[0], SR_X) &&
-        (par[0] < 64 || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        bool rsr_end, wsr_end;
+#ifndef CONFIG_USER_ONLY
+    TCGv_i32 tmp = tcg_temp_new_i32();

 
 

-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        rsr_end = gen_rsr(dc, cpu_R[arg[0]], par[0]);
-        wsr_end = gen_wsr(dc, par[0], tmp);
-        tcg_temp_free(tmp);
-        if (rsr_end && !wsr_end) {
-            gen_jumpi_check_loop_end(dc, 0);
-        }
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();

     }
     }

+
+    gen_helper_update_ccount(cpu_env);
+    tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
+    gen_helper_wsr_ccount(cpu_env, arg[0].in);
+    tcg_gen_mov_i32(arg[0].out, tmp);
+    tcg_temp_free(tmp);
+
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_end();
+    }
+#endif

 }
 
 }
 

+#define gen_translate_xsr(name) \
+    static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \
+                                     const uint32_t par[]) \
+{ \
+    TCGv_i32 tmp = tcg_temp_new_i32(); \
+ \
+    tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
+    translate_wsr_##name(dc, arg, par); \
+    tcg_gen_mov_i32(arg[0].out, tmp); \
+    tcg_temp_free(tmp); \
+}
+
+gen_translate_xsr(acchi)
+gen_translate_xsr(ccompare)
+gen_translate_xsr(dbreaka)
+gen_translate_xsr(dbreakc)
+gen_translate_xsr(ibreaka)
+gen_translate_xsr(ibreakenable)
+gen_translate_xsr(icount)
+gen_translate_xsr(memctl)
+gen_translate_xsr(ps)
+gen_translate_xsr(rasid)
+gen_translate_xsr(sar)
+gen_translate_xsr(windowbase)
+gen_translate_xsr(windowstart)
+
+#undef gen_translate_xsr
+

 static const XtensaOpcodeOps core_ops[] = {
     {
         .name = "abs",
         .translate = translate_abs,
     }, {
 static const XtensaOpcodeOps core_ops[] = {
     {
         .name = "abs",
         .translate = translate_abs,
     }, {

-        .name = "add",
-        .translate = translate_add,
-    }, {
-        .name = "add.n",
+        .name = (const char * const[]) {
+            "add", "add.n", NULL,
+        },

         .translate = translate_add,
         .translate = translate_add,

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "addi",
-        .translate = translate_addi,
-    }, {
-        .name = "addi.n",
+        .name = (const char * const[]) {
+            "addi", "addi.n", NULL,
+        },

         .translate = translate_addi,
         .translate = translate_addi,

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "addmi",
         .translate = translate_addi,
     }, {
         .name = "addmi",
         .translate = translate_addi,


@@ -2678,121 +2798,187 @@ static const XtensaOpcodeOps core_ops[] = {
         .translate = translate_all,
         .par = (const uint32_t[]){false, 8},
     }, {
         .translate = translate_all,
         .par = (const uint32_t[]){false, 8},
     }, {

-        .name = "ball",
+        .name = (const char * const[]) {
+            "ball", "ball.w15", "ball.w18", NULL,
+        },

         .translate = translate_ball,
         .par = (const uint32_t[]){TCG_COND_EQ},
         .translate = translate_ball,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bany",
+        .name = (const char * const[]) {
+            "bany", "bany.w15", "bany.w18", NULL,
+        },

         .translate = translate_bany,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_bany,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bbc",
+        .name = (const char * const[]) {
+            "bbc", "bbc.w15", "bbc.w18", NULL,
+        },

         .translate = translate_bb,
         .par = (const uint32_t[]){TCG_COND_EQ},
         .translate = translate_bb,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bbci",
+        .name = (const char * const[]) {
+            "bbci", "bbci.w15", "bbci.w18", NULL,
+        },

         .translate = translate_bbi,
         .par = (const uint32_t[]){TCG_COND_EQ},
         .translate = translate_bbi,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bbs",
+        .name = (const char * const[]) {
+            "bbs", "bbs.w15", "bbs.w18", NULL,
+        },

         .translate = translate_bb,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_bb,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bbsi",
+        .name = (const char * const[]) {
+            "bbsi", "bbsi.w15", "bbsi.w18", NULL,
+        },

         .translate = translate_bbi,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_bbi,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "beq",
+        .name = (const char * const[]) {
+            "beq", "beq.w15", "beq.w18", NULL,
+        },

         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_EQ},
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "beqi",
+        .name = (const char * const[]) {
+            "beqi", "beqi.w15", "beqi.w18", NULL,
+        },

         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_EQ},
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "beqz",
-        .translate = translate_bz,
-        .par = (const uint32_t[]){TCG_COND_EQ},
-    }, {
-        .name = "beqz.n",
+        .name = (const char * const[]) {
+            "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL,
+        },

         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_EQ},
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "bf",
         .translate = translate_bp,
         .par = (const uint32_t[]){TCG_COND_EQ},
     }, {
     }, {
         .name = "bf",
         .translate = translate_bp,
         .par = (const uint32_t[]){TCG_COND_EQ},
     }, {

-        .name = "bge",
+        .name = (const char * const[]) {
+            "bge", "bge.w15", "bge.w18", NULL,
+        },

         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_GE},
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_GE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bgei",
+        .name = (const char * const[]) {
+            "bgei", "bgei.w15", "bgei.w18", NULL,
+        },

         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_GE},
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_GE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bgeu",
+        .name = (const char * const[]) {
+            "bgeu", "bgeu.w15", "bgeu.w18", NULL,
+        },

         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_GEU},
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_GEU},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bgeui",
+        .name = (const char * const[]) {
+            "bgeui", "bgeui.w15", "bgeui.w18", NULL,
+        },

         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_GEU},
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_GEU},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bgez",
+        .name = (const char * const[]) {
+            "bgez", "bgez.w15", "bgez.w18", NULL,
+        },

         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_GE},
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_GE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "blt",
+        .name = (const char * const[]) {
+            "blt", "blt.w15", "blt.w18", NULL,
+        },

         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_LT},
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_LT},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "blti",
+        .name = (const char * const[]) {
+            "blti", "blti.w15", "blti.w18", NULL,
+        },

         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_LT},
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_LT},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bltu",
+        .name = (const char * const[]) {
+            "bltu", "bltu.w15", "bltu.w18", NULL,
+        },

         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_LTU},
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_LTU},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bltui",
+        .name = (const char * const[]) {
+            "bltui", "bltui.w15", "bltui.w18", NULL,
+        },

         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_LTU},
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_LTU},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bltz",
+        .name = (const char * const[]) {
+            "bltz", "bltz.w15", "bltz.w18", NULL,
+        },

         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_LT},
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_LT},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bnall",
+        .name = (const char * const[]) {
+            "bnall", "bnall.w15", "bnall.w18", NULL,
+        },

         .translate = translate_ball,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_ball,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bne",
+        .name = (const char * const[]) {
+            "bne", "bne.w15", "bne.w18", NULL,
+        },

         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bnei",
+        .name = (const char * const[]) {
+            "bnei", "bnei.w15", "bnei.w18", NULL,
+        },

         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bnez",
+        .name = (const char * const[]) {
+            "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL,
+        },

         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "bnez.n",
-        .translate = translate_bz,
-        .par = (const uint32_t[]){TCG_COND_NE},
-    }, {
-        .name = "bnone",
+        .name = (const char * const[]) {
+            "bnone", "bnone.w15", "bnone.w18", NULL,
+        },

         .translate = translate_bany,
         .par = (const uint32_t[]){TCG_COND_EQ},
         .translate = translate_bany,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "break",
     }, {
         .name = "break",

-        .translate = translate_break,
+        .translate = translate_nop,

         .par = (const uint32_t[]){DEBUGCAUSE_BI},
         .par = (const uint32_t[]){DEBUGCAUSE_BI},

+        .op_flags = XTENSA_OP_DEBUG_BREAK,

     }, {
         .name = "break.n",
     }, {
         .name = "break.n",

-        .translate = translate_break,
+        .translate = translate_nop,

         .par = (const uint32_t[]){DEBUGCAUSE_BN},
         .par = (const uint32_t[]){DEBUGCAUSE_BN},

+        .op_flags = XTENSA_OP_DEBUG_BREAK,

     }, {
         .name = "bt",
         .translate = translate_bp,
     }, {
         .name = "bt",
         .translate = translate_bp,


@@ -2842,61 +3028,59 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "dhi",
         .translate = translate_dcache,
     }, {
         .name = "dhi",
         .translate = translate_dcache,

-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "dhu",
         .translate = translate_dcache,
     }, {
         .name = "dhu",
         .translate = translate_dcache,

-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "dhwb",
         .translate = translate_dcache,
     }, {
         .name = "dhwb",
         .translate = translate_dcache,

-        .par = (const uint32_t[]){false, true},

     }, {
         .name = "dhwbi",
         .translate = translate_dcache,
     }, {
         .name = "dhwbi",
         .translate = translate_dcache,

-        .par = (const uint32_t[]){false, true},

     }, {
         .name = "dii",
     }, {
         .name = "dii",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "diu",
     }, {
         .name = "diu",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "diwb",
     }, {
         .name = "diwb",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "diwbi",
     }, {
         .name = "diwbi",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "dpfl",
         .translate = translate_dcache,
     }, {
         .name = "dpfl",
         .translate = translate_dcache,

-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "dpfr",
     }, {
         .name = "dpfr",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,

     }, {
         .name = "dpfro",
     }, {
         .name = "dpfro",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,

     }, {
         .name = "dpfw",
     }, {
         .name = "dpfw",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,

     }, {
         .name = "dpfwo",
     }, {
         .name = "dpfwo",

-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,

     }, {
         .name = "dsync",
         .translate = translate_nop,
     }, {
         .name = "entry",
         .translate = translate_entry,
     }, {
         .name = "dsync",
         .translate = translate_nop,
     }, {
         .name = "entry",
         .translate = translate_entry,

+        .test_ill = test_ill_entry,
+        .test_overflow = test_overflow_entry,
+        .op_flags = XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_SYNC_REGISTER_WINDOW,

     }, {
         .name = "esync",
         .translate = translate_nop,
     }, {
         .name = "esync",
         .translate = translate_nop,


@@ -2911,48 +3095,47 @@ static const XtensaOpcodeOps core_ops[] = {
         .translate = translate_memw,
     }, {
         .name = "hwwdtlba",
         .translate = translate_memw,
     }, {
         .name = "hwwdtlba",

-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "hwwitlba",
     }, {
         .name = "hwwitlba",

-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "idtlb",
         .translate = translate_itlb,
         .par = (const uint32_t[]){true},
     }, {
         .name = "idtlb",
         .translate = translate_itlb,
         .par = (const uint32_t[]){true},

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "ihi",
         .translate = translate_icache,
     }, {
         .name = "ihi",
         .translate = translate_icache,

-        .par = (const uint32_t[]){false, true},

     }, {
         .name = "ihu",
         .translate = translate_icache,
     }, {
         .name = "ihu",
         .translate = translate_icache,

-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "iii",
     }, {
         .name = "iii",

-        .translate = translate_icache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "iitlb",
         .translate = translate_itlb,
         .par = (const uint32_t[]){false},
     }, {
         .name = "iitlb",
         .translate = translate_itlb,
         .par = (const uint32_t[]){false},

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "iiu",
     }, {
         .name = "iiu",

-        .translate = translate_icache,
-        .par = (const uint32_t[]){true, false},
-    }, {
-        .name = "ill",
-        .translate = translate_ill,
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
     }, {

-        .name = "ill.n",
-        .translate = translate_ill,
+        .name = (const char * const[]) {
+            "ill", "ill.n", NULL,
+        },
+        .op_flags = XTENSA_OP_ILL | XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "ipf",
     }, {
         .name = "ipf",

-        .translate = translate_icache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,

     }, {
         .name = "ipfl",
         .translate = translate_icache,
     }, {
         .name = "ipfl",
         .translate = translate_icache,

-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "isync",
         .translate = translate_nop,
     }, {
         .name = "isync",
         .translate = translate_nop,


@@ -2966,55 +3149,71 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "l16si",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TESW, false, false},
         .name = "l16si",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TESW, false, false},

+        .op_flags = XTENSA_OP_LOAD,

     }, {
         .name = "l16ui",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUW, false, false},
     }, {
         .name = "l16ui",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUW, false, false},

+        .op_flags = XTENSA_OP_LOAD,

     }, {
         .name = "l32ai",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, true, false},
     }, {
         .name = "l32ai",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, true, false},

+        .op_flags = XTENSA_OP_LOAD,

     }, {
         .name = "l32e",
         .translate = translate_l32e,
     }, {
         .name = "l32e",
         .translate = translate_l32e,

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD,

     }, {
     }, {

-        .name = "l32i",
-        .translate = translate_ldst,
-        .par = (const uint32_t[]){MO_TEUL, false, false},
-    }, {
-        .name = "l32i.n",
+        .name = (const char * const[]) {
+            "l32i", "l32i.n", NULL,
+        },

         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, false},
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, false},

+        .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_LOAD,

     }, {
         .name = "l32r",
         .translate = translate_l32r,
     }, {
         .name = "l32r",
         .translate = translate_l32r,

+        .op_flags = XTENSA_OP_LOAD,

     }, {
         .name = "l8ui",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_UB, false, false},
     }, {
         .name = "l8ui",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_UB, false, false},

+        .op_flags = XTENSA_OP_LOAD,

     }, {
         .name = "lddec",
         .translate = translate_mac16,
     }, {
         .name = "lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4},
+        .par = (const uint32_t[]){MAC16_NONE, 0, -4},
+        .op_flags = XTENSA_OP_LOAD,

     }, {
         .name = "ldinc",
         .translate = translate_mac16,
     }, {
         .name = "ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4},
+        .par = (const uint32_t[]){MAC16_NONE, 0, 4},
+        .op_flags = XTENSA_OP_LOAD,

     }, {
         .name = "ldpte",
     }, {
         .name = "ldpte",

-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,

     }, {
     }, {

-        .name = "loop",
+        .name = (const char * const[]) {
+            "loop", "loop.w15", NULL,
+        },

         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_NEVER},
         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_NEVER},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "loopgtz",
+        .name = (const char * const[]) {
+            "loopgtz", "loopgtz.w15", NULL,
+        },

         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_GT},
         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_GT},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "loopnez",
+        .name = (const char * const[]) {
+            "loopnez", "loopnez.w15", NULL,
+        },

         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_NE},
         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "max",
         .translate = translate_smax,
     }, {
         .name = "max",
         .translate = translate_smax,


@@ -3031,11 +3230,11 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "minu",
         .translate = translate_umin,
     }, {
         .name = "minu",
         .translate = translate_umin,
     }, {

-        .name = "mov",
-        .translate = translate_mov,
-    }, {
-        .name = "mov.n",
+        .name = (const char * const[]) {
+            "mov", "mov.n", NULL,
+        },

         .translate = translate_mov,
         .translate = translate_mov,

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "moveqz",
         .translate = translate_movcond,
     }, {
         .name = "moveqz",
         .translate = translate_movcond,


@@ -3065,6 +3264,7 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "movsp",
         .translate = translate_movsp,
     }, {
         .name = "movsp",
         .translate = translate_movsp,

+        .op_flags = XTENSA_OP_ALLOCA,

     }, {
         .name = "movt",
         .translate = translate_movp,
     }, {
         .name = "movt",
         .translate = translate_movp,


@@ -3072,67 +3272,67 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "mul.aa.hh",
         .translate = translate_mac16,
     }, {
         .name = "mul.aa.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},

     }, {
         .name = "mul.aa.hl",
         .translate = translate_mac16,
     }, {
         .name = "mul.aa.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},

     }, {
         .name = "mul.aa.lh",
         .translate = translate_mac16,
     }, {
         .name = "mul.aa.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},

     }, {
         .name = "mul.aa.ll",
         .translate = translate_mac16,
     }, {
         .name = "mul.aa.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},

     }, {
         .name = "mul.ad.hh",
         .translate = translate_mac16,
     }, {
         .name = "mul.ad.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},

     }, {
         .name = "mul.ad.hl",
         .translate = translate_mac16,
     }, {
         .name = "mul.ad.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},

     }, {
         .name = "mul.ad.lh",
         .translate = translate_mac16,
     }, {
         .name = "mul.ad.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},

     }, {
         .name = "mul.ad.ll",
         .translate = translate_mac16,
     }, {
         .name = "mul.ad.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},

     }, {
         .name = "mul.da.hh",
         .translate = translate_mac16,
     }, {
         .name = "mul.da.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},

     }, {
         .name = "mul.da.hl",
         .translate = translate_mac16,
     }, {
         .name = "mul.da.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},

     }, {
         .name = "mul.da.lh",
         .translate = translate_mac16,
     }, {
         .name = "mul.da.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},

     }, {
         .name = "mul.da.ll",
         .translate = translate_mac16,
     }, {
         .name = "mul.da.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},

     }, {
         .name = "mul.dd.hh",
         .translate = translate_mac16,
     }, {
         .name = "mul.dd.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},

     }, {
         .name = "mul.dd.hl",
         .translate = translate_mac16,
     }, {
         .name = "mul.dd.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},

     }, {
         .name = "mul.dd.lh",
         .translate = translate_mac16,
     }, {
         .name = "mul.dd.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},

     }, {
         .name = "mul.dd.ll",
         .translate = translate_mac16,
     }, {
         .name = "mul.dd.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},

     }, {
         .name = "mul16s",
         .translate = translate_mul16,
     }, {
         .name = "mul16s",
         .translate = translate_mul16,


@@ -3144,198 +3344,198 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "mula.aa.hh",
         .translate = translate_mac16,
     }, {
         .name = "mula.aa.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},

     }, {
         .name = "mula.aa.hl",
         .translate = translate_mac16,
     }, {
         .name = "mula.aa.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},

     }, {
         .name = "mula.aa.lh",
         .translate = translate_mac16,
     }, {
         .name = "mula.aa.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},

     }, {
         .name = "mula.aa.ll",
         .translate = translate_mac16,
     }, {
         .name = "mula.aa.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},

     }, {
         .name = "mula.ad.hh",
         .translate = translate_mac16,
     }, {
         .name = "mula.ad.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},

     }, {
         .name = "mula.ad.hl",
         .translate = translate_mac16,
     }, {
         .name = "mula.ad.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},

     }, {
         .name = "mula.ad.lh",
         .translate = translate_mac16,
     }, {
         .name = "mula.ad.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},

     }, {
         .name = "mula.ad.ll",
         .translate = translate_mac16,
     }, {
         .name = "mula.ad.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},

     }, {
         .name = "mula.da.hh",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},

     }, {
         .name = "mula.da.hh.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.hh.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},

     }, {
         .name = "mula.da.hh.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.hh.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},

     }, {
         .name = "mula.da.hl",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},

     }, {
         .name = "mula.da.hl.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.hl.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},

     }, {
         .name = "mula.da.hl.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.hl.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},

     }, {
         .name = "mula.da.lh",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},

     }, {
         .name = "mula.da.lh.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.lh.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},

     }, {
         .name = "mula.da.lh.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.lh.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},

     }, {
         .name = "mula.da.ll",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},

     }, {
         .name = "mula.da.ll.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.ll.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},

     }, {
         .name = "mula.da.ll.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.da.ll.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},

     }, {
         .name = "mula.dd.hh",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},

     }, {
         .name = "mula.dd.hh.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.hh.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},

     }, {
         .name = "mula.dd.hh.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.hh.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},

     }, {
         .name = "mula.dd.hl",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},

     }, {
         .name = "mula.dd.hl.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.hl.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},

     }, {
         .name = "mula.dd.hl.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.hl.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},

     }, {
         .name = "mula.dd.lh",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},

     }, {
         .name = "mula.dd.lh.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.lh.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},

     }, {
         .name = "mula.dd.lh.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.lh.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},

     }, {
         .name = "mula.dd.ll",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},

     }, {
         .name = "mula.dd.ll.lddec",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.ll.lddec",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},

     }, {
         .name = "mula.dd.ll.ldinc",
         .translate = translate_mac16,
     }, {
         .name = "mula.dd.ll.ldinc",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4},
+        .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},

     }, {
         .name = "mull",
         .translate = translate_mull,
     }, {
         .name = "muls.aa.hh",
         .translate = translate_mac16,
     }, {
         .name = "mull",
         .translate = translate_mull,
     }, {
         .name = "muls.aa.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},

     }, {
         .name = "muls.aa.hl",
         .translate = translate_mac16,
     }, {
         .name = "muls.aa.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},

     }, {
         .name = "muls.aa.lh",
         .translate = translate_mac16,
     }, {
         .name = "muls.aa.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},

     }, {
         .name = "muls.aa.ll",
         .translate = translate_mac16,
     }, {
         .name = "muls.aa.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},

     }, {
         .name = "muls.ad.hh",
         .translate = translate_mac16,
     }, {
         .name = "muls.ad.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},

     }, {
         .name = "muls.ad.hl",
         .translate = translate_mac16,
     }, {
         .name = "muls.ad.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},

     }, {
         .name = "muls.ad.lh",
         .translate = translate_mac16,
     }, {
         .name = "muls.ad.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},

     }, {
         .name = "muls.ad.ll",
         .translate = translate_mac16,
     }, {
         .name = "muls.ad.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},

     }, {
         .name = "muls.da.hh",
         .translate = translate_mac16,
     }, {
         .name = "muls.da.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},

     }, {
         .name = "muls.da.hl",
         .translate = translate_mac16,
     }, {
         .name = "muls.da.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},

     }, {
         .name = "muls.da.lh",
         .translate = translate_mac16,
     }, {
         .name = "muls.da.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},

     }, {
         .name = "muls.da.ll",
         .translate = translate_mac16,
     }, {
         .name = "muls.da.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},

     }, {
         .name = "muls.dd.hh",
         .translate = translate_mac16,
     }, {
         .name = "muls.dd.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},

     }, {
         .name = "muls.dd.hl",
         .translate = translate_mac16,
     }, {
         .name = "muls.dd.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},

     }, {
         .name = "muls.dd.lh",
         .translate = translate_mac16,
     }, {
         .name = "muls.dd.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},

     }, {
         .name = "muls.dd.ll",
         .translate = translate_mac16,
     }, {
         .name = "muls.dd.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},

     }, {
         .name = "mulsh",
         .translate = translate_mulh,
     }, {
         .name = "mulsh",
         .translate = translate_mulh,


@@ -3348,11 +3548,11 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "neg",
         .translate = translate_neg,
     }, {
         .name = "neg",
         .translate = translate_neg,
     }, {

-        .name = "nop",
-        .translate = translate_nop,
-    }, {
-        .name = "nop.n",
+        .name = (const char * const[]) {
+            "nop", "nop.n", NULL,
+        },

         .translate = translate_nop,
         .translate = translate_nop,

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "nsa",
         .translate = translate_nsa,
     }, {
         .name = "nsa",
         .translate = translate_nsa,


@@ -3374,26 +3574,31 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "pdtlb",
         .translate = translate_ptlb,
         .par = (const uint32_t[]){true},
         .name = "pdtlb",
         .translate = translate_ptlb,
         .par = (const uint32_t[]){true},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "pitlb",
         .translate = translate_ptlb,
         .par = (const uint32_t[]){false},
     }, {
         .name = "pitlb",
         .translate = translate_ptlb,
         .par = (const uint32_t[]){false},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "quos",
         .translate = translate_quos,
         .par = (const uint32_t[]){true},
     }, {
         .name = "quos",
         .translate = translate_quos,
         .par = (const uint32_t[]){true},

+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,

     }, {
         .name = "quou",
         .translate = translate_quou,
     }, {
         .name = "quou",
         .translate = translate_quou,

-        .par = (const uint32_t[]){true},
+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,

     }, {
         .name = "rdtlb0",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){true, 0},
     }, {
         .name = "rdtlb0",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){true, 0},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rdtlb1",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){true, 1},
     }, {
         .name = "rdtlb1",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){true, 1},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "read_impwire",
         .translate = translate_read_impwire,
     }, {
         .name = "read_impwire",
         .translate = translate_read_impwire,


@@ -3401,346 +3606,745 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "rems",
         .translate = translate_quos,
         .par = (const uint32_t[]){false},
         .name = "rems",
         .translate = translate_quos,
         .par = (const uint32_t[]){false},

+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,

     }, {
         .name = "remu",
     }, {
         .name = "remu",

-        .translate = translate_quou,
-        .par = (const uint32_t[]){false},
+        .translate = translate_remu,
+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,

     }, {
         .name = "rer",
         .translate = translate_rer,
     }, {
         .name = "rer",
         .translate = translate_rer,

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
     }, {

-        .name = "ret",
-        .translate = translate_ret,
-    }, {
-        .name = "ret.n",
+        .name = (const char * const[]) {
+            "ret", "ret.n", NULL,
+        },

         .translate = translate_ret,
         .translate = translate_ret,

+        .op_flags = XTENSA_OP_NAME_ARRAY,

     }, {
     }, {

-        .name = "retw",
-        .translate = translate_retw,
-    }, {
-        .name = "retw.n",
+        .name = (const char * const[]) {
+            "retw", "retw.n", NULL,
+        },

         .translate = translate_retw,
         .translate = translate_retw,

+        .test_ill = test_ill_retw,
+        .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY,

     }, {
         .name = "rfdd",
     }, {
         .name = "rfdd",

-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "rfde",
         .translate = translate_rfde,
     }, {
         .name = "rfde",
         .translate = translate_rfde,

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rfdo",
     }, {
         .name = "rfdo",

-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "rfe",
         .translate = translate_rfe,
     }, {
         .name = "rfe",
         .translate = translate_rfe,

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "rfi",
         .translate = translate_rfi,
     }, {
         .name = "rfi",
         .translate = translate_rfi,

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "rfwo",
         .translate = translate_rfw,
         .par = (const uint32_t[]){true},
     }, {
         .name = "rfwo",
         .translate = translate_rfw,
         .par = (const uint32_t[]){true},

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "rfwu",
         .translate = translate_rfw,
         .par = (const uint32_t[]){false},
     }, {
         .name = "rfwu",
         .translate = translate_rfw,
         .par = (const uint32_t[]){false},

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "ritlb0",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){false, 0},
     }, {
         .name = "ritlb0",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){false, 0},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "ritlb1",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){false, 1},
     }, {
         .name = "ritlb1",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){false, 1},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rotw",
         .translate = translate_rotw,
     }, {
         .name = "rotw",
         .translate = translate_rotw,

+        .op_flags = XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_SYNC_REGISTER_WINDOW,

     }, {
         .name = "rsil",
         .translate = translate_rsil,
     }, {
         .name = "rsil",
         .translate = translate_rsil,

+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "rsr.176",
         .translate = translate_rsr,
         .par = (const uint32_t[]){176},
     }, {
         .name = "rsr.176",
         .translate = translate_rsr,
         .par = (const uint32_t[]){176},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.208",
         .translate = translate_rsr,
         .par = (const uint32_t[]){208},
     }, {
         .name = "rsr.208",
         .translate = translate_rsr,
         .par = (const uint32_t[]){208},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.acchi",
         .translate = translate_rsr,
     }, {
         .name = "rsr.acchi",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){ACCHI},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ACCHI,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "rsr.acclo",
         .translate = translate_rsr,
     }, {
         .name = "rsr.acclo",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){ACCLO},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ACCLO,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "rsr.atomctl",
         .translate = translate_rsr,
     }, {
         .name = "rsr.atomctl",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){ATOMCTL},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ATOMCTL,
+            XTENSA_OPTION_ATOMCTL,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.br",
         .translate = translate_rsr,
     }, {
         .name = "rsr.br",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){BR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            BR,
+            XTENSA_OPTION_BOOLEAN,
+        },

     }, {
         .name = "rsr.cacheattr",
         .translate = translate_rsr,
     }, {
         .name = "rsr.cacheattr",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){CACHEATTR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CACHEATTR,
+            XTENSA_OPTION_CACHEATTR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ccompare0",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ccompare0",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){CCOMPARE},
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ccompare1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ccompare1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){CCOMPARE + 1},
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE + 1,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ccompare2",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ccompare2",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){CCOMPARE + 2},
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE + 2,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ccount",
     }, {
         .name = "rsr.ccount",

-        .translate = translate_rsr,
-        .par = (const uint32_t[]){CCOUNT},
+        .translate = translate_rsr_ccount,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CCOUNT,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "rsr.configid0",
         .translate = translate_rsr,
         .par = (const uint32_t[]){CONFIGID0},
     }, {
         .name = "rsr.configid0",
         .translate = translate_rsr,
         .par = (const uint32_t[]){CONFIGID0},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.configid1",
         .translate = translate_rsr,
         .par = (const uint32_t[]){CONFIGID1},
     }, {
         .name = "rsr.configid1",
         .translate = translate_rsr,
         .par = (const uint32_t[]){CONFIGID1},

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.cpenable",
         .translate = translate_rsr,
     }, {
         .name = "rsr.cpenable",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){CPENABLE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CPENABLE,
+            XTENSA_OPTION_COPROCESSOR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.dbreaka0",
         .translate = translate_rsr,
     }, {
         .name = "rsr.dbreaka0",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DBREAKA},
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKA,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.dbreaka1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.dbreaka1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DBREAKA + 1},
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKA + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.dbreakc0",
         .translate = translate_rsr,
     }, {
         .name = "rsr.dbreakc0",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DBREAKC},
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKC,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.dbreakc1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.dbreakc1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DBREAKC + 1},
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKC + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ddr",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ddr",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DDR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DDR,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.debugcause",
         .translate = translate_rsr,
     }, {
         .name = "rsr.debugcause",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DEBUGCAUSE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DEBUGCAUSE,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.depc",
         .translate = translate_rsr,
     }, {
         .name = "rsr.depc",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DEPC},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DEPC,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.dtlbcfg",
         .translate = translate_rsr,
     }, {
         .name = "rsr.dtlbcfg",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){DTLBCFG},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DTLBCFG,
+            XTENSA_OPTION_MMU,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.epc1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.epc1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPC1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EPC1,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.epc2",
         .translate = translate_rsr,
     }, {
         .name = "rsr.epc2",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPC1 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.epc3",
         .translate = translate_rsr,
     }, {
         .name = "rsr.epc3",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPC1 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.epc4",
         .translate = translate_rsr,
     }, {
         .name = "rsr.epc4",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPC1 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.epc5",
         .translate = translate_rsr,
     }, {
         .name = "rsr.epc5",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPC1 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.epc6",
         .translate = translate_rsr,
     }, {
         .name = "rsr.epc6",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPC1 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.epc7",
         .translate = translate_rsr,
     }, {
         .name = "rsr.epc7",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPC1 + 6},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 6,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.eps2",
         .translate = translate_rsr,
     }, {
         .name = "rsr.eps2",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPS2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.eps3",
         .translate = translate_rsr,
     }, {
         .name = "rsr.eps3",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPS2 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.eps4",
         .translate = translate_rsr,
     }, {
         .name = "rsr.eps4",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPS2 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.eps5",
         .translate = translate_rsr,
     }, {
         .name = "rsr.eps5",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPS2 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.eps6",
         .translate = translate_rsr,
     }, {
         .name = "rsr.eps6",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPS2 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.eps7",
         .translate = translate_rsr,
     }, {
         .name = "rsr.eps7",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EPS2 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.exccause",
         .translate = translate_rsr,
     }, {
         .name = "rsr.exccause",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCCAUSE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCCAUSE,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excsave1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excsave1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCSAVE1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCSAVE1,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excsave2",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excsave2",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excsave3",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excsave3",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excsave4",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excsave4",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excsave5",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excsave5",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excsave6",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excsave6",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excsave7",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excsave7",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 6},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 6,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.excvaddr",
         .translate = translate_rsr,
     }, {
         .name = "rsr.excvaddr",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){EXCVADDR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCVADDR,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ibreaka0",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ibreaka0",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){IBREAKA},
+        .test_ill = test_ill_ibreak,
+        .par = (const uint32_t[]){
+            IBREAKA,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ibreaka1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ibreaka1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){IBREAKA + 1},
+        .test_ill = test_ill_ibreak,
+        .par = (const uint32_t[]){
+            IBREAKA + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ibreakenable",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ibreakenable",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){IBREAKENABLE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            IBREAKENABLE,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.icount",
         .translate = translate_rsr,
     }, {
         .name = "rsr.icount",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){ICOUNT},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ICOUNT,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.icountlevel",
         .translate = translate_rsr,
     }, {
         .name = "rsr.icountlevel",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){ICOUNTLEVEL},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ICOUNTLEVEL,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.intclear",
         .translate = translate_rsr,
     }, {
         .name = "rsr.intclear",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){INTCLEAR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTCLEAR,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.intenable",
         .translate = translate_rsr,
     }, {
         .name = "rsr.intenable",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){INTENABLE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTENABLE,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.interrupt",
     }, {
         .name = "rsr.interrupt",

-        .translate = translate_rsr,
-        .par = (const uint32_t[]){INTSET},
+        .translate = translate_rsr_ccount,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTSET,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "rsr.intset",
     }, {
         .name = "rsr.intset",

-        .translate = translate_rsr,
-        .par = (const uint32_t[]){INTSET},
+        .translate = translate_rsr_ccount,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTSET,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "rsr.itlbcfg",
         .translate = translate_rsr,
     }, {
         .name = "rsr.itlbcfg",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){ITLBCFG},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ITLBCFG,
+            XTENSA_OPTION_MMU,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.lbeg",
         .translate = translate_rsr,
     }, {
         .name = "rsr.lbeg",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){LBEG},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LBEG,
+            XTENSA_OPTION_LOOP,
+        },

     }, {
         .name = "rsr.lcount",
         .translate = translate_rsr,
     }, {
         .name = "rsr.lcount",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){LCOUNT},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LCOUNT,
+            XTENSA_OPTION_LOOP,
+        },

     }, {
         .name = "rsr.lend",
         .translate = translate_rsr,
     }, {
         .name = "rsr.lend",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){LEND},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LEND,
+            XTENSA_OPTION_LOOP,
+        },

     }, {
         .name = "rsr.litbase",
         .translate = translate_rsr,
     }, {
         .name = "rsr.litbase",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){LITBASE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LITBASE,
+            XTENSA_OPTION_EXTENDED_L32R,
+        },

     }, {
         .name = "rsr.m0",
         .translate = translate_rsr,
     }, {
         .name = "rsr.m0",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "rsr.m1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.m1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MR + 1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 1,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "rsr.m2",
         .translate = translate_rsr,
     }, {
         .name = "rsr.m2",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MR + 2},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 2,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "rsr.m3",
         .translate = translate_rsr,
     }, {
         .name = "rsr.m3",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MR + 3},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 3,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "rsr.memctl",
         .translate = translate_rsr,
         .par = (const uint32_t[]){MEMCTL},
     }, {
         .name = "rsr.memctl",
         .translate = translate_rsr,
         .par = (const uint32_t[]){MEMCTL},

+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.mecr",
+        .translate = translate_rsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MECR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.mepc",
+        .translate = translate_rsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MEPC,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.meps",
+        .translate = translate_rsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MEPS,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.mesave",
+        .translate = translate_rsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESAVE,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.mesr",
+        .translate = translate_rsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.mevaddr",
+        .translate = translate_rsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.misc0",
         .translate = translate_rsr,
     }, {
         .name = "rsr.misc0",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MISC},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.misc1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.misc1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MISC + 1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 1,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.misc2",
         .translate = translate_rsr,
     }, {
         .name = "rsr.misc2",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MISC + 2},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 2,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.misc3",
         .translate = translate_rsr,
     }, {
         .name = "rsr.misc3",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){MISC + 3},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 3,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.prefctl",
+        .translate = translate_rsr,
+        .par = (const uint32_t[]){PREFCTL},

     }, {
         .name = "rsr.prid",
         .translate = translate_rsr,
     }, {
         .name = "rsr.prid",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){PRID},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            PRID,
+            XTENSA_OPTION_PROCESSOR_ID,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ps",
         .translate = translate_rsr,
     }, {
         .name = "rsr.ps",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){PS},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            PS,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.ptevaddr",
     }, {
         .name = "rsr.ptevaddr",

-        .translate = translate_rsr,
-        .par = (const uint32_t[]){PTEVADDR},
+        .translate = translate_rsr_ptevaddr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            PTEVADDR,
+            XTENSA_OPTION_MMU,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.rasid",
         .translate = translate_rsr,
     }, {
         .name = "rsr.rasid",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){RASID},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            RASID,
+            XTENSA_OPTION_MMU,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.sar",
         .translate = translate_rsr,
     }, {
         .name = "rsr.sar",
         .translate = translate_rsr,


@@ -3748,19 +4352,38 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "rsr.scompare1",
         .translate = translate_rsr,
     }, {
         .name = "rsr.scompare1",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){SCOMPARE1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            SCOMPARE1,
+            XTENSA_OPTION_CONDITIONAL_STORE,
+        },

     }, {
         .name = "rsr.vecbase",
         .translate = translate_rsr,
     }, {
         .name = "rsr.vecbase",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){VECBASE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            VECBASE,
+            XTENSA_OPTION_RELOCATABLE_VECTOR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.windowbase",
         .translate = translate_rsr,
     }, {
         .name = "rsr.windowbase",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){WINDOW_BASE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            WINDOW_BASE,
+            XTENSA_OPTION_WINDOWED_REGISTER,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsr.windowstart",
         .translate = translate_rsr,
     }, {
         .name = "rsr.windowstart",
         .translate = translate_rsr,

-        .par = (const uint32_t[]){WINDOW_START},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            WINDOW_START,
+            XTENSA_OPTION_WINDOWED_REGISTER,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "rsync",
         .translate = translate_nop,
     }, {
         .name = "rsync",
         .translate = translate_nop,


@@ -3772,10 +4395,12 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "rur.fcr",
         .translate = translate_rur,
         .par = (const uint32_t[]){FCR},
         .name = "rur.fcr",
         .translate = translate_rur,
         .par = (const uint32_t[]){FCR},

+        .coprocessor = 0x1,

     }, {
         .name = "rur.fsr",
         .translate = translate_rur,
         .par = (const uint32_t[]){FSR},
     }, {
         .name = "rur.fsr",
         .translate = translate_rur,
         .par = (const uint32_t[]){FSR},

+        .coprocessor = 0x1,

     }, {
         .name = "rur.threadptr",
         .translate = translate_rur,
     }, {
         .name = "rur.threadptr",
         .translate = translate_rur,


@@ -3784,32 +4409,32 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "s16i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUW, false, true},
         .name = "s16i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUW, false, true},

+        .op_flags = XTENSA_OP_STORE,

     }, {
         .name = "s32c1i",
         .translate = translate_s32c1i,
     }, {
         .name = "s32c1i",
         .translate = translate_s32c1i,

+        .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE,

     }, {
         .name = "s32e",
         .translate = translate_s32e,
     }, {
         .name = "s32e",
         .translate = translate_s32e,

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE,

     }, {
     }, {

-        .name = "s32i",
-        .translate = translate_ldst,
-        .par = (const uint32_t[]){MO_TEUL, false, true},
-    }, {
-        .name = "s32i.n",
-        .translate = translate_ldst,
-        .par = (const uint32_t[]){MO_TEUL, false, true},
-    }, {
-        .name = "s32nb",
+        .name = (const char * const[]) {
+            "s32i", "s32i.n", "s32nb", NULL,
+        },

         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, true},
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, true},

+        .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_STORE,

     }, {
         .name = "s32ri",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, true, true},
     }, {
         .name = "s32ri",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, true, true},

+        .op_flags = XTENSA_OP_STORE,

     }, {
         .name = "s8i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_UB, false, true},
     }, {
         .name = "s8i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_UB, false, true},

+        .op_flags = XTENSA_OP_STORE,

     }, {
         .name = "salt",
         .translate = translate_salt,
     }, {
         .name = "salt",
         .translate = translate_salt,


@@ -3827,6 +4452,8 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "simcall",
         .translate = translate_simcall,
     }, {
         .name = "simcall",
         .translate = translate_simcall,

+        .test_ill = test_ill_simcall,
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "sll",
         .translate = translate_sll,
     }, {
         .name = "sll",
         .translate = translate_sll,


@@ -3880,360 +4507,780 @@ static const XtensaOpcodeOps core_ops[] = {
         .par = (const uint32_t[]){3},
     }, {
         .name = "syscall",
         .par = (const uint32_t[]){3},
     }, {
         .name = "syscall",

-        .translate = translate_syscall,
+        .op_flags = XTENSA_OP_SYSCALL,

     }, {
         .name = "umul.aa.hh",
         .translate = translate_mac16,
     }, {
         .name = "umul.aa.hh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0},
+        .par = (const uint32_t[]){MAC16_UMUL, MAC16_HH, 0},

     }, {
         .name = "umul.aa.hl",
         .translate = translate_mac16,
     }, {
         .name = "umul.aa.hl",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0},
+        .par = (const uint32_t[]){MAC16_UMUL, MAC16_HL, 0},

     }, {
         .name = "umul.aa.lh",
         .translate = translate_mac16,
     }, {
         .name = "umul.aa.lh",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0},
+        .par = (const uint32_t[]){MAC16_UMUL, MAC16_LH, 0},

     }, {
         .name = "umul.aa.ll",
         .translate = translate_mac16,
     }, {
         .name = "umul.aa.ll",
         .translate = translate_mac16,

-        .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0},
+        .par = (const uint32_t[]){MAC16_UMUL, MAC16_LL, 0},

     }, {
         .name = "waiti",
         .translate = translate_waiti,
     }, {
         .name = "waiti",
         .translate = translate_waiti,

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wdtlb",
         .translate = translate_wtlb,
         .par = (const uint32_t[]){true},
     }, {
         .name = "wdtlb",
         .translate = translate_wtlb,
         .par = (const uint32_t[]){true},

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wer",
         .translate = translate_wer,
     }, {
         .name = "wer",
         .translate = translate_wer,

+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "witlb",
         .translate = translate_wtlb,
         .par = (const uint32_t[]){false},
     }, {
         .name = "witlb",
         .translate = translate_wtlb,
         .par = (const uint32_t[]){false},

+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wrmsk_expstate",
         .translate = translate_wrmsk_expstate,
     }, {
         .name = "wsr.176",
     }, {
         .name = "wrmsk_expstate",
         .translate = translate_wrmsk_expstate,
     }, {
         .name = "wsr.176",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){176},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "wsr.208",
     }, {
         .name = "wsr.208",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){208},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "wsr.acchi",
     }, {
         .name = "wsr.acchi",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){ACCHI},
+        .translate = translate_wsr_acchi,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ACCHI,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "wsr.acclo",
         .translate = translate_wsr,
     }, {
         .name = "wsr.acclo",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){ACCLO},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ACCLO,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "wsr.atomctl",
     }, {
         .name = "wsr.atomctl",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){ATOMCTL},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ATOMCTL,
+            XTENSA_OPTION_ATOMCTL,
+            0x3f,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.br",
     }, {
         .name = "wsr.br",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){BR},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            BR,
+            XTENSA_OPTION_BOOLEAN,
+            0xffff,
+        },

     }, {
         .name = "wsr.cacheattr",
         .translate = translate_wsr,
     }, {
         .name = "wsr.cacheattr",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){CACHEATTR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CACHEATTR,
+            XTENSA_OPTION_CACHEATTR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.ccompare0",
     }, {
         .name = "wsr.ccompare0",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){CCOMPARE},
+        .translate = translate_wsr_ccompare,
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wsr.ccompare1",
     }, {
         .name = "wsr.ccompare1",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){CCOMPARE + 1},
+        .translate = translate_wsr_ccompare,
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE + 1,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wsr.ccompare2",
     }, {
         .name = "wsr.ccompare2",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){CCOMPARE + 2},
+        .translate = translate_wsr_ccompare,
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE + 2,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wsr.ccount",
     }, {
         .name = "wsr.ccount",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){CCOUNT},
+        .translate = translate_wsr_ccount,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CCOUNT,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wsr.configid0",
     }, {
         .name = "wsr.configid0",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){CONFIGID0},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "wsr.configid1",
     }, {
         .name = "wsr.configid1",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){CONFIGID1},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "wsr.cpenable",
     }, {
         .name = "wsr.cpenable",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){CPENABLE},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CPENABLE,
+            XTENSA_OPTION_COPROCESSOR,
+            0xff,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wsr.dbreaka0",
     }, {
         .name = "wsr.dbreaka0",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){DBREAKA},
+        .translate = translate_wsr_dbreaka,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKA,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.dbreaka1",
     }, {
         .name = "wsr.dbreaka1",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){DBREAKA + 1},
+        .translate = translate_wsr_dbreaka,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKA + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.dbreakc0",
     }, {
         .name = "wsr.dbreakc0",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){DBREAKC},
+        .translate = translate_wsr_dbreakc,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKC,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.dbreakc1",
     }, {
         .name = "wsr.dbreakc1",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){DBREAKC + 1},
+        .translate = translate_wsr_dbreakc,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKC + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.ddr",
         .translate = translate_wsr,
     }, {
         .name = "wsr.ddr",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){DDR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DDR,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.debugcause",
     }, {
         .name = "wsr.debugcause",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){DEBUGCAUSE},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "wsr.depc",
         .translate = translate_wsr,
     }, {
         .name = "wsr.depc",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){DEPC},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DEPC,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.dtlbcfg",
     }, {
         .name = "wsr.dtlbcfg",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){DTLBCFG},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DTLBCFG,
+            XTENSA_OPTION_MMU,
+            0x01130000,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.epc1",
         .translate = translate_wsr,
     }, {
         .name = "wsr.epc1",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPC1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EPC1,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.epc2",
         .translate = translate_wsr,
     }, {
         .name = "wsr.epc2",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPC1 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.epc3",
         .translate = translate_wsr,
     }, {
         .name = "wsr.epc3",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPC1 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.epc4",
         .translate = translate_wsr,
     }, {
         .name = "wsr.epc4",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPC1 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.epc5",
         .translate = translate_wsr,
     }, {
         .name = "wsr.epc5",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPC1 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.epc6",
         .translate = translate_wsr,
     }, {
         .name = "wsr.epc6",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPC1 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.epc7",
         .translate = translate_wsr,
     }, {
         .name = "wsr.epc7",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPC1 + 6},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 6,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.eps2",
         .translate = translate_wsr,
     }, {
         .name = "wsr.eps2",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPS2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.eps3",
         .translate = translate_wsr,
     }, {
         .name = "wsr.eps3",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPS2 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.eps4",
         .translate = translate_wsr,
     }, {
         .name = "wsr.eps4",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPS2 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.eps5",
         .translate = translate_wsr,
     }, {
         .name = "wsr.eps5",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPS2 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.eps6",
         .translate = translate_wsr,
     }, {
         .name = "wsr.eps6",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPS2 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.eps7",
         .translate = translate_wsr,
     }, {
         .name = "wsr.eps7",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EPS2 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.exccause",
         .translate = translate_wsr,
     }, {
         .name = "wsr.exccause",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCCAUSE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCCAUSE,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excsave1",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excsave1",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCSAVE1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCSAVE1,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excsave2",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excsave2",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excsave3",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excsave3",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excsave4",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excsave4",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excsave5",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excsave5",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excsave6",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excsave6",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excsave7",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excsave7",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 6},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 6,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.excvaddr",
         .translate = translate_wsr,
     }, {
         .name = "wsr.excvaddr",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){EXCVADDR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCVADDR,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.ibreaka0",
     }, {
         .name = "wsr.ibreaka0",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){IBREAKA},
+        .translate = translate_wsr_ibreaka,
+        .test_ill = test_ill_ibreak,
+        .par = (const uint32_t[]){
+            IBREAKA,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wsr.ibreaka1",
     }, {
         .name = "wsr.ibreaka1",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){IBREAKA + 1},
+        .translate = translate_wsr_ibreaka,
+        .test_ill = test_ill_ibreak,
+        .par = (const uint32_t[]){
+            IBREAKA + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wsr.ibreakenable",
     }, {
         .name = "wsr.ibreakenable",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){IBREAKENABLE},
+        .translate = translate_wsr_ibreakenable,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            IBREAKENABLE,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "wsr.icount",
     }, {
         .name = "wsr.icount",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){ICOUNT},
+        .translate = translate_wsr_icount,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ICOUNT,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.icountlevel",
     }, {
         .name = "wsr.icountlevel",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){ICOUNTLEVEL},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ICOUNTLEVEL,
+            XTENSA_OPTION_DEBUG,
+            0xf,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wsr.intclear",
     }, {
         .name = "wsr.intclear",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){INTCLEAR},
+        .translate = translate_wsr_intclear,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTCLEAR,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "wsr.intenable",
         .translate = translate_wsr,
     }, {
         .name = "wsr.intenable",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){INTENABLE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTENABLE,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "wsr.interrupt",
         .translate = translate_wsr,
     }, {
         .name = "wsr.interrupt",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){INTSET},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTSET,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "wsr.intset",
     }, {
         .name = "wsr.intset",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){INTSET},
+        .translate = translate_wsr_intset,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTSET,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "wsr.itlbcfg",
     }, {
         .name = "wsr.itlbcfg",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){ITLBCFG},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ITLBCFG,
+            XTENSA_OPTION_MMU,
+            0x01130000,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.lbeg",
         .translate = translate_wsr,
     }, {
         .name = "wsr.lbeg",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){LBEG},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LBEG,
+            XTENSA_OPTION_LOOP,
+        },
+        .op_flags = XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wsr.lcount",
         .translate = translate_wsr,
     }, {
         .name = "wsr.lcount",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){LCOUNT},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LCOUNT,
+            XTENSA_OPTION_LOOP,
+        },

     }, {
         .name = "wsr.lend",
         .translate = translate_wsr,
     }, {
         .name = "wsr.lend",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){LEND},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LEND,
+            XTENSA_OPTION_LOOP,
+        },
+        .op_flags = XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wsr.litbase",
     }, {
         .name = "wsr.litbase",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){LITBASE},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LITBASE,
+            XTENSA_OPTION_EXTENDED_L32R,
+            0xfffff001,
+        },
+        .op_flags = XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wsr.m0",
         .translate = translate_wsr,
     }, {
         .name = "wsr.m0",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "wsr.m1",
         .translate = translate_wsr,
     }, {
         .name = "wsr.m1",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MR + 1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 1,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "wsr.m2",
         .translate = translate_wsr,
     }, {
         .name = "wsr.m2",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MR + 2},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 2,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "wsr.m3",
         .translate = translate_wsr,
     }, {
         .name = "wsr.m3",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MR + 3},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 3,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "wsr.memctl",
     }, {
         .name = "wsr.memctl",

-        .translate = translate_wsr,
+        .translate = translate_wsr_memctl,

         .par = (const uint32_t[]){MEMCTL},
         .par = (const uint32_t[]){MEMCTL},

+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.mecr",
+        .translate = translate_wsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MECR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.mepc",
+        .translate = translate_wsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MEPC,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.meps",
+        .translate = translate_wsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MEPS,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.mesave",
+        .translate = translate_wsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESAVE,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.mesr",
+        .translate = translate_wsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.mevaddr",
+        .translate = translate_wsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.misc0",
         .translate = translate_wsr,
     }, {
         .name = "wsr.misc0",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MISC},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.misc1",
         .translate = translate_wsr,
     }, {
         .name = "wsr.misc1",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MISC + 1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 1,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.misc2",
         .translate = translate_wsr,
     }, {
         .name = "wsr.misc2",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MISC + 2},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 2,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.misc3",
         .translate = translate_wsr,
     }, {
         .name = "wsr.misc3",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MISC + 3},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 3,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.mmid",
         .translate = translate_wsr,
     }, {
         .name = "wsr.mmid",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){MMID},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MMID,
+            XTENSA_OPTION_TRACE_PORT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.prefctl",
+        .translate = translate_wsr,
+        .par = (const uint32_t[]){PREFCTL},

     }, {
         .name = "wsr.prid",
     }, {
         .name = "wsr.prid",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){PRID},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "wsr.ps",
     }, {
         .name = "wsr.ps",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){PS},
+        .translate = translate_wsr_ps,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            PS,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "wsr.ptevaddr",
     }, {
         .name = "wsr.ptevaddr",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){PTEVADDR},
+        .translate = translate_wsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            PTEVADDR,
+            XTENSA_OPTION_MMU,
+            0xffc00000,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.rasid",
     }, {
         .name = "wsr.rasid",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){RASID},
+        .translate = translate_wsr_rasid,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            RASID,
+            XTENSA_OPTION_MMU,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wsr.sar",
     }, {
         .name = "wsr.sar",

-        .translate = translate_wsr,
+        .translate = translate_wsr_sar,

         .par = (const uint32_t[]){SAR},
     }, {
         .name = "wsr.scompare1",
         .translate = translate_wsr,
         .par = (const uint32_t[]){SAR},
     }, {
         .name = "wsr.scompare1",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){SCOMPARE1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            SCOMPARE1,
+            XTENSA_OPTION_CONDITIONAL_STORE,
+        },

     }, {
         .name = "wsr.vecbase",
         .translate = translate_wsr,
     }, {
         .name = "wsr.vecbase",
         .translate = translate_wsr,

-        .par = (const uint32_t[]){VECBASE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            VECBASE,
+            XTENSA_OPTION_RELOCATABLE_VECTOR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "wsr.windowbase",
     }, {
         .name = "wsr.windowbase",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){WINDOW_BASE},
+        .translate = translate_wsr_windowbase,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            WINDOW_BASE,
+            XTENSA_OPTION_WINDOWED_REGISTER,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_SYNC_REGISTER_WINDOW,

     }, {
         .name = "wsr.windowstart",
     }, {
         .name = "wsr.windowstart",

-        .translate = translate_wsr,
-        .par = (const uint32_t[]){WINDOW_START},
+        .translate = translate_wsr_windowstart,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            WINDOW_START,
+            XTENSA_OPTION_WINDOWED_REGISTER,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "wur.expstate",
         .translate = translate_wur,
         .par = (const uint32_t[]){EXPSTATE},
     }, {
         .name = "wur.fcr",
     }, {
         .name = "wur.expstate",
         .translate = translate_wur,
         .par = (const uint32_t[]){EXPSTATE},
     }, {
         .name = "wur.fcr",

-        .translate = translate_wur,
+        .translate = translate_wur_fcr,

         .par = (const uint32_t[]){FCR},
         .par = (const uint32_t[]){FCR},

+        .coprocessor = 0x1,

     }, {
         .name = "wur.fsr",
     }, {
         .name = "wur.fsr",

-        .translate = translate_wur,
+        .translate = translate_wur_fsr,

         .par = (const uint32_t[]){FSR},
         .par = (const uint32_t[]){FSR},

+        .coprocessor = 0x1,

     }, {
         .name = "wur.threadptr",
         .translate = translate_wur,
     }, {
         .name = "wur.threadptr",
         .translate = translate_wur,


@@ -4247,308 +5294,690 @@ static const XtensaOpcodeOps core_ops[] = {
         .par = (const uint32_t[]){BOOLEAN_XOR},
     }, {
         .name = "xsr.176",
         .par = (const uint32_t[]){BOOLEAN_XOR},
     }, {
         .name = "xsr.176",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){176},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.208",
     }, {
         .name = "xsr.208",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){208},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.acchi",
     }, {
         .name = "xsr.acchi",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){ACCHI},
+        .translate = translate_xsr_acchi,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ACCHI,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "xsr.acclo",
         .translate = translate_xsr,
     }, {
         .name = "xsr.acclo",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){ACCLO},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ACCLO,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "xsr.atomctl",
     }, {
         .name = "xsr.atomctl",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){ATOMCTL},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ATOMCTL,
+            XTENSA_OPTION_ATOMCTL,
+            0x3f,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.br",
     }, {
         .name = "xsr.br",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){BR},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            BR,
+            XTENSA_OPTION_BOOLEAN,
+            0xffff,
+        },

     }, {
         .name = "xsr.cacheattr",
         .translate = translate_xsr,
     }, {
         .name = "xsr.cacheattr",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){CACHEATTR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CACHEATTR,
+            XTENSA_OPTION_CACHEATTR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.ccompare0",
     }, {
         .name = "xsr.ccompare0",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){CCOMPARE},
+        .translate = translate_xsr_ccompare,
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "xsr.ccompare1",
     }, {
         .name = "xsr.ccompare1",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){CCOMPARE + 1},
+        .translate = translate_xsr_ccompare,
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE + 1,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "xsr.ccompare2",
     }, {
         .name = "xsr.ccompare2",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){CCOMPARE + 2},
+        .translate = translate_xsr_ccompare,
+        .test_ill = test_ill_ccompare,
+        .par = (const uint32_t[]){
+            CCOMPARE + 2,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "xsr.ccount",
     }, {
         .name = "xsr.ccount",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){CCOUNT},
+        .translate = translate_xsr_ccount,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CCOUNT,
+            XTENSA_OPTION_TIMER_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "xsr.configid0",
     }, {
         .name = "xsr.configid0",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){CONFIGID0},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.configid1",
     }, {
         .name = "xsr.configid1",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){CONFIGID1},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.cpenable",
     }, {
         .name = "xsr.cpenable",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){CPENABLE},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            CPENABLE,
+            XTENSA_OPTION_COPROCESSOR,
+            0xff,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "xsr.dbreaka0",
     }, {
         .name = "xsr.dbreaka0",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){DBREAKA},
+        .translate = translate_xsr_dbreaka,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKA,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.dbreaka1",
     }, {
         .name = "xsr.dbreaka1",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){DBREAKA + 1},
+        .translate = translate_xsr_dbreaka,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKA + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.dbreakc0",
     }, {
         .name = "xsr.dbreakc0",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){DBREAKC},
+        .translate = translate_xsr_dbreakc,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKC,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.dbreakc1",
     }, {
         .name = "xsr.dbreakc1",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){DBREAKC + 1},
+        .translate = translate_xsr_dbreakc,
+        .test_ill = test_ill_dbreak,
+        .par = (const uint32_t[]){
+            DBREAKC + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.ddr",
         .translate = translate_xsr,
     }, {
         .name = "xsr.ddr",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){DDR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DDR,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.debugcause",
     }, {
         .name = "xsr.debugcause",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){DEBUGCAUSE},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.depc",
         .translate = translate_xsr,
     }, {
         .name = "xsr.depc",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){DEPC},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DEPC,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.dtlbcfg",
     }, {
         .name = "xsr.dtlbcfg",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){DTLBCFG},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            DTLBCFG,
+            XTENSA_OPTION_MMU,
+            0x01130000,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.epc1",
         .translate = translate_xsr,
     }, {
         .name = "xsr.epc1",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPC1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EPC1,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.epc2",
         .translate = translate_xsr,
     }, {
         .name = "xsr.epc2",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPC1 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.epc3",
         .translate = translate_xsr,
     }, {
         .name = "xsr.epc3",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPC1 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.epc4",
         .translate = translate_xsr,
     }, {
         .name = "xsr.epc4",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPC1 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.epc5",
         .translate = translate_xsr,
     }, {
         .name = "xsr.epc5",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPC1 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.epc6",
         .translate = translate_xsr,
     }, {
         .name = "xsr.epc6",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPC1 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.epc7",
         .translate = translate_xsr,
     }, {
         .name = "xsr.epc7",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPC1 + 6},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPC1 + 6,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.eps2",
         .translate = translate_xsr,
     }, {
         .name = "xsr.eps2",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPS2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.eps3",
         .translate = translate_xsr,
     }, {
         .name = "xsr.eps3",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPS2 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.eps4",
         .translate = translate_xsr,
     }, {
         .name = "xsr.eps4",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPS2 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.eps5",
         .translate = translate_xsr,
     }, {
         .name = "xsr.eps5",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPS2 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.eps6",
         .translate = translate_xsr,
     }, {
         .name = "xsr.eps6",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPS2 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.eps7",
         .translate = translate_xsr,
     }, {
         .name = "xsr.eps7",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EPS2 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EPS2 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.exccause",
         .translate = translate_xsr,
     }, {
         .name = "xsr.exccause",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCCAUSE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCCAUSE,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excsave1",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excsave1",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCSAVE1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCSAVE1,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excsave2",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excsave2",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 1},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 1,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excsave3",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excsave3",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 2},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 2,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excsave4",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excsave4",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 3},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 3,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excsave5",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excsave5",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 4},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 4,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excsave6",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excsave6",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 5},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 5,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excsave7",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excsave7",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCSAVE1 + 6},
+        .test_ill = test_ill_hpi,
+        .par = (const uint32_t[]){
+            EXCSAVE1 + 6,
+            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.excvaddr",
         .translate = translate_xsr,
     }, {
         .name = "xsr.excvaddr",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){EXCVADDR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            EXCVADDR,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.ibreaka0",
     }, {
         .name = "xsr.ibreaka0",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){IBREAKA},
+        .translate = translate_xsr_ibreaka,
+        .test_ill = test_ill_ibreak,
+        .par = (const uint32_t[]){
+            IBREAKA,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "xsr.ibreaka1",
     }, {
         .name = "xsr.ibreaka1",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){IBREAKA + 1},
+        .translate = translate_xsr_ibreaka,
+        .test_ill = test_ill_ibreak,
+        .par = (const uint32_t[]){
+            IBREAKA + 1,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "xsr.ibreakenable",
     }, {
         .name = "xsr.ibreakenable",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){IBREAKENABLE},
+        .translate = translate_xsr_ibreakenable,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            IBREAKENABLE,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,

     }, {
         .name = "xsr.icount",
     }, {
         .name = "xsr.icount",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){ICOUNT},
+        .translate = translate_xsr_icount,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ICOUNT,
+            XTENSA_OPTION_DEBUG,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.icountlevel",
     }, {
         .name = "xsr.icountlevel",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){ICOUNTLEVEL},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ICOUNTLEVEL,
+            XTENSA_OPTION_DEBUG,
+            0xf,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "xsr.intclear",
     }, {
         .name = "xsr.intclear",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){INTCLEAR},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.intenable",
         .translate = translate_xsr,
     }, {
         .name = "xsr.intenable",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){INTENABLE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            INTENABLE,
+            XTENSA_OPTION_INTERRUPT,
+        },
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "xsr.interrupt",
     }, {
         .name = "xsr.interrupt",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){INTSET},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.intset",
     }, {
         .name = "xsr.intset",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){INTSET},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.itlbcfg",
     }, {
         .name = "xsr.itlbcfg",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){ITLBCFG},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            ITLBCFG,
+            XTENSA_OPTION_MMU,
+            0x01130000,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.lbeg",
         .translate = translate_xsr,
     }, {
         .name = "xsr.lbeg",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){LBEG},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LBEG,
+            XTENSA_OPTION_LOOP,
+        },
+        .op_flags = XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "xsr.lcount",
         .translate = translate_xsr,
     }, {
         .name = "xsr.lcount",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){LCOUNT},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LCOUNT,
+            XTENSA_OPTION_LOOP,
+        },

     }, {
         .name = "xsr.lend",
         .translate = translate_xsr,
     }, {
         .name = "xsr.lend",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){LEND},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LEND,
+            XTENSA_OPTION_LOOP,
+        },
+        .op_flags = XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "xsr.litbase",
     }, {
         .name = "xsr.litbase",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){LITBASE},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            LITBASE,
+            XTENSA_OPTION_EXTENDED_L32R,
+            0xfffff001,
+        },
+        .op_flags = XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "xsr.m0",
         .translate = translate_xsr,
     }, {
         .name = "xsr.m0",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MR},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "xsr.m1",
         .translate = translate_xsr,
     }, {
         .name = "xsr.m1",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MR + 1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 1,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "xsr.m2",
         .translate = translate_xsr,
     }, {
         .name = "xsr.m2",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MR + 2},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 2,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "xsr.m3",
         .translate = translate_xsr,
     }, {
         .name = "xsr.m3",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MR + 3},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MR + 3,
+            XTENSA_OPTION_MAC16,
+        },

     }, {
         .name = "xsr.memctl",
     }, {
         .name = "xsr.memctl",

-        .translate = translate_xsr,
+        .translate = translate_xsr_memctl,

         .par = (const uint32_t[]){MEMCTL},
         .par = (const uint32_t[]){MEMCTL},

+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.mecr",
+        .translate = translate_xsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MECR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.mepc",
+        .translate = translate_xsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MEPC,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.meps",
+        .translate = translate_xsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MEPS,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.mesave",
+        .translate = translate_xsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESAVE,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.mesr",
+        .translate = translate_xsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.mevaddr",
+        .translate = translate_xsr,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MESR,
+            XTENSA_OPTION_MEMORY_ECC_PARITY,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.misc0",
         .translate = translate_xsr,
     }, {
         .name = "xsr.misc0",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MISC},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.misc1",
         .translate = translate_xsr,
     }, {
         .name = "xsr.misc1",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MISC + 1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 1,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.misc2",
         .translate = translate_xsr,
     }, {
         .name = "xsr.misc2",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MISC + 2},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 2,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.misc3",
         .translate = translate_xsr,
     }, {
         .name = "xsr.misc3",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){MISC + 3},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            MISC + 3,
+            XTENSA_OPTION_MISC_SR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.prefctl",
+        .translate = translate_xsr,
+        .par = (const uint32_t[]){PREFCTL},

     }, {
         .name = "xsr.prid",
     }, {
         .name = "xsr.prid",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){PRID},
+        .op_flags = XTENSA_OP_ILL,

     }, {
         .name = "xsr.ps",
     }, {
         .name = "xsr.ps",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){PS},
+        .translate = translate_xsr_ps,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            PS,
+            XTENSA_OPTION_EXCEPTION,
+        },
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_CHECK_INTERRUPTS,

     }, {
         .name = "xsr.ptevaddr",
     }, {
         .name = "xsr.ptevaddr",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){PTEVADDR},
+        .translate = translate_xsr_mask,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            PTEVADDR,
+            XTENSA_OPTION_MMU,
+            0xffc00000,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.rasid",
     }, {
         .name = "xsr.rasid",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){RASID},
+        .translate = translate_xsr_rasid,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            RASID,
+            XTENSA_OPTION_MMU,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     }, {
         .name = "xsr.sar",
     }, {
         .name = "xsr.sar",

-        .translate = translate_xsr,
+        .translate = translate_xsr_sar,

         .par = (const uint32_t[]){SAR},
     }, {
         .name = "xsr.scompare1",
         .translate = translate_xsr,
         .par = (const uint32_t[]){SAR},
     }, {
         .name = "xsr.scompare1",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){SCOMPARE1},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            SCOMPARE1,
+            XTENSA_OPTION_CONDITIONAL_STORE,
+        },

     }, {
         .name = "xsr.vecbase",
         .translate = translate_xsr,
     }, {
         .name = "xsr.vecbase",
         .translate = translate_xsr,

-        .par = (const uint32_t[]){VECBASE},
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            VECBASE,
+            XTENSA_OPTION_RELOCATABLE_VECTOR,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED,

     }, {
         .name = "xsr.windowbase",
     }, {
         .name = "xsr.windowbase",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){WINDOW_BASE},
+        .translate = translate_xsr_windowbase,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            WINDOW_BASE,
+            XTENSA_OPTION_WINDOWED_REGISTER,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_SYNC_REGISTER_WINDOW,

     }, {
         .name = "xsr.windowstart",
     }, {
         .name = "xsr.windowstart",

-        .translate = translate_xsr,
-        .par = (const uint32_t[]){WINDOW_START},
+        .translate = translate_xsr_windowstart,
+        .test_ill = test_ill_sr,
+        .par = (const uint32_t[]){
+            WINDOW_START,
+            XTENSA_OPTION_WINDOWED_REGISTER,
+        },
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,

     },
 };
 
     },
 };
 


@@ -4558,21 +5987,17 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = {
 };
 
 
 };
 
 

-static void translate_abs_s(DisasContext *dc, const uint32_t arg[],
+static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
-    }
+    gen_helper_abs_s(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_add_s(DisasContext *dc, const uint32_t arg[],
+static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_add_s(cpu_FR[arg[0]], cpu_env,
-                         cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_add_s(arg[0].out, cpu_env,
+                     arg[1].in, arg[2].in);

 }
 
 enum {
 }
 
 enum {


@@ -4585,7 +6010,7 @@ enum {
     COMPARE_ULE,
 };
 
     COMPARE_ULE,
 };
 

-static void translate_compare_s(DisasContext *dc, const uint32_t arg[],
+static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],

                                 const uint32_t par[])
 {
     static void (* const helper[])(TCGv_env env, TCGv_i32 bit,
                                 const uint32_t par[])
 {
     static void (* const helper[])(TCGv_env env, TCGv_i32 bit,


@@ -4598,331 +6023,344 @@ static void translate_compare_s(DisasContext *dc, const uint32_t arg[],
         [COMPARE_OLE] = gen_helper_ole_s,
         [COMPARE_ULE] = gen_helper_ule_s,
     };
         [COMPARE_OLE] = gen_helper_ole_s,
         [COMPARE_ULE] = gen_helper_ule_s,
     };

+    TCGv_i32 bit = tcg_const_i32(1 << arg[0].imm);

 
 

-    if (gen_check_cpenable(dc, 0)) {
-        TCGv_i32 bit = tcg_const_i32(1 << arg[0]);
-
-        helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]);
-        tcg_temp_free(bit);
-    }
+    helper[par[0]](cpu_env, bit, arg[1].in, arg[2].in);
+    tcg_temp_free(bit);

 }
 
 }
 

-static void translate_float_s(DisasContext *dc, const uint32_t arg[],
+static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],

                               const uint32_t par[])
 {
                               const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 scale = tcg_const_i32(-arg[2]);
+    TCGv_i32 scale = tcg_const_i32(-arg[2].imm);

 
 

-        if (par[0]) {
-            gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
-        } else {
-            gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
-        }
-        tcg_temp_free(scale);
+    if (par[0]) {
+        gen_helper_uitof(arg[0].out, cpu_env, arg[1].in, scale);
+    } else {
+        gen_helper_itof(arg[0].out, cpu_env, arg[1].in, scale);

     }
     }

+    tcg_temp_free(scale);

 }
 
 }
 

-static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[],
+static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-        TCGv_i32 scale = tcg_const_i32(arg[2]);
+    TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
+    TCGv_i32 scale = tcg_const_i32(arg[2].imm);

 
 

-        if (par[1]) {
-            gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]],
-                             rounding_mode, scale);
-        } else {
-            gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]],
-                            rounding_mode, scale);
-        }
-        tcg_temp_free(rounding_mode);
-        tcg_temp_free(scale);
+    if (par[1]) {
+        gen_helper_ftoui(arg[0].out, arg[1].in,
+                         rounding_mode, scale);
+    } else {
+        gen_helper_ftoi(arg[0].out, arg[1].in,
+                        rounding_mode, scale);

     }
     }

+    tcg_temp_free(rounding_mode);
+    tcg_temp_free(scale);

 }
 
 }
 

-static void translate_ldsti(DisasContext *dc, const uint32_t arg[],
+static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();

 
 

-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        if (par[0]) {
-            tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
-        } else {
-            tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
-        }
-        if (par[1]) {
-            tcg_gen_mov_i32(cpu_R[arg[1]], addr);
-        }
-        tcg_temp_free(addr);
+    tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
+    gen_load_store_alignment(dc, 2, addr, false);
+    if (par[0]) {
+        tcg_gen_qemu_st32(arg[0].in, addr, dc->cring);
+    } else {
+        tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring);

     }
     }

+    if (par[1]) {
+        tcg_gen_mov_i32(arg[1].out, addr);
+    }
+    tcg_temp_free(addr);

 }
 
 }
 

-static void translate_ldstx(DisasContext *dc, const uint32_t arg[],
+static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check2(dc, arg[1], arg[2]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();

 
 

-        tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        if (par[0]) {
-            tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
-        } else {
-            tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
-        }
-        if (par[1]) {
-            tcg_gen_mov_i32(cpu_R[arg[1]], addr);
-        }
-        tcg_temp_free(addr);
+    tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
+    gen_load_store_alignment(dc, 2, addr, false);
+    if (par[0]) {
+        tcg_gen_qemu_st32(arg[0].in, addr, dc->cring);
+    } else {
+        tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring);
+    }
+    if (par[1]) {
+        tcg_gen_mov_i32(arg[1].out, addr);

     }
     }

+    tcg_temp_free(addr);

 }
 
 }
 

-static void translate_madd_s(DisasContext *dc, const uint32_t arg[],
+static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_madd_s(cpu_FR[arg[0]], cpu_env,
-                          cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_madd_s(arg[0].out, cpu_env,
+                      arg[0].in, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_mov_s(DisasContext *dc, const uint32_t arg[],
+static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]);
-    }
+    tcg_gen_mov_i32(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_movcond_s(DisasContext *dc, const uint32_t arg[],
+static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],

                                 const uint32_t par[])
 {
                                 const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[2]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 zero = tcg_const_i32(0);

 
 

-        tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]],
-                            cpu_R[arg[2]], zero,
-                            cpu_FR[arg[1]], cpu_FR[arg[0]]);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_movcond_i32(par[0], arg[0].out,
+                        arg[2].in, zero,
+                        arg[1].in, arg[0].in);
+    tcg_temp_free(zero);

 }
 
 }
 

-static void translate_movp_s(DisasContext *dc, const uint32_t arg[],
+static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        TCGv_i32 zero = tcg_const_i32(0);
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 tmp = tcg_temp_new_i32();

 
 

-        tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
-        tcg_gen_movcond_i32(par[0],
-                            cpu_FR[arg[0]], tmp, zero,
-                            cpu_FR[arg[1]], cpu_FR[arg[0]]);
-        tcg_temp_free(tmp);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
+    tcg_gen_movcond_i32(par[0],
+                        arg[0].out, tmp, zero,
+                        arg[1].in, arg[0].in);
+    tcg_temp_free(tmp);
+    tcg_temp_free(zero);

 }
 
 }
 

-static void translate_mul_s(DisasContext *dc, const uint32_t arg[],
+static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_mul_s(cpu_FR[arg[0]], cpu_env,
-                         cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_mul_s(arg[0].out, cpu_env,
+                     arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_msub_s(DisasContext *dc, const uint32_t arg[],
+static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[],

                              const uint32_t par[])
 {
                              const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_msub_s(cpu_FR[arg[0]], cpu_env,
-                          cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_msub_s(arg[0].out, cpu_env,
+                      arg[0].in, arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_neg_s(DisasContext *dc, const uint32_t arg[],
+static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
-    }
+    gen_helper_neg_s(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_rfr_s(DisasContext *dc, const uint32_t arg[],
+static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[0]) &&
-        gen_check_cpenable(dc, 0)) {
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]);
-    }
+    tcg_gen_mov_i32(arg[0].out, arg[1].in);

 }
 
 }
 

-static void translate_sub_s(DisasContext *dc, const uint32_t arg[],
+static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_sub_s(cpu_FR[arg[0]], cpu_env,
-                         cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_sub_s(arg[0].out, cpu_env,
+                     arg[1].in, arg[2].in);

 }
 
 }
 

-static void translate_wfr_s(DisasContext *dc, const uint32_t arg[],
+static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],

                             const uint32_t par[])
 {
                             const uint32_t par[])
 {

-    if (gen_window_check1(dc, arg[1]) &&
-        gen_check_cpenable(dc, 0)) {
-        tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_mov_i32(arg[0].out, arg[1].in);

 }
 
 static const XtensaOpcodeOps fpu2000_ops[] = {
     {
         .name = "abs.s",
         .translate = translate_abs_s,
 }
 
 static const XtensaOpcodeOps fpu2000_ops[] = {
     {
         .name = "abs.s",
         .translate = translate_abs_s,

+        .coprocessor = 0x1,

     }, {
         .name = "add.s",
         .translate = translate_add_s,
     }, {
         .name = "add.s",
         .translate = translate_add_s,

+        .coprocessor = 0x1,

     }, {
         .name = "ceil.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_up, false},
     }, {
         .name = "ceil.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_up, false},

+        .coprocessor = 0x1,

     }, {
         .name = "float.s",
         .translate = translate_float_s,
         .par = (const uint32_t[]){false},
     }, {
         .name = "float.s",
         .translate = translate_float_s,
         .par = (const uint32_t[]){false},

+        .coprocessor = 0x1,

     }, {
         .name = "floor.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_down, false},
     }, {
         .name = "floor.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_down, false},

+        .coprocessor = 0x1,

     }, {
         .name = "lsi",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){false, false},
     }, {
         .name = "lsi",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){false, false},

+        .op_flags = XTENSA_OP_LOAD,
+        .coprocessor = 0x1,

     }, {
         .name = "lsiu",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){false, true},
     }, {
         .name = "lsiu",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){false, true},

+        .op_flags = XTENSA_OP_LOAD,
+        .coprocessor = 0x1,

     }, {
         .name = "lsx",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){false, false},
     }, {
         .name = "lsx",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){false, false},

+        .op_flags = XTENSA_OP_LOAD,
+        .coprocessor = 0x1,

     }, {
         .name = "lsxu",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){false, true},
     }, {
         .name = "lsxu",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){false, true},

+        .op_flags = XTENSA_OP_LOAD,
+        .coprocessor = 0x1,

     }, {
         .name = "madd.s",
         .translate = translate_madd_s,
     }, {
         .name = "madd.s",
         .translate = translate_madd_s,

+        .coprocessor = 0x1,

     }, {
         .name = "mov.s",
         .translate = translate_mov_s,
     }, {
         .name = "mov.s",
         .translate = translate_mov_s,

+        .coprocessor = 0x1,

     }, {
         .name = "moveqz.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_EQ},
     }, {
         .name = "moveqz.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .coprocessor = 0x1,

     }, {
         .name = "movf.s",
         .translate = translate_movp_s,
         .par = (const uint32_t[]){TCG_COND_EQ},
     }, {
         .name = "movf.s",
         .translate = translate_movp_s,
         .par = (const uint32_t[]){TCG_COND_EQ},

+        .coprocessor = 0x1,

     }, {
         .name = "movgez.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_GE},
     }, {
         .name = "movgez.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_GE},

+        .coprocessor = 0x1,

     }, {
         .name = "movltz.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_LT},
     }, {
         .name = "movltz.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_LT},

+        .coprocessor = 0x1,

     }, {
         .name = "movnez.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_NE},
     }, {
         .name = "movnez.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .coprocessor = 0x1,

     }, {
         .name = "movt.s",
         .translate = translate_movp_s,
         .par = (const uint32_t[]){TCG_COND_NE},
     }, {
         .name = "movt.s",
         .translate = translate_movp_s,
         .par = (const uint32_t[]){TCG_COND_NE},

+        .coprocessor = 0x1,

     }, {
         .name = "msub.s",
         .translate = translate_msub_s,
     }, {
         .name = "msub.s",
         .translate = translate_msub_s,

+        .coprocessor = 0x1,

     }, {
         .name = "mul.s",
         .translate = translate_mul_s,
     }, {
         .name = "mul.s",
         .translate = translate_mul_s,

+        .coprocessor = 0x1,

     }, {
         .name = "neg.s",
         .translate = translate_neg_s,
     }, {
         .name = "neg.s",
         .translate = translate_neg_s,

+        .coprocessor = 0x1,

     }, {
         .name = "oeq.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OEQ},
     }, {
         .name = "oeq.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OEQ},

+        .coprocessor = 0x1,

     }, {
         .name = "ole.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OLE},
     }, {
         .name = "ole.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OLE},

+        .coprocessor = 0x1,

     }, {
         .name = "olt.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OLT},
     }, {
         .name = "olt.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OLT},

+        .coprocessor = 0x1,

     }, {
         .name = "rfr",
         .translate = translate_rfr_s,
     }, {
         .name = "rfr",
         .translate = translate_rfr_s,

+        .coprocessor = 0x1,

     }, {
         .name = "round.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_nearest_even, false},
     }, {
         .name = "round.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_nearest_even, false},

+        .coprocessor = 0x1,

     }, {
         .name = "ssi",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){true, false},
     }, {
         .name = "ssi",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){true, false},

+        .op_flags = XTENSA_OP_STORE,
+        .coprocessor = 0x1,

     }, {
         .name = "ssiu",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){true, true},
     }, {
         .name = "ssiu",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){true, true},

+        .op_flags = XTENSA_OP_STORE,
+        .coprocessor = 0x1,

     }, {
         .name = "ssx",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){true, false},
     }, {
         .name = "ssx",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){true, false},

+        .op_flags = XTENSA_OP_STORE,
+        .coprocessor = 0x1,

     }, {
         .name = "ssxu",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){true, true},
     }, {
         .name = "ssxu",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){true, true},

+        .op_flags = XTENSA_OP_STORE,
+        .coprocessor = 0x1,

     }, {
         .name = "sub.s",
         .translate = translate_sub_s,
     }, {
         .name = "sub.s",
         .translate = translate_sub_s,

+        .coprocessor = 0x1,

     }, {
         .name = "trunc.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_to_zero, false},
     }, {
         .name = "trunc.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_to_zero, false},

+        .coprocessor = 0x1,

     }, {
         .name = "ueq.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_UEQ},
     }, {
         .name = "ueq.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_UEQ},

+        .coprocessor = 0x1,

     }, {
         .name = "ufloat.s",
         .translate = translate_float_s,
         .par = (const uint32_t[]){true},
     }, {
         .name = "ufloat.s",
         .translate = translate_float_s,
         .par = (const uint32_t[]){true},

+        .coprocessor = 0x1,

     }, {
         .name = "ule.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_ULE},
     }, {
         .name = "ule.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_ULE},

+        .coprocessor = 0x1,

     }, {
         .name = "ult.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_ULT},
     }, {
         .name = "ult.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_ULT},

+        .coprocessor = 0x1,

     }, {
         .name = "un.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_UN},
     }, {
         .name = "un.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_UN},

+        .coprocessor = 0x1,

     }, {
         .name = "utrunc.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_to_zero, true},
     }, {
         .name = "utrunc.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_to_zero, true},

+        .coprocessor = 0x1,

     }, {
         .name = "wfr",
         .translate = translate_wfr_s,
     }, {
         .name = "wfr",
         .translate = translate_wfr_s,

+        .coprocessor = 0x1,

     },
 };
 
     },
 };