* Copyright (c) 2006 Openedhand Ltd.
* Copyright (c) 2006 Thorsten Zitterell
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
#include "hw.h"
-#include "qemu-timer.h"
-#include "sysemu.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
#include "pxa.h"
#include "sysbus.h"
typedef struct {
uint32_t value;
- int level;
+ qemu_irq irq;
QEMUTimer *qtimer;
int num;
PXA2xxTimerInfo *info;
struct PXA2xxTimerInfo {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t flags;
int32_t clock;
uint64_t lastload;
uint32_t freq;
PXA2xxTimer0 timer[4];
- qemu_irq irqs[5];
uint32_t events;
uint32_t irq_enabled;
uint32_t reset3;
uint32_t snapshot;
- PXA2xxTimer4 tm4[8];
qemu_irq irq4;
+ PXA2xxTimer4 tm4[8];
};
#define PXA2XX_TIMER_HAVE_TM4 0
qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}
-static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
+static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
+ unsigned size)
{
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
int tm = 0;
switch (offset) {
case OSMR3: tm ++;
+ /* fall through */
case OSMR2: tm ++;
+ /* fall through */
case OSMR1: tm ++;
+ /* fall through */
case OSMR0:
return s->timer[tm].value;
case OSMR11: tm ++;
+ /* fall through */
case OSMR10: tm ++;
+ /* fall through */
case OSMR9: tm ++;
+ /* fall through */
case OSMR8: tm ++;
+ /* fall through */
case OSMR7: tm ++;
+ /* fall through */
case OSMR6: tm ++;
+ /* fall through */
case OSMR5: tm ++;
+ /* fall through */
case OSMR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
return s->tm4[tm].tm.value;
case OSCR:
- return s->clock + muldiv64(qemu_get_clock(vm_clock) -
+ return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
s->lastload, s->freq, get_ticks_per_sec());
case OSCR11: tm ++;
+ /* fall through */
case OSCR10: tm ++;
+ /* fall through */
case OSCR9: tm ++;
+ /* fall through */
case OSCR8: tm ++;
+ /* fall through */
case OSCR7: tm ++;
+ /* fall through */
case OSCR6: tm ++;
+ /* fall through */
case OSCR5: tm ++;
+ /* fall through */
case OSCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
if (s->tm4[tm - 1].freq)
s->snapshot = s->tm4[tm - 1].clock + muldiv64(
- qemu_get_clock(vm_clock) -
+ qemu_get_clock_ns(vm_clock) -
s->tm4[tm - 1].lastload,
s->tm4[tm - 1].freq, get_ticks_per_sec());
else
if (!s->tm4[tm].freq)
return s->tm4[tm].clock;
- return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
+ return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
case OIER:
return s->irq_enabled;
case OWER:
return s->reset3;
case OMCR11: tm ++;
+ /* fall through */
case OMCR10: tm ++;
+ /* fall through */
case OMCR9: tm ++;
+ /* fall through */
case OMCR8: tm ++;
+ /* fall through */
case OMCR7: tm ++;
+ /* fall through */
case OMCR6: tm ++;
+ /* fall through */
case OMCR5: tm ++;
+ /* fall through */
case OMCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
return 0;
}
-static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+static void pxa2xx_timer_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
{
int i, tm = 0;
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
switch (offset) {
case OSMR3: tm ++;
+ /* fall through */
case OSMR2: tm ++;
+ /* fall through */
case OSMR1: tm ++;
+ /* fall through */
case OSMR0:
s->timer[tm].value = value;
- pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
+ pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
break;
case OSMR11: tm ++;
+ /* fall through */
case OSMR10: tm ++;
+ /* fall through */
case OSMR9: tm ++;
+ /* fall through */
case OSMR8: tm ++;
+ /* fall through */
case OSMR7: tm ++;
+ /* fall through */
case OSMR6: tm ++;
+ /* fall through */
case OSMR5: tm ++;
+ /* fall through */
case OSMR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].tm.value = value;
- pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
+ pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
break;
case OSCR:
s->oldclock = s->clock;
- s->lastload = qemu_get_clock(vm_clock);
+ s->lastload = qemu_get_clock_ns(vm_clock);
s->clock = value;
pxa2xx_timer_update(s, s->lastload);
break;
case OSCR11: tm ++;
+ /* fall through */
case OSCR10: tm ++;
+ /* fall through */
case OSCR9: tm ++;
+ /* fall through */
case OSCR8: tm ++;
+ /* fall through */
case OSCR7: tm ++;
+ /* fall through */
case OSCR6: tm ++;
+ /* fall through */
case OSCR5: tm ++;
+ /* fall through */
case OSCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].oldclock = s->tm4[tm].clock;
- s->tm4[tm].lastload = qemu_get_clock(vm_clock);
+ s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
s->tm4[tm].clock = value;
pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
break;
s->irq_enabled = value & 0xfff;
break;
case OSSR: /* Status register */
+ value &= s->events;
s->events &= ~value;
- for (i = 0; i < 4; i ++, value >>= 1) {
- if (s->timer[i].level && (value & 1)) {
- s->timer[i].level = 0;
- qemu_irq_lower(s->irqs[i]);
- }
- }
- if (pxa2xx_timer_has_tm4(s)) {
- for (i = 0; i < 8; i ++, value >>= 1)
- if (s->tm4[i].tm.level && (value & 1))
- s->tm4[i].tm.level = 0;
- if (!(s->events & 0xff0))
- qemu_irq_lower(s->irq4);
- }
+ for (i = 0; i < 4; i ++, value >>= 1)
+ if (value & 1)
+ qemu_irq_lower(s->timer[i].irq);
+ if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
+ qemu_irq_lower(s->irq4);
break;
case OWER: /* XXX: Reset on OSMR3 match? */
s->reset3 = value;
break;
case OMCR7: tm ++;
+ /* fall through */
case OMCR6: tm ++;
+ /* fall through */
case OMCR5: tm ++;
+ /* fall through */
case OMCR4:
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
else {
s->tm4[tm].freq = 0;
- pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
+ pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
}
break;
case OMCR11: tm ++;
+ /* fall through */
case OMCR10: tm ++;
+ /* fall through */
case OMCR9: tm ++;
+ /* fall through */
case OMCR8: tm += 4;
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
else {
s->tm4[tm].freq = 0;
- pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
+ pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
}
break;
default:
}
}
-static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
- pxa2xx_timer_read,
- pxa2xx_timer_read,
- pxa2xx_timer_read,
-};
-
-static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
- pxa2xx_timer_write,
- pxa2xx_timer_write,
- pxa2xx_timer_write,
+static const MemoryRegionOps pxa2xx_timer_ops = {
+ .read = pxa2xx_timer_read,
+ .write = pxa2xx_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void pxa2xx_timer_tick(void *opaque)
PXA2xxTimerInfo *i = t->info;
if (i->irq_enabled & (1 << t->num)) {
- t->level = 1;
i->events |= 1 << t->num;
- qemu_irq_raise(t->num < 4 ? i->irqs[t->num] : i->irq4);
+ qemu_irq_raise(t->irq);
}
if (t->num == 3)
if (t->control & (1 << 3))
t->clock = 0;
if (t->control & (1 << 6))
- pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
+ pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
+ if (i->events & 0xff0)
+ qemu_irq_raise(i->irq4);
}
static int pxa25x_timer_post_load(void *opaque, int version_id)
int64_t now;
int i;
- now = qemu_get_clock(vm_clock);
+ now = qemu_get_clock_ns(vm_clock);
pxa2xx_timer_update(s, now);
if (pxa2xx_timer_has_tm4(s))
static int pxa2xx_timer_init(SysBusDevice *dev)
{
int i;
- int iomemtype;
PXA2xxTimerInfo *s;
s = FROM_SYSBUS(PXA2xxTimerInfo, dev);
s->irq_enabled = 0;
s->oldclock = 0;
s->clock = 0;
- s->lastload = qemu_get_clock(vm_clock);
+ s->lastload = qemu_get_clock_ns(vm_clock);
s->reset3 = 0;
for (i = 0; i < 4; i ++) {
s->timer[i].value = 0;
- sysbus_init_irq(dev, &s->irqs[i]);
+ sysbus_init_irq(dev, &s->timer[i].irq);
s->timer[i].info = s;
s->timer[i].num = i;
- s->timer[i].level = 0;
- s->timer[i].qtimer = qemu_new_timer(vm_clock,
+ s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
pxa2xx_timer_tick, &s->timer[i]);
}
if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
s->tm4[i].tm.value = 0;
s->tm4[i].tm.info = s;
s->tm4[i].tm.num = i + 4;
- s->tm4[i].tm.level = 0;
s->tm4[i].freq = 0;
s->tm4[i].control = 0x0;
- s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
+ s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
pxa2xx_timer_tick4, &s->tm4[i]);
}
}
- iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
- pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x00001000, iomemtype);
+ memory_region_init_io(&s->iomem, &pxa2xx_timer_ops, s,
+ "pxa2xx-timer", 0x00001000);
+ sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
.name = "pxa2xx_timer0",
- .version_id = 1,
- .minimum_version_id = 1,
- .minimum_version_id_old = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .minimum_version_id_old = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(value, PXA2xxTimer0),
- VMSTATE_INT32(level, PXA2xxTimer0),
VMSTATE_END_OF_LIST(),
},
};
}
};
-static SysBusDeviceInfo pxa25x_timer_dev_info = {
- .init = pxa2xx_timer_init,
- .qdev.name = "pxa25x-timer",
- .qdev.desc = "PXA25x timer",
- .qdev.size = sizeof(PXA2xxTimerInfo),
- .qdev.vmsd = &vmstate_pxa2xx_timer_regs,
- .qdev.props = (Property[]) {
- DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
- DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
- PXA2XX_TIMER_HAVE_TM4, false),
- DEFINE_PROP_END_OF_LIST(),
- },
+static Property pxa25x_timer_dev_properties[] = {
+ DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
+ DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
+ PXA2XX_TIMER_HAVE_TM4, false),
+ DEFINE_PROP_END_OF_LIST(),
};
-static SysBusDeviceInfo pxa27x_timer_dev_info = {
- .init = pxa2xx_timer_init,
- .qdev.name = "pxa27x-timer",
- .qdev.desc = "PXA27x timer",
- .qdev.size = sizeof(PXA2xxTimerInfo),
- .qdev.vmsd = &vmstate_pxa2xx_timer_regs,
- .qdev.props = (Property[]) {
- DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
- DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
- PXA2XX_TIMER_HAVE_TM4, true),
- DEFINE_PROP_END_OF_LIST(),
- },
+static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = pxa2xx_timer_init;
+ dc->desc = "PXA25x timer";
+ dc->vmsd = &vmstate_pxa2xx_timer_regs;
+ dc->props = pxa25x_timer_dev_properties;
+}
+
+static const TypeInfo pxa25x_timer_dev_info = {
+ .name = "pxa25x-timer",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PXA2xxTimerInfo),
+ .class_init = pxa25x_timer_dev_class_init,
};
-static void pxa2xx_timer_register(void)
+static Property pxa27x_timer_dev_properties[] = {
+ DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
+ DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
+ PXA2XX_TIMER_HAVE_TM4, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
{
- sysbus_register_withprop(&pxa25x_timer_dev_info);
- sysbus_register_withprop(&pxa27x_timer_dev_info);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = pxa2xx_timer_init;
+ dc->desc = "PXA27x timer";
+ dc->vmsd = &vmstate_pxa2xx_timer_regs;
+ dc->props = pxa27x_timer_dev_properties;
+}
+
+static const TypeInfo pxa27x_timer_dev_info = {
+ .name = "pxa27x-timer",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PXA2xxTimerInfo),
+ .class_init = pxa27x_timer_dev_class_init,
};
-device_init(pxa2xx_timer_register);
+
+static void pxa2xx_timer_register_types(void)
+{
+ type_register_static(&pxa25x_timer_dev_info);
+ type_register_static(&pxa27x_timer_dev_info);
+}
+
+type_init(pxa2xx_timer_register_types)
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