LSI SCSI qdev conversion

[qemu.git] / hw / cs4231.c

diff --git a/hw/cs4231.c b/hw/cs4231.c
index 8ba8253945718f691ea80ea21f6f098e415293ec..22669806de1e32c7c47480ba50cada6da306b670 100644 (file)
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -30,8 +30,7 @@
 /*
  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  */
-#define CS_MAXADDR 0x3f
-#define CS_SIZE (CS_MAXADDR + 1)
+#define CS_SIZE 0x40
 #define CS_REGS 16
 #define CS_DREGS 32
 #define CS_MAXDREG (CS_DREGS - 1)
@@ -47,10 +46,10 @@ typedef struct CSState {
 #define CS_CDC_VER 0x8a
 
 #ifdef DEBUG_CS
-#define DPRINTF(fmt, args...)                           \
-    do { printf("CS: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...)                                       \
+    do { printf("CS: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF(fmt, args...)
+#define DPRINTF(fmt, ...)
 #endif
 
 static void cs_reset(void *opaque)
@@ -68,7 +67,7 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
     CSState *s = opaque;
     uint32_t saddr, ret;
 
-    saddr = (addr & CS_MAXADDR) >> 2;
+    saddr = addr >> 2;
     switch (saddr) {
     case 1:
         switch (CS_RAP(s)) {
@@ -94,7 +93,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
     CSState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr & CS_MAXADDR) >> 2;
+    saddr = addr >> 2;
     DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
     switch (saddr) {
     case 1:
@@ -172,8 +171,6 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
     CSState *s;
 
     s = qemu_mallocz(sizeof(CSState));
-    if (!s)
-        return;
 
     cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
     cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);