* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "pci.h"
*/
/* the helper functio to get a PCIDeice* for a given pci address */
-static inline PCIDevice *pci_addr_to_dev(PCIBus *bus, uint32_t addr)
+static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
{
- uint8_t bus_num = (addr >> 16) & 0xff;
- uint8_t devfn = (addr >> 8) & 0xff;
- return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
+ uint8_t bus_num = addr >> 16;
+ uint8_t devfn = addr >> 8;
+
+ return pci_find_device(bus, bus_num, devfn);
+}
+
+void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
+ uint32_t limit, uint32_t val, uint32_t len)
+{
+ assert(len <= 4);
+ pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
}
-static inline uint32_t pci_addr_to_config(uint32_t addr)
+uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
+ uint32_t limit, uint32_t len)
{
- return addr & (PCI_CONFIG_SPACE_SIZE - 1);
+ assert(len <= 4);
+ return pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
}
-void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
+void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
{
- PCIBus *s = opaque;
- PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
- uint32_t config_addr = pci_addr_to_config(addr);
+ PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
+ uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
- if (!pci_dev)
+ if (!pci_dev) {
return;
+ }
- PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRI32x" len=%d\n",
+ PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n",
__func__, pci_dev->name, config_addr, val, len);
- pci_dev->config_write(pci_dev, config_addr, val, len);
+ pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
+ val, len);
}
-uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
+uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
{
- PCIBus *s = opaque;
- PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
- uint32_t config_addr = pci_addr_to_config(addr);
+ PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
+ uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
uint32_t val;
if (!pci_dev) {
- switch(len) {
- case 1:
- val = 0xff;
- break;
- case 2:
- val = 0xffff;
- break;
- default:
- case 4:
- val = 0xffffffff;
- break;
- }
- } else {
- val = pci_dev->config_read(pci_dev, config_addr, len);
- PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
- __func__, pci_dev->name, config_addr, val, len);
+ return ~0x0;
}
+ val = pci_host_config_read_common(pci_dev, config_addr,
+ PCI_CONFIG_SPACE_SIZE, len);
+ PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
+ __func__, pci_dev->name, config_addr, val, len);
+
return val;
}
-static void pci_host_config_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
- __func__, addr, val);
+ PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
+ __func__, addr, len, val);
s->config_reg = val;
}
-static uint32_t pci_host_config_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned len)
{
PCIHostState *s = opaque;
uint32_t val = s->config_reg;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
- __func__, addr, val);
+ PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
+ __func__, addr, len, val);
return val;
}
-static CPUWriteMemoryFunc * const pci_host_config_write[] = {
- &pci_host_config_writel,
- &pci_host_config_writel,
- &pci_host_config_writel,
-};
-
-static CPUReadMemoryFunc * const pci_host_config_read[] = {
- &pci_host_config_readl,
- &pci_host_config_readl,
- &pci_host_config_readl,
-};
-
-int pci_host_config_register_io_memory(PCIHostState *s)
-{
- return cpu_register_io_memory(pci_host_config_read,
- pci_host_config_write, s);
-}
-
-static void pci_host_config_writel_noswap(void *opaque,
- target_phys_addr_t addr,
- uint32_t val)
+static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
-
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
- __func__, addr, val);
- s->config_reg = val;
+ PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n",
+ addr, len, (unsigned)val);
+ if (s->config_reg & (1u << 31))
+ pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_config_readl_noswap(void *opaque,
- target_phys_addr_t addr)
+static uint64_t pci_host_data_read(void *opaque,
+ target_phys_addr_t addr, unsigned len)
{
PCIHostState *s = opaque;
- uint32_t val = s->config_reg;
-
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
- __func__, addr, val);
+ uint32_t val;
+ if (!(s->config_reg & (1 << 31)))
+ return 0xffffffff;
+ val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
+ PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
+ addr, len, val);
return val;
}
-static CPUWriteMemoryFunc * const pci_host_config_write_noswap[] = {
- &pci_host_config_writel_noswap,
- &pci_host_config_writel_noswap,
- &pci_host_config_writel_noswap,
+const MemoryRegionOps pci_host_conf_le_ops = {
+ .read = pci_host_config_read,
+ .write = pci_host_config_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
-static CPUReadMemoryFunc * const pci_host_config_read_noswap[] = {
- &pci_host_config_readl_noswap,
- &pci_host_config_readl_noswap,
- &pci_host_config_readl_noswap,
+const MemoryRegionOps pci_host_conf_be_ops = {
+ .read = pci_host_config_read,
+ .write = pci_host_config_write,
+ .endianness = DEVICE_BIG_ENDIAN,
};
-int pci_host_config_register_io_memory_noswap(PCIHostState *s)
-{
- return cpu_register_io_memory(pci_host_config_read_noswap,
- pci_host_config_write_noswap, s);
-}
-
-static void pci_host_config_writel_ioport(void *opaque,
- uint32_t addr, uint32_t val)
-{
- PCIHostState *s = opaque;
-
- PCI_DPRINTF("%s addr %"PRIx32 " val %"PRIx32"\n", __func__, addr, val);
- s->config_reg = val;
-}
-
-static uint32_t pci_host_config_readl_ioport(void *opaque, uint32_t addr)
-{
- PCIHostState *s = opaque;
- uint32_t val = s->config_reg;
-
- PCI_DPRINTF("%s addr %"PRIx32" val %"PRIx32"\n", __func__, addr, val);
- return val;
-}
-
-void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s)
-{
- register_ioport_write(ioport, 4, 4, pci_host_config_writel_ioport, s);
- register_ioport_read(ioport, 4, 4, pci_host_config_readl_ioport, s);
-}
-
-#define PCI_ADDR_T target_phys_addr_t
-#define PCI_HOST_SUFFIX _mmio
-
-#include "pci_host_template.h"
-
-static CPUWriteMemoryFunc * const pci_host_data_write_mmio[] = {
- pci_host_data_writeb_mmio,
- pci_host_data_writew_mmio,
- pci_host_data_writel_mmio,
+const MemoryRegionOps pci_host_data_le_ops = {
+ .read = pci_host_data_read,
+ .write = pci_host_data_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
-static CPUReadMemoryFunc * const pci_host_data_read_mmio[] = {
- pci_host_data_readb_mmio,
- pci_host_data_readw_mmio,
- pci_host_data_readl_mmio,
+const MemoryRegionOps pci_host_data_be_ops = {
+ .read = pci_host_data_read,
+ .write = pci_host_data_write,
+ .endianness = DEVICE_BIG_ENDIAN,
};
-int pci_host_data_register_io_memory(PCIHostState *s)
-{
- return cpu_register_io_memory(pci_host_data_read_mmio,
- pci_host_data_write_mmio,
- s);
-}
-
-#undef PCI_ADDR_T
-#undef PCI_HOST_SUFFIX
-
-#define PCI_ADDR_T uint32_t
-#define PCI_HOST_SUFFIX _ioport
-#include "pci_host_template.h"
-
-void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
-{
- register_ioport_write(ioport, 4, 1, pci_host_data_writeb_ioport, s);
- register_ioport_write(ioport, 4, 2, pci_host_data_writew_ioport, s);
- register_ioport_write(ioport, 4, 4, pci_host_data_writel_ioport, s);
- register_ioport_read(ioport, 4, 1, pci_host_data_readb_ioport, s);
- register_ioport_read(ioport, 4, 2, pci_host_data_readw_ioport, s);
- register_ioport_read(ioport, 4, 4, pci_host_data_readl_ioport, s);
-}
projects / qemu.git / blobdiff