#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
+#include "exec/helper-proto.h"
+#include "qemu/error-report.h"
+#include "qemu/qemu-print.h"
#include "qemu/host-utils.h"
-#if !defined(CONFIG_USER_ONLY)
-#include "hw/loader.h"
-#endif
static struct XtensaConfigList *xtensa_cores;
-static void xtensa_core_class_init(ObjectClass *oc, void *data)
+static void add_translator_to_hash(GHashTable *translator,
+ const char *name,
+ const XtensaOpcodeOps *opcode)
{
- CPUClass *cc = CPU_CLASS(oc);
- XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
- const XtensaConfig *config = data;
+ if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) {
+ error_report("Multiple definitions of '%s' opcode in a single table",
+ name);
+ }
+}
- xcc->config = config;
+static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t)
+{
+ unsigned i, j;
+ GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal);
- /* Use num_core_regs to see only non-privileged registers in an unmodified
- * gdb. Use num_regs to see all registers. gdb modification is required
- * for that: reset bit 0 in the 'flags' field of the registers definitions
- * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
- */
- cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
+ for (i = 0; i < t->num_opcodes; ++i) {
+ if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) {
+ const char * const *name = t->opcode[i].name;
+
+ for (j = 0; name[j]; ++j) {
+ add_translator_to_hash(translator,
+ (void *)name[j],
+ (void *)(t->opcode + i));
+ }
+ } else {
+ add_translator_to_hash(translator,
+ (void *)t->opcode[i].name,
+ (void *)(t->opcode + i));
+ }
+ }
+ return translator;
+}
+
+static XtensaOpcodeOps *
+xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
+ const char *name)
+{
+ static GHashTable *translators;
+ GHashTable *translator;
+
+ if (translators == NULL) {
+ translators = g_hash_table_new(g_direct_hash, g_direct_equal);
+ }
+ translator = g_hash_table_lookup(translators, t);
+ if (translator == NULL) {
+ translator = hash_opcode_translators(t);
+ g_hash_table_insert(translators, (void *)t, translator);
+ }
+ return g_hash_table_lookup(translator, name);
}
static void init_libisa(XtensaConfig *config)
{
unsigned i, j;
unsigned opcodes;
+ unsigned formats;
+ unsigned regfiles;
config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
opcodes = xtensa_isa_num_opcodes(config->isa);
+ formats = xtensa_isa_num_formats(config->isa);
+ regfiles = xtensa_isa_num_regfiles(config->isa);
config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
+ for (i = 0; i < formats; ++i) {
+ assert(xtensa_format_num_slots(config->isa, i) <= MAX_INSN_SLOTS);
+ }
+
for (i = 0; i < opcodes; ++i) {
const char *opc_name = xtensa_opcode_name(config->isa, i);
XtensaOpcodeOps *ops = NULL;
#endif
config->opcode_ops[i] = ops;
}
+ config->a_regfile = xtensa_regfile_lookup(config->isa, "AR");
+
+ config->regfile = g_new(void **, regfiles);
+ for (i = 0; i < regfiles; ++i) {
+ const char *name = xtensa_regfile_name(config->isa, i);
+
+ config->regfile[i] = xtensa_get_regfile_by_name(name);
+#ifdef DEBUG
+ if (config->regfile[i] == NULL) {
+ fprintf(stderr, "regfile '%s' not found for %s\n",
+ name, config->name);
+ }
+#endif
+ }
+ xtensa_collect_sr_names(config);
}
-void xtensa_finalize_config(XtensaConfig *config)
+static void xtensa_finalize_config(XtensaConfig *config)
{
- unsigned i, n = 0;
-
if (config->isa_internal) {
init_libisa(config);
}
- if (config->gdb_regmap.num_regs) {
- return;
- }
- for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
- n += (config->gdb_regmap.reg[i].type != 6);
+ if (config->gdb_regmap.num_regs == 0 ||
+ config->gdb_regmap.num_core_regs == 0) {
+ unsigned n_regs = 0;
+ unsigned n_core_regs = 0;
+
+ xtensa_count_regs(config, &n_regs, &n_core_regs);
+ if (config->gdb_regmap.num_regs == 0) {
+ config->gdb_regmap.num_regs = n_regs;
+ }
+ if (config->gdb_regmap.num_core_regs == 0) {
+ config->gdb_regmap.num_core_regs = n_core_regs;
+ }
}
- config->gdb_regmap.num_regs = n;
+}
+
+static void xtensa_core_class_init(ObjectClass *oc, void *data)
+{
+ CPUClass *cc = CPU_CLASS(oc);
+ XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
+ XtensaConfig *config = data;
+
+ xtensa_finalize_config(config);
+ xcc->config = config;
+
+ /*
+ * Use num_core_regs to see only non-privileged registers in an unmodified
+ * gdb. Use num_regs to see all registers. gdb modification is required
+ * for that: reset bit 0 in the 'flags' field of the registers definitions
+ * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
+ */
+ cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
}
void xtensa_register_core(XtensaConfigList *node)
}
}
-void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+void xtensa_cpu_list(void)
{
XtensaConfigList *core = xtensa_cores;
- cpu_fprintf(f, "Available CPUs:\n");
+ qemu_printf("Available CPUs:\n");
for (; core; core = core->next) {
- cpu_fprintf(f, " %s\n", core->config->name);
- }
-}
-
-hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
-{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- uint32_t paddr;
- uint32_t page_size;
- unsigned access;
-
- if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
- &paddr, &page_size, &access) == 0) {
- return paddr;
- }
- if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
- &paddr, &page_size, &access) == 0) {
- return paddr;
+ qemu_printf(" %s\n", core->config->name);
}
- return ~0;
}
-static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
-{
- if (xtensa_option_enabled(env->config,
- XTENSA_OPTION_RELOCATABLE_VECTOR)) {
- return vector - env->config->vecbase + env->sregs[VECBASE];
- } else {
- return vector;
- }
-}
-
-/*!
- * Handle penging IRQ.
- * For the high priority interrupt jump to the corresponding interrupt vector.
- * For the level-1 interrupt convert it to either user, kernel or double
- * exception with the 'level-1 interrupt' exception cause.
- */
-static void handle_interrupt(CPUXtensaState *env)
-{
- int level = env->pending_irq_level;
-
- if (level > xtensa_get_cintlevel(env) &&
- level <= env->config->nlevel &&
- (env->config->level_mask[level] &
- env->sregs[INTSET] &
- env->sregs[INTENABLE])) {
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
-
- if (level > 1) {
- env->sregs[EPC1 + level - 1] = env->pc;
- env->sregs[EPS2 + level - 2] = env->sregs[PS];
- env->sregs[PS] =
- (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
- env->pc = relocated_vector(env,
- env->config->interrupt_vector[level]);
- } else {
- env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
-
- if (env->sregs[PS] & PS_EXCM) {
- if (env->config->ndepc) {
- env->sregs[DEPC] = env->pc;
- } else {
- env->sregs[EPC1] = env->pc;
- }
- cs->exception_index = EXC_DOUBLE;
- } else {
- env->sregs[EPC1] = env->pc;
- cs->exception_index =
- (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
- }
- env->sregs[PS] |= PS_EXCM;
- }
- env->exception_taken = 1;
- }
-}
+#ifdef CONFIG_USER_ONLY
-/* Called from cpu_handle_interrupt with BQL held */
-void xtensa_cpu_do_interrupt(CPUState *cs)
+bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
- if (cs->exception_index == EXC_IRQ) {
- qemu_log_mask(CPU_LOG_INT,
- "%s(EXC_IRQ) level = %d, cintlevel = %d, "
- "pc = %08x, a0 = %08x, ps = %08x, "
- "intset = %08x, intenable = %08x, "
- "ccount = %08x\n",
- __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
- env->pc, env->regs[0], env->sregs[PS],
- env->sregs[INTSET], env->sregs[INTENABLE],
- env->sregs[CCOUNT]);
- handle_interrupt(env);
- }
-
- switch (cs->exception_index) {
- case EXC_WINDOW_OVERFLOW4:
- case EXC_WINDOW_UNDERFLOW4:
- case EXC_WINDOW_OVERFLOW8:
- case EXC_WINDOW_UNDERFLOW8:
- case EXC_WINDOW_OVERFLOW12:
- case EXC_WINDOW_UNDERFLOW12:
- case EXC_KERNEL:
- case EXC_USER:
- case EXC_DOUBLE:
- case EXC_DEBUG:
- qemu_log_mask(CPU_LOG_INT, "%s(%d) "
- "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
- __func__, cs->exception_index,
- env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
- if (env->config->exception_vector[cs->exception_index]) {
- env->pc = relocated_vector(env,
- env->config->exception_vector[cs->exception_index]);
- env->exception_taken = 1;
- } else {
- qemu_log_mask(CPU_LOG_INT, "%s(pc = %08x) bad exception_index: %d\n",
- __func__, env->pc, cs->exception_index);
- }
- break;
-
- case EXC_IRQ:
- break;
-
- default:
- qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
- __func__, env->pc, cs->exception_index);
- break;
- }
- check_interrupts(env);
-}
-
-bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- if (interrupt_request & CPU_INTERRUPT_HARD) {
- cs->exception_index = EXC_IRQ;
- xtensa_cpu_do_interrupt(cs);
- return true;
- }
- return false;
-}
-
-static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
- const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
-{
- unsigned wi, ei;
-
- for (wi = 0; wi < tlb->nways; ++wi) {
- for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
- entry[wi][ei].asid = 0;
- entry[wi][ei].variable = true;
- }
- }
-}
-
-static void reset_tlb_mmu_ways56(CPUXtensaState *env,
- const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
-{
- if (!tlb->varway56) {
- static const xtensa_tlb_entry way5[] = {
- {
- .vaddr = 0xd0000000,
- .paddr = 0,
- .asid = 1,
- .attr = 7,
- .variable = false,
- }, {
- .vaddr = 0xd8000000,
- .paddr = 0,
- .asid = 1,
- .attr = 3,
- .variable = false,
- }
- };
- static const xtensa_tlb_entry way6[] = {
- {
- .vaddr = 0xe0000000,
- .paddr = 0xf0000000,
- .asid = 1,
- .attr = 7,
- .variable = false,
- }, {
- .vaddr = 0xf0000000,
- .paddr = 0xf0000000,
- .asid = 1,
- .attr = 3,
- .variable = false,
- }
- };
- memcpy(entry[5], way5, sizeof(way5));
- memcpy(entry[6], way6, sizeof(way6));
- } else {
- uint32_t ei;
- for (ei = 0; ei < 8; ++ei) {
- entry[6][ei].vaddr = ei << 29;
- entry[6][ei].paddr = ei << 29;
- entry[6][ei].asid = 1;
- entry[6][ei].attr = 3;
- }
- }
-}
-
-static void reset_tlb_region_way0(CPUXtensaState *env,
- xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
-{
- unsigned ei;
-
- for (ei = 0; ei < 8; ++ei) {
- entry[0][ei].vaddr = ei << 29;
- entry[0][ei].paddr = ei << 29;
- entry[0][ei].asid = 1;
- entry[0][ei].attr = 2;
- entry[0][ei].variable = true;
- }
-}
-
-void reset_mmu(CPUXtensaState *env)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- env->sregs[RASID] = 0x04030201;
- env->sregs[ITLBCFG] = 0;
- env->sregs[DTLBCFG] = 0;
- env->autorefill_idx = 0;
- reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
- reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
- reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
- reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
- } else {
- reset_tlb_region_way0(env, env->itlb);
- reset_tlb_region_way0(env, env->dtlb);
- }
-}
-
-static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
-{
- unsigned i;
- for (i = 0; i < 4; ++i) {
- if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
- return i;
- }
- }
- return 0xff;
-}
-
-/*!
- * Lookup xtensa TLB for the given virtual address.
- * See ISA, 4.6.2.2
- *
- * \param pwi: [out] way index
- * \param pei: [out] entry index
- * \param pring: [out] access ring
- * \return 0 if ok, exception cause code otherwise
- */
-int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
- uint32_t *pwi, uint32_t *pei, uint8_t *pring)
-{
- const xtensa_tlb *tlb = dtlb ?
- &env->config->dtlb : &env->config->itlb;
- const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
- env->dtlb : env->itlb;
-
- int nhits = 0;
- unsigned wi;
-
- for (wi = 0; wi < tlb->nways; ++wi) {
- uint32_t vpn;
- uint32_t ei;
- split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
- if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
- unsigned ring = get_ring(env, entry[wi][ei].asid);
- if (ring < 4) {
- if (++nhits > 1) {
- return dtlb ?
- LOAD_STORE_TLB_MULTI_HIT_CAUSE :
- INST_TLB_MULTI_HIT_CAUSE;
- }
- *pwi = wi;
- *pei = ei;
- *pring = ring;
- }
- }
- }
- return nhits ? 0 :
- (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
-}
-
-/*!
- * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
- * See ISA, 4.6.5.10
- */
-static unsigned mmu_attr_to_access(uint32_t attr)
-{
- unsigned access = 0;
-
- if (attr < 12) {
- access |= PAGE_READ;
- if (attr & 0x1) {
- access |= PAGE_EXEC;
- }
- if (attr & 0x2) {
- access |= PAGE_WRITE;
- }
-
- switch (attr & 0xc) {
- case 0:
- access |= PAGE_CACHE_BYPASS;
- break;
-
- case 4:
- access |= PAGE_CACHE_WB;
- break;
-
- case 8:
- access |= PAGE_CACHE_WT;
- break;
- }
- } else if (attr == 13) {
- access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
- }
- return access;
-}
-
-/*!
- * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
- * See ISA, 4.6.3.3
- */
-static unsigned region_attr_to_access(uint32_t attr)
-{
- static const unsigned access[16] = {
- [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
- [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
- [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
- [3] = PAGE_EXEC | PAGE_CACHE_WB,
- [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
- [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
- [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
- };
-
- return access[attr & 0xf];
-}
-
-/*!
- * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
- * See ISA, A.2.14 The Cache Attribute Register
- */
-static unsigned cacheattr_attr_to_access(uint32_t attr)
-{
- static const unsigned access[16] = {
- [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
- [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
- [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
- [3] = PAGE_EXEC | PAGE_CACHE_WB,
- [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
- [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
- };
-
- return access[attr & 0xf];
+ qemu_log_mask(CPU_LOG_INT,
+ "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n",
+ __func__, access_type, address, size);
+ env->sregs[EXCVADDR] = address;
+ env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ?
+ STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE);
+ cs->exception_index = EXC_USER;
+ cpu_loop_exit_restore(cs, retaddr);
}
-static bool is_access_granted(unsigned access, int is_write)
-{
- switch (is_write) {
- case 0:
- return access & PAGE_READ;
-
- case 1:
- return access & PAGE_WRITE;
-
- case 2:
- return access & PAGE_EXEC;
-
- default:
- return 0;
- }
-}
-
-static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
+#else
-static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size, unsigned *access,
- bool may_lookup_pt)
+void xtensa_cpu_do_unaligned_access(CPUState *cs,
+ vaddr addr, MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
{
- bool dtlb = is_write != 2;
- uint32_t wi;
- uint32_t ei;
- uint8_t ring;
- uint32_t vpn;
- uint32_t pte;
- const xtensa_tlb_entry *entry = NULL;
- xtensa_tlb_entry tmp_entry;
- int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
-
- if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
- may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
- ring = (pte >> 4) & 0x3;
- wi = 0;
- split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
-
- if (update_tlb) {
- wi = ++env->autorefill_idx & 0x3;
- xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
- env->sregs[EXCVADDR] = vaddr;
- qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
- __func__, vaddr, vpn, pte);
- } else {
- xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
- entry = &tmp_entry;
- }
- ret = 0;
- }
- if (ret != 0) {
- return ret;
- }
-
- if (entry == NULL) {
- entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
- }
-
- if (ring < mmu_idx) {
- return dtlb ?
- LOAD_STORE_PRIVILEGE_CAUSE :
- INST_FETCH_PRIVILEGE_CAUSE;
- }
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
- *access = mmu_attr_to_access(entry->attr) &
- ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
- if (!is_access_granted(*access, is_write)) {
- return dtlb ?
- (is_write ?
- STORE_PROHIBITED_CAUSE :
- LOAD_PROHIBITED_CAUSE) :
- INST_FETCH_PROHIBITED_CAUSE;
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
+ !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
+ cpu_restore_state(CPU(cpu), retaddr, true);
+ HELPER(exception_cause_vaddr)(env,
+ env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
+ addr);
}
-
- *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
- *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
-
- return 0;
}
-static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
+bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
uint32_t paddr;
uint32_t page_size;
unsigned access;
- uint32_t pt_vaddr =
- (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
- int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
- &paddr, &page_size, &access, false);
+ int ret = xtensa_get_physical_addr(env, true, address, access_type,
+ mmu_idx, &paddr, &page_size, &access);
- qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
- __func__, vaddr, ret ? ~0 : paddr);
+ qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx
+ ", %d, %d) -> %08x, ret = %d\n",
+ __func__, address, access_type, mmu_idx, paddr, ret);
if (ret == 0) {
- *pte = ldl_phys(cs->as, paddr);
- }
- return ret;
-}
-
-static int get_physical_addr_region(CPUXtensaState *env,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size, unsigned *access)
-{
- bool dtlb = is_write != 2;
- uint32_t wi = 0;
- uint32_t ei = (vaddr >> 29) & 0x7;
- const xtensa_tlb_entry *entry =
- xtensa_tlb_get_entry(env, dtlb, wi, ei);
-
- *access = region_attr_to_access(entry->attr);
- if (!is_access_granted(*access, is_write)) {
- return dtlb ?
- (is_write ?
- STORE_PROHIBITED_CAUSE :
- LOAD_PROHIBITED_CAUSE) :
- INST_FETCH_PROHIBITED_CAUSE;
- }
-
- *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
- *page_size = ~REGION_PAGE_MASK + 1;
-
- return 0;
-}
-
-/*!
- * Convert virtual address to physical addr.
- * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
- *
- * \return 0 if ok, exception cause code otherwise
- */
-int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
- uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size, unsigned *access)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- return get_physical_addr_mmu(env, update_tlb,
- vaddr, is_write, mmu_idx, paddr, page_size, access, true);
- } else if (xtensa_option_bits_enabled(env->config,
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
- return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
- paddr, page_size, access);
+ tlb_set_page(cs,
+ address & TARGET_PAGE_MASK,
+ paddr & TARGET_PAGE_MASK,
+ access, mmu_idx, page_size);
+ return true;
+ } else if (probe) {
+ return false;
} else {
- *paddr = vaddr;
- *page_size = TARGET_PAGE_SIZE;
- *access = cacheattr_attr_to_access(
- env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
- return 0;
+ cpu_restore_state(cs, retaddr, true);
+ HELPER(exception_cause_vaddr)(env, env->pc, ret, address);
}
}
-static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
- CPUXtensaState *env, bool dtlb)
+void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr)
{
- unsigned wi, ei;
- const xtensa_tlb *conf =
- dtlb ? &env->config->dtlb : &env->config->itlb;
- unsigned (*attr_to_access)(uint32_t) =
- xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
- mmu_attr_to_access : region_attr_to_access;
-
- for (wi = 0; wi < conf->nways; ++wi) {
- uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
- const char *sz_text;
- bool print_header = true;
-
- if (sz >= 0x100000) {
- sz >>= 20;
- sz_text = "MB";
- } else {
- sz >>= 10;
- sz_text = "KB";
- }
-
- for (ei = 0; ei < conf->way_size[wi]; ++ei) {
- const xtensa_tlb_entry *entry =
- xtensa_tlb_get_entry(env, dtlb, wi, ei);
-
- if (entry->asid) {
- static const char * const cache_text[8] = {
- [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
- [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
- [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
- [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
- };
- unsigned access = attr_to_access(entry->attr);
- unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
- PAGE_CACHE_SHIFT;
-
- if (print_header) {
- print_header = false;
- cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
- cpu_fprintf(f,
- "\tVaddr Paddr ASID Attr RWX Cache\n"
- "\t---------- ---------- ---- ---- --- -------\n");
- }
- cpu_fprintf(f,
- "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
- entry->vaddr,
- entry->paddr,
- entry->asid,
- entry->attr,
- (access & PAGE_READ) ? 'R' : '-',
- (access & PAGE_WRITE) ? 'W' : '-',
- (access & PAGE_EXEC) ? 'X' : '-',
- cache_text[cache_idx] ? cache_text[cache_idx] :
- "Invalid");
- }
- }
- }
-}
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
-{
- if (xtensa_option_bits_enabled(env->config,
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
-
- cpu_fprintf(f, "ITLB:\n");
- dump_tlb(f, cpu_fprintf, env, false);
- cpu_fprintf(f, "\nDTLB:\n");
- dump_tlb(f, cpu_fprintf, env, true);
- } else {
- cpu_fprintf(f, "No TLB for this CPU core\n");
- }
+ cpu_restore_state(cs, retaddr, true);
+ HELPER(exception_cause_vaddr)(env, env->pc,
+ access_type == MMU_INST_FETCH ?
+ INSTR_PIF_ADDR_ERROR_CAUSE :
+ LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
+ addr);
}
void xtensa_runstall(CPUXtensaState *env, bool runstall)
{
- CPUState *cpu = CPU(xtensa_env_get_cpu(env));
+ CPUState *cpu = env_cpu(env);
env->runstall = runstall;
cpu->halted = runstall;
if (runstall) {
cpu_interrupt(cpu, CPU_INTERRUPT_HALT);
} else {
- cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT);
+ qemu_cpu_kick(cpu);
}
}
+#endif
projects / qemu.git / blobdiff