#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
+#include "helper.h"
+#include "tcg-op.h"
+#include "qemu-common.h"
//#define MIPS_DEBUG_DISAS
//#define MIPS_DEBUG_SIGN_EXTENSIONS
//#define MIPS_SINGLE_STEP
-#ifdef USE_DIRECT_JUMP
-#define TBPARAM(x)
-#else
-#define TBPARAM(x) (long)(x)
-#endif
-
-enum {
-#define DEF(s, n, copy_size) INDEX_op_ ## s,
-#include "opc.h"
-#undef DEF
- NB_OPS,
-};
-
-static uint16_t *gen_opc_ptr;
-static uint32_t *gen_opparam_ptr;
-
-#include "gen-op.h"
-
/* MIPS major opcodes */
#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
};
+/* Multiplication variants of the vr54xx. */
+#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
+
+enum {
+ OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
+ OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
+ OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
+ OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
+ OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
+ OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
+ OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
+ OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
+ OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
+ OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
+ OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
+ OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
+ OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
+ OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
+};
+
/* REGIMM (rt field) opcodes */
#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
OPC_NMSUB_PS= 0x3E | OPC_CP3,
};
+/* global register indices */
+static TCGv cpu_env, current_tc_gprs, current_tc_hi, cpu_T[2];
+
+typedef struct DisasContext {
+ struct TranslationBlock *tb;
+ target_ulong pc, saved_pc;
+ uint32_t opcode;
+ uint32_t fp_status;
+ /* Routine used to access memory */
+ int mem_idx;
+ uint32_t hflags, saved_hflags;
+ int bstate;
+ target_ulong btarget;
+} DisasContext;
-const unsigned char *regnames[] =
+enum {
+ BS_NONE = 0, /* We go out of the TB without reaching a branch or an
+ * exception condition
+ */
+ BS_STOP = 1, /* We want to stop translation for any reason */
+ BS_BRANCH = 2, /* We reached a branch condition */
+ BS_EXCP = 3, /* We reached an exception condition */
+};
+
+static const char *regnames[] =
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
-/* Warning: no function for r0 register (hard wired to zero) */
-#define GEN32(func, NAME) \
-static GenOpFunc *NAME ## _table [32] = { \
-NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
-NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
-NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
-NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
-NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
-NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
-NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
-NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
-}; \
-static always_inline void func(int n) \
-{ \
- NAME ## _table[n](); \
-}
-
-/* General purpose registers moves */
-GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
-GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
-GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
-
-GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
-GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
-
-/* Moves to/from shadow registers */
-GEN32(gen_op_load_srsgpr_T0, gen_op_load_srsgpr_T0_gpr);
-GEN32(gen_op_store_T0_srsgpr, gen_op_store_T0_srsgpr_gpr);
-
static const char *fregnames[] =
{ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
+#ifdef MIPS_DEBUG_DISAS
+#define MIPS_DEBUG(fmt, args...) \
+do { \
+ if (loglevel & CPU_LOG_TB_IN_ASM) { \
+ fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
+ ctx->pc, ctx->opcode , ##args); \
+ } \
+} while (0)
+#else
+#define MIPS_DEBUG(fmt, args...) do { } while(0)
+#endif
+
+#define MIPS_INVAL(op) \
+do { \
+ MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
+ ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
+} while (0)
+
+/* General purpose registers moves. */
+static inline void gen_load_gpr (TCGv t, int reg)
+{
+ if (reg == 0)
+ tcg_gen_movi_tl(t, 0);
+ else
+ tcg_gen_ld_tl(t, current_tc_gprs, sizeof(target_ulong) * reg);
+}
+
+static inline void gen_store_gpr (TCGv t, int reg)
+{
+ if (reg != 0)
+ tcg_gen_st_tl(t, current_tc_gprs, sizeof(target_ulong) * reg);
+}
+
+/* Moves to/from HI and LO registers. */
+static inline void gen_load_LO (TCGv t, int reg)
+{
+ tcg_gen_ld_tl(t, current_tc_hi,
+ offsetof(CPUState, LO)
+ - offsetof(CPUState, HI)
+ + sizeof(target_ulong) * reg);
+}
+
+static inline void gen_store_LO (TCGv t, int reg)
+{
+ tcg_gen_st_tl(t, current_tc_hi,
+ offsetof(CPUState, LO)
+ - offsetof(CPUState, HI)
+ + sizeof(target_ulong) * reg);
+}
+
+static inline void gen_load_HI (TCGv t, int reg)
+{
+ tcg_gen_ld_tl(t, current_tc_hi, sizeof(target_ulong) * reg);
+}
+
+static inline void gen_store_HI (TCGv t, int reg)
+{
+ tcg_gen_st_tl(t, current_tc_hi, sizeof(target_ulong) * reg);
+}
+
+/* Moves to/from shadow registers. */
+static inline void gen_load_srsgpr (TCGv t, int reg)
+{
+ if (reg == 0)
+ tcg_gen_movi_tl(t, 0);
+ else {
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
+ tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
+ tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
+ tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
+
+ tcg_gen_ld_tl(t, r_tmp, sizeof(target_ulong) * reg);
+ tcg_temp_free(r_tmp);
+ }
+}
+
+static inline void gen_store_srsgpr (TCGv t, int reg)
+{
+ if (reg != 0) {
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
+ tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
+ tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
+ tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
+
+ tcg_gen_st_tl(t, r_tmp, sizeof(target_ulong) * reg);
+ tcg_temp_free(r_tmp);
+ }
+}
+
+/* Floating point register moves. */
#define FGEN32(func, NAME) \
static GenOpFunc *NAME ## _table [32] = { \
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
FGEN32(gen_op_load_fpr_WTH2, gen_op_load_fpr_WTH2_fpr);
FGEN32(gen_op_store_fpr_WTH2, gen_op_store_fpr_WTH2_fpr);
+#define GEN_LOAD_FREG_FTN(FTn, Fn) \
+do { \
+ glue(gen_op_load_fpr_, FTn)(Fn); \
+} while (0)
+
+#define GEN_STORE_FTN_FREG(Fn, FTn) \
+do { \
+ glue(gen_op_store_fpr_, FTn)(Fn); \
+} while (0)
+
#define FOP_CONDS(type, fmt) \
static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
gen_op_cmp ## type ## _ ## fmt ## _f, \
FOP_CONDS(, ps)
FOP_CONDS(abs, ps)
-typedef struct DisasContext {
- struct TranslationBlock *tb;
- target_ulong pc, saved_pc;
- uint32_t opcode;
- uint32_t fp_status;
- /* Routine used to access memory */
- int mem_idx;
- uint32_t hflags, saved_hflags;
- int bstate;
- target_ulong btarget;
-} DisasContext;
-
-enum {
- BS_NONE = 0, /* We go out of the TB without reaching a branch or an
- * exception condition
- */
- BS_STOP = 1, /* We want to stop translation for any reason */
- BS_BRANCH = 2, /* We reached a branch condition */
- BS_EXCP = 3, /* We reached an exception condition */
-};
-
-#ifdef MIPS_DEBUG_DISAS
-#define MIPS_DEBUG(fmt, args...) \
-do { \
- if (loglevel & CPU_LOG_TB_IN_ASM) { \
- fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
- ctx->pc, ctx->opcode , ##args); \
- } \
-} while (0)
-#else
-#define MIPS_DEBUG(fmt, args...) do { } while(0)
-#endif
-
-#define MIPS_INVAL(op) \
-do { \
- MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
- ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
-} while (0)
-
-#define GEN_LOAD_REG_TN(Tn, Rn) \
-do { \
- if (Rn == 0) { \
- glue(gen_op_reset_, Tn)(); \
- } else { \
- glue(gen_op_load_gpr_, Tn)(Rn); \
- } \
-} while (0)
-
-#define GEN_LOAD_SRSREG_TN(Tn, Rn) \
-do { \
- if (Rn == 0) { \
- glue(gen_op_reset_, Tn)(); \
- } else { \
- glue(gen_op_load_srsgpr_, Tn)(Rn); \
- } \
-} while (0)
-
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
-#define GEN_LOAD_IMM_TN(Tn, Imm) \
-do { \
- if (Imm == 0) { \
- glue(gen_op_reset_, Tn)(); \
- } else if ((int32_t)Imm == Imm) { \
- glue(gen_op_set_, Tn)(Imm); \
- } else { \
- glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm); \
- } \
-} while (0)
-#else
-#define GEN_LOAD_IMM_TN(Tn, Imm) \
-do { \
- if (Imm == 0) { \
- glue(gen_op_reset_, Tn)(); \
- } else { \
- glue(gen_op_set_, Tn)(Imm); \
- } \
-} while (0)
-#endif
-
-#define GEN_STORE_TN_REG(Rn, Tn) \
-do { \
- if (Rn != 0) { \
- glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
- } \
-} while (0)
-
-#define GEN_STORE_TN_SRSREG(Rn, Tn) \
-do { \
- if (Rn != 0) { \
- glue(glue(gen_op_store_, Tn),_srsgpr)(Rn); \
- } \
-} while (0)
+/* Tests */
+#define OP_COND(name, cond) \
+void glue(gen_op_, name) (void) \
+{ \
+ int l1 = gen_new_label(); \
+ int l2 = gen_new_label(); \
+ \
+ tcg_gen_brcond_tl(cond, cpu_T[0], cpu_T[1], l1); \
+ tcg_gen_movi_tl(cpu_T[0], 0); \
+ tcg_gen_br(l2); \
+ gen_set_label(l1); \
+ tcg_gen_movi_tl(cpu_T[0], 1); \
+ gen_set_label(l2); \
+}
+OP_COND(eq, TCG_COND_EQ);
+OP_COND(ne, TCG_COND_NE);
+OP_COND(ge, TCG_COND_GE);
+OP_COND(geu, TCG_COND_GEU);
+OP_COND(lt, TCG_COND_LT);
+OP_COND(ltu, TCG_COND_LTU);
+#undef OP_COND
+
+#define OP_CONDI(name, cond) \
+void glue(gen_op_, name) (target_ulong val) \
+{ \
+ int l1 = gen_new_label(); \
+ int l2 = gen_new_label(); \
+ \
+ tcg_gen_brcondi_tl(cond, cpu_T[0], val, l1); \
+ tcg_gen_movi_tl(cpu_T[0], 0); \
+ tcg_gen_br(l2); \
+ gen_set_label(l1); \
+ tcg_gen_movi_tl(cpu_T[0], 1); \
+ gen_set_label(l2); \
+}
+OP_CONDI(lti, TCG_COND_LT);
+OP_CONDI(ltiu, TCG_COND_LTU);
+#undef OP_CONDI
+
+#define OP_CONDZ(name, cond) \
+void glue(gen_op_, name) (void) \
+{ \
+ int l1 = gen_new_label(); \
+ int l2 = gen_new_label(); \
+ \
+ tcg_gen_brcondi_tl(cond, cpu_T[0], 0, l1); \
+ tcg_gen_movi_tl(cpu_T[0], 0); \
+ tcg_gen_br(l2); \
+ gen_set_label(l1); \
+ tcg_gen_movi_tl(cpu_T[0], 1); \
+ gen_set_label(l2); \
+}
+OP_CONDZ(gez, TCG_COND_GE);
+OP_CONDZ(gtz, TCG_COND_GT);
+OP_CONDZ(lez, TCG_COND_LE);
+OP_CONDZ(ltz, TCG_COND_LT);
+#undef OP_CONDZ
-#define GEN_LOAD_FREG_FTN(FTn, Fn) \
-do { \
- glue(gen_op_load_fpr_, FTn)(Fn); \
-} while (0)
+static inline void gen_save_pc(target_ulong pc)
+{
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tc_off = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tc_off_ptr = tcg_temp_new(TCG_TYPE_PTR);
+ TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
+
+ tcg_gen_movi_tl(r_tmp, pc);
+ tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
+ tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
+ tcg_gen_ext_i32_ptr(r_tc_off_ptr, r_tc_off);
+ tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
+ tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
+ tcg_temp_free(r_tc_off);
+ tcg_temp_free(r_tc_off_tl);
+ tcg_temp_free(r_ptr);
+ tcg_temp_free(r_tmp);
+}
-#define GEN_STORE_FTN_FREG(Fn, FTn) \
-do { \
- glue(gen_op_store_fpr_, FTn)(Fn); \
-} while (0)
+static inline void gen_breg_pc(void)
+{
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tc_off = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tc_off_ptr = tcg_temp_new(TCG_TYPE_PTR);
+ TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
+
+ tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
+ tcg_gen_ld_i32(r_tc_off, cpu_env, offsetof(CPUState, current_tc));
+ tcg_gen_muli_i32(r_tc_off, r_tc_off, sizeof(target_ulong));
+ tcg_gen_ext_i32_ptr(r_tc_off_ptr, r_tc_off);
+ tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
+ tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
+ tcg_temp_free(r_tc_off);
+ tcg_temp_free(r_tc_off_tl);
+ tcg_temp_free(r_ptr);
+ tcg_temp_free(r_tmp);
+}
-static always_inline void gen_save_pc(target_ulong pc)
+static inline void gen_save_btarget(target_ulong btarget)
{
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
- if (pc == (int32_t)pc) {
- gen_op_save_pc(pc);
- } else {
- gen_op_save_pc64(pc >> 32, (uint32_t)pc);
- }
-#else
- gen_op_save_pc(pc);
-#endif
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
+
+ tcg_gen_movi_tl(r_tmp, btarget);
+ tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
}
-static always_inline void gen_save_btarget(target_ulong btarget)
+static always_inline void gen_save_breg_target(int reg)
{
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
- if (btarget == (int32_t)btarget) {
- gen_op_save_btarget(btarget);
- } else {
- gen_op_save_btarget64(btarget >> 32, (uint32_t)btarget);
- }
-#else
- gen_op_save_btarget(btarget);
-#endif
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
+
+ gen_load_gpr(r_tmp, reg);
+ tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, btarget));
}
static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
ctx->saved_hflags = ctx->hflags;
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
case MIPS_HFLAG_BR:
- gen_op_save_breg_target();
break;
case MIPS_HFLAG_BC:
- gen_op_save_bcond();
- /* fall through */
case MIPS_HFLAG_BL:
- /* bcond was already saved by the BL insn */
- /* fall through */
case MIPS_HFLAG_B:
gen_save_btarget(ctx->btarget);
break;
ctx->saved_hflags = ctx->hflags;
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
case MIPS_HFLAG_BR:
- gen_op_restore_breg_target();
- break;
- case MIPS_HFLAG_B:
- ctx->btarget = env->btarget;
break;
case MIPS_HFLAG_BC:
case MIPS_HFLAG_BL:
+ case MIPS_HFLAG_B:
ctx->btarget = env->btarget;
- gen_op_restore_bcond();
break;
}
}
-static always_inline void generate_exception_err (DisasContext *ctx, int excp, int err)
+static always_inline void
+generate_exception_err (DisasContext *ctx, int excp, int err)
{
-#if defined MIPS_DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_IN_ASM)
- fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
-#endif
save_cpu_state(ctx, 1);
- if (err == 0)
- gen_op_raise_exception(excp);
- else
- gen_op_raise_exception_err(excp, err);
- ctx->bstate = BS_EXCP;
+ tcg_gen_helper_0_2(do_raise_exception_err, tcg_const_i32(excp), tcg_const_i32(err));
+ tcg_gen_helper_0_0(do_interrupt_restart);
+ tcg_gen_exit_tb(0);
}
-static always_inline void generate_exception (DisasContext *ctx, int excp)
+static always_inline void
+generate_exception (DisasContext *ctx, int excp)
{
- generate_exception_err (ctx, excp, 0);
+ save_cpu_state(ctx, 1);
+ tcg_gen_helper_0_1(do_raise_exception, tcg_const_i32(excp));
+ tcg_gen_helper_0_0(do_interrupt_restart);
+ tcg_gen_exit_tb(0);
+}
+
+/* Addresses computation */
+static inline void gen_op_addr_add (void)
+{
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+
+#if defined(TARGET_MIPS64)
+ /* For compatibility with 32-bit code, data reference in user mode
+ with Status_UX = 0 should be casted to 32-bit and sign extended.
+ See the MIPS64 PRA manual, section 4.10. */
+ {
+ int l1 = gen_new_label();
+
+ {
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
+ tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
+ tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
+ }
+ {
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
+ tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
+ tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
+ }
+ tcg_gen_ext32s_i64(cpu_T[0], cpu_T[0]);
+ gen_set_label(l1);
+ }
+#endif
}
static always_inline void check_cp0_enabled(DisasContext *ctx)
generate_exception_err(ctx, EXCP_CpU, 1);
}
+/* Verify that the processor is running with COP1X instructions enabled.
+ This is associated with the nabla symbol in the MIPS32 and MIPS64
+ opcode tables. */
+
+static always_inline void check_cop1x(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
+ generate_exception(ctx, EXCP_RI);
+}
+
+/* Verify that the processor is running with 64-bit floating-point
+ operations enabled. */
+
static always_inline void check_cp1_64bitmode(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64)))
+ if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
generate_exception(ctx, EXCP_RI);
}
generate_exception(ctx, EXCP_RI);
}
+/* load/store instructions. */
#if defined(CONFIG_USER_ONLY)
#define op_ldst(name) gen_op_##name##_raw()
#define OP_LD_TABLE(width)
#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
#define OP_LD_TABLE(width) \
static GenOpFunc *gen_op_l##width[] = { \
- &gen_op_l##width##_user, \
&gen_op_l##width##_kernel, \
+ &gen_op_l##width##_super, \
+ &gen_op_l##width##_user, \
}
#define OP_ST_TABLE(width) \
static GenOpFunc *gen_op_s##width[] = { \
- &gen_op_s##width##_user, \
&gen_op_s##width##_kernel, \
+ &gen_op_s##width##_super, \
+ &gen_op_s##width##_user, \
}
#endif
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
-OP_LD_TABLE(d);
+#if defined(TARGET_MIPS64)
OP_LD_TABLE(dl);
OP_LD_TABLE(dr);
-OP_ST_TABLE(d);
OP_ST_TABLE(dl);
OP_ST_TABLE(dr);
-OP_LD_TABLE(ld);
-OP_ST_TABLE(cd);
-OP_LD_TABLE(wu);
#endif
-OP_LD_TABLE(w);
OP_LD_TABLE(wl);
OP_LD_TABLE(wr);
-OP_ST_TABLE(w);
OP_ST_TABLE(wl);
OP_ST_TABLE(wr);
-OP_LD_TABLE(h);
-OP_LD_TABLE(hu);
-OP_ST_TABLE(h);
-OP_LD_TABLE(b);
-OP_LD_TABLE(bu);
-OP_ST_TABLE(b);
-OP_LD_TABLE(l);
-OP_ST_TABLE(c);
OP_LD_TABLE(wc1);
OP_ST_TABLE(wc1);
OP_LD_TABLE(dc1);
OP_LD_TABLE(uxc1);
OP_ST_TABLE(uxc1);
+#define OP_LD(insn,fname) \
+void inline op_ldst_##insn(DisasContext *ctx) \
+{ \
+ tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \
+}
+OP_LD(lb,ld8s);
+OP_LD(lbu,ld8u);
+OP_LD(lh,ld16s);
+OP_LD(lhu,ld16u);
+OP_LD(lw,ld32s);
+#if defined(TARGET_MIPS64)
+OP_LD(lwu,ld32u);
+OP_LD(ld,ld64);
+#endif
+#undef OP_LD
+
+#define OP_ST(insn,fname) \
+void inline op_ldst_##insn(DisasContext *ctx) \
+{ \
+ tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \
+}
+OP_ST(sb,st8);
+OP_ST(sh,st16);
+OP_ST(sw,st32);
+#if defined(TARGET_MIPS64)
+OP_ST(sd,st64);
+#endif
+#undef OP_ST
+
+#define OP_LD_ATOMIC(insn,fname) \
+void inline op_ldst_##insn(DisasContext *ctx) \
+{ \
+ tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); \
+ tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx); \
+ tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUState, CP0_LLAddr)); \
+}
+OP_LD_ATOMIC(ll,ld32s);
+#if defined(TARGET_MIPS64)
+OP_LD_ATOMIC(lld,ld64);
+#endif
+#undef OP_LD_ATOMIC
+
+#define OP_ST_ATOMIC(insn,fname,almask) \
+void inline op_ldst_##insn(DisasContext *ctx) \
+{ \
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL); \
+ int l1 = gen_new_label(); \
+ int l2 = gen_new_label(); \
+ int l3 = gen_new_label(); \
+ \
+ tcg_gen_andi_tl(r_tmp, cpu_T[0], almask); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
+ generate_exception(ctx, EXCP_AdES); \
+ gen_set_label(l1); \
+ tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
+ tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2); \
+ tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx); \
+ tcg_gen_movi_tl(cpu_T[0], 1); \
+ tcg_gen_br(l3); \
+ gen_set_label(l2); \
+ tcg_gen_movi_tl(cpu_T[0], 0); \
+ gen_set_label(l3); \
+}
+OP_ST_ATOMIC(sc,st32,0x3);
+#if defined(TARGET_MIPS64)
+OP_ST_ATOMIC(scd,st64,0x7);
+#endif
+#undef OP_ST_ATOMIC
+
+void inline op_ldst_lwc1(DisasContext *ctx)
+{
+ op_ldst(lwc1);
+}
+
+void inline op_ldst_ldc1(DisasContext *ctx)
+{
+ op_ldst(ldc1);
+}
+
+void inline op_ldst_swc1(DisasContext *ctx)
+{
+ op_ldst(swc1);
+}
+
+void inline op_ldst_sdc1(DisasContext *ctx)
+{
+ op_ldst(sdc1);
+}
+
/* Load and store */
static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
int base, int16_t offset)
const char *opn = "ldst";
if (base == 0) {
- GEN_LOAD_IMM_TN(T0, offset);
+ tcg_gen_movi_tl(cpu_T[0], offset);
} else if (offset == 0) {
- gen_op_load_gpr_T0(base);
+ gen_load_gpr(cpu_T[0], base);
} else {
- gen_op_load_gpr_T0(base);
- gen_op_set_T1(offset);
+ gen_load_gpr(cpu_T[0], base);
+ tcg_gen_movi_tl(cpu_T[1], offset);
gen_op_addr_add();
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_LWU:
- op_ldst(lwu);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_lwu(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "lwu";
break;
case OPC_LD:
- op_ldst(ld);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_ld(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "ld";
break;
case OPC_LLD:
- op_ldst(lld);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_lld(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "lld";
break;
case OPC_SD:
- GEN_LOAD_REG_TN(T1, rt);
- op_ldst(sd);
+ gen_load_gpr(cpu_T[1], rt);
+ op_ldst_sd(ctx);
opn = "sd";
break;
case OPC_SCD:
save_cpu_state(ctx, 1);
- GEN_LOAD_REG_TN(T1, rt);
- op_ldst(scd);
- GEN_STORE_TN_REG(rt, T0);
+ gen_load_gpr(cpu_T[1], rt);
+ op_ldst_scd(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "scd";
break;
case OPC_LDL:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(ldl);
- GEN_STORE_TN_REG(rt, T1);
+ gen_store_gpr(cpu_T[1], rt);
opn = "ldl";
break;
case OPC_SDL:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(sdl);
opn = "sdl";
break;
case OPC_LDR:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(ldr);
- GEN_STORE_TN_REG(rt, T1);
+ gen_store_gpr(cpu_T[1], rt);
opn = "ldr";
break;
case OPC_SDR:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(sdr);
opn = "sdr";
break;
#endif
case OPC_LW:
- op_ldst(lw);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_lw(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "lw";
break;
case OPC_SW:
- GEN_LOAD_REG_TN(T1, rt);
- op_ldst(sw);
+ gen_load_gpr(cpu_T[1], rt);
+ op_ldst_sw(ctx);
opn = "sw";
break;
case OPC_LH:
- op_ldst(lh);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_lh(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "lh";
break;
case OPC_SH:
- GEN_LOAD_REG_TN(T1, rt);
- op_ldst(sh);
+ gen_load_gpr(cpu_T[1], rt);
+ op_ldst_sh(ctx);
opn = "sh";
break;
case OPC_LHU:
- op_ldst(lhu);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_lhu(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "lhu";
break;
case OPC_LB:
- op_ldst(lb);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_lb(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "lb";
break;
case OPC_SB:
- GEN_LOAD_REG_TN(T1, rt);
- op_ldst(sb);
+ gen_load_gpr(cpu_T[1], rt);
+ op_ldst_sb(ctx);
opn = "sb";
break;
case OPC_LBU:
- op_ldst(lbu);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_lbu(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "lbu";
break;
case OPC_LWL:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(lwl);
- GEN_STORE_TN_REG(rt, T1);
+ gen_store_gpr(cpu_T[1], rt);
opn = "lwl";
break;
case OPC_SWL:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(swl);
opn = "swr";
break;
case OPC_LWR:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(lwr);
- GEN_STORE_TN_REG(rt, T1);
+ gen_store_gpr(cpu_T[1], rt);
opn = "lwr";
break;
case OPC_SWR:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
op_ldst(swr);
opn = "swr";
break;
case OPC_LL:
- op_ldst(ll);
- GEN_STORE_TN_REG(rt, T0);
+ op_ldst_ll(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "ll";
break;
case OPC_SC:
save_cpu_state(ctx, 1);
- GEN_LOAD_REG_TN(T1, rt);
- op_ldst(sc);
- GEN_STORE_TN_REG(rt, T0);
+ gen_load_gpr(cpu_T[1], rt);
+ op_ldst_sc(ctx);
+ gen_store_gpr(cpu_T[0], rt);
opn = "sc";
break;
default:
const char *opn = "flt_ldst";
if (base == 0) {
- GEN_LOAD_IMM_TN(T0, offset);
+ tcg_gen_movi_tl(cpu_T[0], offset);
} else if (offset == 0) {
- gen_op_load_gpr_T0(base);
+ gen_load_gpr(cpu_T[0], base);
} else {
- gen_op_load_gpr_T0(base);
- gen_op_set_T1(offset);
+ gen_load_gpr(cpu_T[0], base);
+ tcg_gen_movi_tl(cpu_T[1], offset);
gen_op_addr_add();
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
case OPC_LWC1:
- op_ldst(lwc1);
+ op_ldst_lwc1(ctx);
GEN_STORE_FTN_FREG(ft, WT0);
opn = "lwc1";
break;
case OPC_SWC1:
GEN_LOAD_FREG_FTN(WT0, ft);
- op_ldst(swc1);
+ op_ldst_swc1(ctx);
opn = "swc1";
break;
case OPC_LDC1:
- op_ldst(ldc1);
+ op_ldst_ldc1(ctx);
GEN_STORE_FTN_FREG(ft, DT0);
opn = "ldc1";
break;
case OPC_SDC1:
GEN_LOAD_FREG_FTN(DT0, ft);
- op_ldst(sdc1);
+ op_ldst_sdc1(ctx);
opn = "sdc1";
break;
default:
switch (opc) {
case OPC_ADDI:
case OPC_ADDIU:
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DADDI:
case OPC_DADDIU:
#endif
case OPC_SLTI:
case OPC_SLTIU:
uimm = (target_long)imm; /* Sign extend to 32/64 bits */
+ tcg_gen_movi_tl(cpu_T[1], uimm);
/* Fall through. */
case OPC_ANDI:
case OPC_ORI:
case OPC_XORI:
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_IMM_TN(T1, uimm);
+ gen_load_gpr(cpu_T[0], rs);
break;
case OPC_LUI:
- GEN_LOAD_IMM_TN(T0, imm << 16);
+ tcg_gen_movi_tl(cpu_T[0], imm << 16);
break;
case OPC_SLL:
case OPC_SRA:
case OPC_SRL:
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DSLL:
case OPC_DSRA:
case OPC_DSRL:
case OPC_DSRL32:
#endif
uimm &= 0x1f;
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_IMM_TN(T1, uimm);
+ gen_load_gpr(cpu_T[0], rs);
break;
}
switch (opc) {
case OPC_ADDI:
- save_cpu_state(ctx, 1);
- gen_op_addo();
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
+ save_cpu_state(ctx, 1);
+ tcg_gen_ext32s_tl(r_tmp1, cpu_T[0]);
+ tcg_gen_addi_tl(cpu_T[0], r_tmp1, uimm);
+
+ tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm);
+ tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
+ tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
+ tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
+ /* operands of same sign, result different sign */
+ generate_exception(ctx, EXCP_OVERFLOW);
+ gen_set_label(l1);
+
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ }
opn = "addi";
break;
case OPC_ADDIU:
- gen_op_add();
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_addi_tl(cpu_T[0], cpu_T[0], uimm);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "addiu";
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DADDI:
- save_cpu_state(ctx, 1);
- gen_op_daddo();
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
+ save_cpu_state(ctx, 1);
+ tcg_gen_mov_tl(r_tmp1, cpu_T[0]);
+ tcg_gen_addi_tl(cpu_T[0], cpu_T[0], uimm);
+
+ tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm);
+ tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
+ tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
+ tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
+ /* operands of same sign, result different sign */
+ generate_exception(ctx, EXCP_OVERFLOW);
+ gen_set_label(l1);
+ }
opn = "daddi";
break;
case OPC_DADDIU:
- gen_op_dadd();
+ tcg_gen_addi_tl(cpu_T[0], cpu_T[0], uimm);
opn = "daddiu";
break;
#endif
case OPC_SLTI:
- gen_op_lt();
+ gen_op_lti(uimm);
opn = "slti";
break;
case OPC_SLTIU:
- gen_op_ltu();
+ gen_op_ltiu(uimm);
opn = "sltiu";
break;
case OPC_ANDI:
- gen_op_and();
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], uimm);
opn = "andi";
break;
case OPC_ORI:
- gen_op_or();
+ tcg_gen_ori_tl(cpu_T[0], cpu_T[0], uimm);
opn = "ori";
break;
case OPC_XORI:
- gen_op_xor();
+ tcg_gen_xori_tl(cpu_T[0], cpu_T[0], uimm);
opn = "xori";
break;
case OPC_LUI:
opn = "lui";
break;
case OPC_SLL:
- gen_op_sll();
+ tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_shli_tl(cpu_T[0], cpu_T[0], uimm);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "sll";
break;
case OPC_SRA:
- gen_op_sra();
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_sari_tl(cpu_T[0], cpu_T[0], uimm);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "sra";
break;
case OPC_SRL:
switch ((ctx->opcode >> 21) & 0x1f) {
case 0:
- gen_op_srl();
+ tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "srl";
break;
case 1:
/* rotr is decoded as srl on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
- gen_op_rotr();
+ if (uimm != 0) {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
+ tcg_gen_movi_i32(r_tmp2, 0x20);
+ tcg_gen_subi_i32(r_tmp2, r_tmp2, uimm);
+ tcg_gen_shl_i32(r_tmp2, r_tmp1, r_tmp2);
+ tcg_gen_shri_i32(r_tmp1, r_tmp1, uimm);
+ tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
+ tcg_temp_free(r_tmp1);
+ tcg_temp_free(r_tmp2);
+ }
opn = "rotr";
} else {
- gen_op_srl();
+ tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "srl";
}
break;
break;
}
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DSLL:
- gen_op_dsll();
+ tcg_gen_shli_tl(cpu_T[0], cpu_T[0], uimm);
opn = "dsll";
break;
case OPC_DSRA:
- gen_op_dsra();
+ tcg_gen_sari_tl(cpu_T[0], cpu_T[0], uimm);
opn = "dsra";
break;
case OPC_DSRL:
switch ((ctx->opcode >> 21) & 0x1f) {
case 0:
- gen_op_dsrl();
+ tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
opn = "dsrl";
break;
case 1:
/* drotr is decoded as dsrl on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
- gen_op_drotr();
+ if (uimm != 0) {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+
+ tcg_gen_movi_tl(r_tmp1, 0x40);
+ tcg_gen_subi_tl(r_tmp1, r_tmp1, uimm);
+ tcg_gen_shl_tl(r_tmp1, cpu_T[0], r_tmp1);
+ tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
+ tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
+ }
opn = "drotr";
} else {
- gen_op_dsrl();
+ tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
opn = "dsrl";
}
break;
}
break;
case OPC_DSLL32:
- gen_op_dsll32();
+ tcg_gen_shli_tl(cpu_T[0], cpu_T[0], uimm + 32);
opn = "dsll32";
break;
case OPC_DSRA32:
- gen_op_dsra32();
+ tcg_gen_sari_tl(cpu_T[0], cpu_T[0], uimm + 32);
opn = "dsra32";
break;
case OPC_DSRL32:
switch ((ctx->opcode >> 21) & 0x1f) {
case 0:
- gen_op_dsrl32();
+ tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm + 32);
opn = "dsrl32";
break;
case 1:
/* drotr32 is decoded as dsrl32 on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
- gen_op_drotr32();
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+
+ tcg_gen_movi_tl(r_tmp1, 0x40);
+ tcg_gen_movi_tl(r_tmp2, 32);
+ tcg_gen_addi_tl(r_tmp2, r_tmp2, uimm);
+ tcg_gen_sub_tl(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_shl_tl(r_tmp1, cpu_T[0], r_tmp1);
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[0], r_tmp2);
+ tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
opn = "drotr32";
} else {
- gen_op_dsrl32();
+ tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm + 32);
opn = "dsrl32";
}
break;
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
}
MIPS_DEBUG("NOP");
return;
}
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[0], rs);
+ /* Specialcase the conventional move operation. */
+ if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU
+ || opc == OPC_SUBU || opc == OPC_DSUBU)) {
+ gen_store_gpr(cpu_T[0], rd);
+ return;
+ }
+ gen_load_gpr(cpu_T[1], rt);
switch (opc) {
case OPC_ADD:
- save_cpu_state(ctx, 1);
- gen_op_addo();
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
+ save_cpu_state(ctx, 1);
+ tcg_gen_ext32s_tl(r_tmp1, cpu_T[0]);
+ tcg_gen_ext32s_tl(r_tmp2, cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], r_tmp1, r_tmp2);
+
+ tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[1]);
+ tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
+ tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
+ tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
+ /* operands of same sign, result different sign */
+ generate_exception(ctx, EXCP_OVERFLOW);
+ gen_set_label(l1);
+
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ }
opn = "add";
break;
case OPC_ADDU:
- gen_op_add();
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "addu";
break;
case OPC_SUB:
- save_cpu_state(ctx, 1);
- gen_op_subo();
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
+ save_cpu_state(ctx, 1);
+ tcg_gen_ext32s_tl(r_tmp1, cpu_T[0]);
+ tcg_gen_ext32s_tl(r_tmp2, cpu_T[1]);
+ tcg_gen_sub_tl(cpu_T[0], r_tmp1, r_tmp2);
+
+ tcg_gen_xor_tl(r_tmp2, r_tmp1, cpu_T[1]);
+ tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
+ tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
+ /* operands of different sign, first operand and result different sign */
+ generate_exception(ctx, EXCP_OVERFLOW);
+ gen_set_label(l1);
+
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ }
opn = "sub";
break;
case OPC_SUBU:
- gen_op_sub();
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "subu";
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DADD:
- save_cpu_state(ctx, 1);
- gen_op_daddo();
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
+ save_cpu_state(ctx, 1);
+ tcg_gen_mov_tl(r_tmp1, cpu_T[0]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+
+ tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[1]);
+ tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
+ tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
+ tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
+ /* operands of same sign, result different sign */
+ generate_exception(ctx, EXCP_OVERFLOW);
+ gen_set_label(l1);
+ }
opn = "dadd";
break;
case OPC_DADDU:
- gen_op_dadd();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
opn = "daddu";
break;
case OPC_DSUB:
- save_cpu_state(ctx, 1);
- gen_op_dsubo();
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
+ save_cpu_state(ctx, 1);
+ tcg_gen_mov_tl(r_tmp1, cpu_T[0]);
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+
+ tcg_gen_xor_tl(r_tmp2, r_tmp1, cpu_T[1]);
+ tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
+ tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
+ /* operands of different sign, first operand and result different sign */
+ generate_exception(ctx, EXCP_OVERFLOW);
+ gen_set_label(l1);
+ }
opn = "dsub";
break;
case OPC_DSUBU:
- gen_op_dsub();
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
opn = "dsubu";
break;
#endif
opn = "sltu";
break;
case OPC_AND:
- gen_op_and();
+ tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
opn = "and";
break;
case OPC_NOR:
- gen_op_nor();
+ tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
opn = "nor";
break;
case OPC_OR:
- gen_op_or();
+ tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
opn = "or";
break;
case OPC_XOR:
- gen_op_xor();
+ tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
opn = "xor";
break;
case OPC_MUL:
- gen_op_mul();
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "mul";
break;
case OPC_MOVN:
- gen_op_movn(rd);
+ {
+ int l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
+ gen_store_gpr(cpu_T[0], rd);
+ gen_set_label(l1);
+ }
opn = "movn";
goto print;
case OPC_MOVZ:
- gen_op_movz(rd);
+ {
+ int l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], 0, l1);
+ gen_store_gpr(cpu_T[0], rd);
+ gen_set_label(l1);
+ }
opn = "movz";
goto print;
case OPC_SLLV:
- gen_op_sllv();
+ tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
+ tcg_gen_shl_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "sllv";
break;
case OPC_SRAV:
- gen_op_srav();
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
+ tcg_gen_sar_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "srav";
break;
case OPC_SRLV:
switch ((ctx->opcode >> 6) & 0x1f) {
case 0:
- gen_op_srlv();
+ tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "srlv";
break;
case 1:
/* rotrv is decoded as srlv on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
- gen_op_rotrv();
+ int l1 = gen_new_label();
+ int l2 = gen_new_label();
+
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
+ tcg_gen_movi_i32(r_tmp3, 0x20);
+ tcg_gen_sub_i32(r_tmp3, r_tmp3, r_tmp1);
+ tcg_gen_shl_i32(r_tmp3, r_tmp2, r_tmp3);
+ tcg_gen_shr_i32(r_tmp1, r_tmp2, r_tmp1);
+ tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp3);
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
+ tcg_temp_free(r_tmp1);
+ tcg_temp_free(r_tmp2);
+ tcg_temp_free(r_tmp3);
+ tcg_gen_br(l2);
+ }
+ gen_set_label(l1);
+ tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
+ gen_set_label(l2);
opn = "rotrv";
} else {
- gen_op_srlv();
+ tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
opn = "srlv";
}
break;
break;
}
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DSLLV:
- gen_op_dsllv();
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
+ tcg_gen_shl_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
opn = "dsllv";
break;
case OPC_DSRAV:
- gen_op_dsrav();
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
+ tcg_gen_sar_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
opn = "dsrav";
break;
case OPC_DSRLV:
switch ((ctx->opcode >> 6) & 0x1f) {
case 0:
- gen_op_dsrlv();
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
opn = "dsrlv";
break;
case 1:
/* drotrv is decoded as dsrlv on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
- gen_op_drotrv();
+ int l1 = gen_new_label();
+ int l2 = gen_new_label();
+
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+
+ tcg_gen_movi_tl(r_tmp1, 0x40);
+ tcg_gen_sub_tl(r_tmp1, r_tmp1, cpu_T[0]);
+ tcg_gen_shl_tl(r_tmp1, cpu_T[1], r_tmp1);
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
+ tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
+ tcg_gen_br(l2);
+ }
+ gen_set_label(l1);
+ tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
+ gen_set_label(l2);
opn = "drotrv";
} else {
- gen_op_dsrlv();
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
opn = "dsrlv";
}
break;
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_STORE_TN_REG(rd, T0);
+ gen_store_gpr(cpu_T[0], rd);
print:
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
}
}
switch (opc) {
case OPC_MFHI:
- gen_op_load_HI(0);
- GEN_STORE_TN_REG(reg, T0);
+ gen_load_HI(cpu_T[0], 0);
+ gen_store_gpr(cpu_T[0], reg);
opn = "mfhi";
break;
case OPC_MFLO:
- gen_op_load_LO(0);
- GEN_STORE_TN_REG(reg, T0);
+ gen_load_LO(cpu_T[0], 0);
+ gen_store_gpr(cpu_T[0], reg);
opn = "mflo";
break;
case OPC_MTHI:
- GEN_LOAD_REG_TN(T0, reg);
- gen_op_store_HI(0);
+ gen_load_gpr(cpu_T[0], reg);
+ gen_store_HI(cpu_T[0], 0);
opn = "mthi";
break;
case OPC_MTLO:
- GEN_LOAD_REG_TN(T0, reg);
- gen_op_store_LO(0);
+ gen_load_gpr(cpu_T[0], reg);
+ gen_store_LO(cpu_T[0], 0);
opn = "mtlo";
break;
default:
{
const char *opn = "mul/div";
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[0], rs);
+ gen_load_gpr(cpu_T[1], rt);
switch (opc) {
case OPC_DIV:
- gen_op_div();
+ {
+ int l1 = gen_new_label();
+
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
+
+ tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
+ tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
+ tcg_gen_div_i64(r_tmp3, r_tmp1, r_tmp2);
+ tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
+ tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ gen_store_LO(cpu_T[0], 0);
+ gen_store_HI(cpu_T[1], 0);
+ }
+ gen_set_label(l1);
+ }
opn = "div";
break;
case OPC_DIVU:
- gen_op_divu();
+ {
+ int l1 = gen_new_label();
+
+ tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
+ tcg_gen_divu_i32(r_tmp3, r_tmp1, r_tmp2);
+ tcg_gen_remu_i32(r_tmp1, r_tmp1, r_tmp2);
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp3);
+ tcg_gen_ext_i32_tl(cpu_T[1], r_tmp1);
+ tcg_temp_free(r_tmp1);
+ tcg_temp_free(r_tmp2);
+ tcg_temp_free(r_tmp3);
+ gen_store_LO(cpu_T[0], 0);
+ gen_store_HI(cpu_T[1], 0);
+ }
+ gen_set_label(l1);
+ }
opn = "divu";
break;
case OPC_MULT:
gen_op_multu();
opn = "multu";
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DDIV:
- gen_op_ddiv();
+ {
+ int l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
+ {
+ int l2 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], -1LL << 63, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1LL, l2);
+ {
+ tcg_gen_movi_tl(cpu_T[1], 0);
+ gen_store_LO(cpu_T[0], 0);
+ gen_store_HI(cpu_T[1], 0);
+ tcg_gen_br(l1);
+ }
+ gen_set_label(l2);
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+
+ tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]);
+ tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]);
+ gen_store_LO(r_tmp1, 0);
+ gen_store_HI(r_tmp2, 0);
+ }
+ }
+ gen_set_label(l1);
+ }
opn = "ddiv";
break;
case OPC_DDIVU:
- gen_op_ddivu();
+ {
+ int l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
+ {
+ TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+
+ tcg_gen_divu_i64(r_tmp1, cpu_T[0], cpu_T[1]);
+ tcg_gen_remu_i64(r_tmp2, cpu_T[0], cpu_T[1]);
+ gen_store_LO(r_tmp1, 0);
+ gen_store_HI(r_tmp2, 0);
+ }
+ gen_set_label(l1);
+ }
opn = "ddivu";
break;
case OPC_DMULT:
MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
}
+static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
+ int rd, int rs, int rt)
+{
+ const char *opn = "mul vr54xx";
+
+ gen_load_gpr(cpu_T[0], rs);
+ gen_load_gpr(cpu_T[1], rt);
+
+ switch (opc) {
+ case OPC_VR54XX_MULS:
+ gen_op_muls();
+ opn = "muls";
+ break;
+ case OPC_VR54XX_MULSU:
+ gen_op_mulsu();
+ opn = "mulsu";
+ break;
+ case OPC_VR54XX_MACC:
+ gen_op_macc();
+ opn = "macc";
+ break;
+ case OPC_VR54XX_MACCU:
+ gen_op_maccu();
+ opn = "maccu";
+ break;
+ case OPC_VR54XX_MSAC:
+ gen_op_msac();
+ opn = "msac";
+ break;
+ case OPC_VR54XX_MSACU:
+ gen_op_msacu();
+ opn = "msacu";
+ break;
+ case OPC_VR54XX_MULHI:
+ gen_op_mulhi();
+ opn = "mulhi";
+ break;
+ case OPC_VR54XX_MULHIU:
+ gen_op_mulhiu();
+ opn = "mulhiu";
+ break;
+ case OPC_VR54XX_MULSHI:
+ gen_op_mulshi();
+ opn = "mulshi";
+ break;
+ case OPC_VR54XX_MULSHIU:
+ gen_op_mulshiu();
+ opn = "mulshiu";
+ break;
+ case OPC_VR54XX_MACCHI:
+ gen_op_macchi();
+ opn = "macchi";
+ break;
+ case OPC_VR54XX_MACCHIU:
+ gen_op_macchiu();
+ opn = "macchiu";
+ break;
+ case OPC_VR54XX_MSACHI:
+ gen_op_msachi();
+ opn = "msachi";
+ break;
+ case OPC_VR54XX_MSACHIU:
+ gen_op_msachiu();
+ opn = "msachiu";
+ break;
+ default:
+ MIPS_INVAL("mul vr54xx");
+ generate_exception(ctx, EXCP_RI);
+ return;
+ }
+ gen_store_gpr(cpu_T[0], rd);
+ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
+}
+
static void gen_cl (DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
MIPS_DEBUG("NOP");
return;
}
- GEN_LOAD_REG_TN(T0, rs);
+ gen_load_gpr(cpu_T[0], rs);
switch (opc) {
case OPC_CLO:
- gen_op_clo();
+ tcg_gen_helper_0_0(do_clo);
opn = "clo";
break;
case OPC_CLZ:
- gen_op_clz();
+ tcg_gen_helper_0_0(do_clz);
opn = "clz";
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DCLO:
- gen_op_dclo();
+ tcg_gen_helper_0_0(do_dclo);
opn = "dclo";
break;
case OPC_DCLZ:
- gen_op_dclz();
+ tcg_gen_helper_0_0(do_dclz);
opn = "dclz";
break;
#endif
generate_exception(ctx, EXCP_RI);
return;
}
- gen_op_store_T0_gpr(rd);
+ gen_store_gpr(cpu_T[0], rd);
MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
}
case OPC_TNE:
/* Compare two registers */
if (rs != rt) {
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[0], rs);
+ gen_load_gpr(cpu_T[1], rt);
cond = 1;
}
break;
case OPC_TNEI:
/* Compare register to immediate */
if (rs != 0 || imm != 0) {
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_IMM_TN(T1, (int32_t)imm);
+ gen_load_gpr(cpu_T[0], rs);
+ tcg_gen_movi_tl(cpu_T[1], (int32_t)imm);
cond = 1;
}
break;
case OPC_TGEU: /* rs >= rs unsigned */
case OPC_TGEIU: /* r0 >= 0 unsigned */
/* Always trap */
- gen_op_set_T0(1);
+ tcg_gen_movi_tl(cpu_T[0], 1);
break;
case OPC_TLT: /* rs < rs */
case OPC_TLTI: /* r0 < 0 */
TranslationBlock *tb;
tb = ctx->tb;
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
- if (n == 0)
- gen_op_goto_tb0(TBPARAM(tb));
- else
- gen_op_goto_tb1(TBPARAM(tb));
+ tcg_gen_goto_tb(n);
gen_save_pc(dest);
- gen_op_set_T0((long)tb + n);
+ tcg_gen_exit_tb((long)tb + n);
} else {
gen_save_pc(dest);
- gen_op_reset_T0();
+ tcg_gen_exit_tb(0);
}
- gen_op_exit_tb();
}
/* Branches (before delay slot) */
case OPC_BNEL:
/* Compare two registers */
if (rs != rt) {
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[0], rs);
+ gen_load_gpr(cpu_T[1], rt);
bcond = 1;
}
btarget = ctx->pc + 4 + offset;
case OPC_BLTZL:
/* Compare to zero */
if (rs != 0) {
- gen_op_load_gpr_T0(rs);
+ gen_load_gpr(cpu_T[0], rs);
bcond = 1;
}
btarget = ctx->pc + 4 + offset;
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_LOAD_REG_TN(T2, rs);
+ gen_save_breg_target(rs);
break;
default:
MIPS_INVAL("branch/jump");
MIPS_DEBUG("bnever (NOP)");
return;
case OPC_BLTZAL: /* 0 < 0 */
- GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
- gen_op_store_T0_gpr(31);
+ tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
+ gen_store_gpr(cpu_T[0], 31);
MIPS_DEBUG("bnever and link");
return;
case OPC_BLTZALL: /* 0 < 0 likely */
- GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
- gen_op_store_T0_gpr(31);
+ tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
+ gen_store_gpr(cpu_T[0], 31);
/* Skip the instruction in the delay slot */
MIPS_DEBUG("bnever, link and skip");
ctx->pc += 4;
MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
- gen_op_set_bcond();
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
break;
case OPC_BLTZALL:
gen_op_ltz();
MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
likely:
ctx->hflags |= MIPS_HFLAG_BL;
- gen_op_set_bcond();
- gen_op_save_bcond();
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
break;
default:
MIPS_INVAL("conditional branch/jump");
ctx->btarget = btarget;
if (blink > 0) {
- GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
- gen_op_store_T0_gpr(blink);
+ tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
+ gen_store_gpr(cpu_T[0], blink);
}
}
static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
int rs, int lsb, int msb)
{
- GEN_LOAD_REG_TN(T1, rs);
+ gen_load_gpr(cpu_T[1], rs);
switch (opc) {
case OPC_EXT:
if (lsb + msb > 31)
goto fail;
gen_op_ext(lsb, msb + 1);
break;
+#if defined(TARGET_MIPS64)
case OPC_DEXTM:
if (lsb + msb > 63)
goto fail;
- gen_op_ext(lsb, msb + 1 + 32);
+ gen_op_dext(lsb, msb + 1 + 32);
break;
case OPC_DEXTU:
if (lsb + msb > 63)
goto fail;
- gen_op_ext(lsb + 32, msb + 1);
+ gen_op_dext(lsb + 32, msb + 1);
break;
case OPC_DEXT:
- gen_op_ext(lsb, msb + 1);
+ if (lsb + msb > 63)
+ goto fail;
+ gen_op_dext(lsb, msb + 1);
break;
+#endif
case OPC_INS:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
gen_op_ins(lsb, msb - lsb + 1);
break;
+#if defined(TARGET_MIPS64)
case OPC_DINSM:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb, msb - lsb + 1 + 32);
+ gen_load_gpr(cpu_T[0], rt);
+ gen_op_dins(lsb, msb - lsb + 1 + 32);
break;
case OPC_DINSU:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb + 32, msb - lsb + 1);
+ gen_load_gpr(cpu_T[0], rt);
+ gen_op_dins(lsb + 32, msb - lsb + 1);
break;
case OPC_DINS:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb, msb - lsb + 1);
+ gen_load_gpr(cpu_T[0], rt);
+ gen_op_dins(lsb, msb - lsb + 1);
break;
+#endif
default:
fail:
MIPS_INVAL("bitops");
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
}
/* CP0 (MMU and control) */
static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp64 = tcg_temp_new(TCG_TYPE_I64);
if (sel != 0)
check_insn(env, ctx, ISA_MIPS32);
case 0:
switch (sel) {
case 0:
- gen_op_mfc0_index();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Index";
break;
case 1:
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpecontrol();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_yqmask();
+ tcg_gen_ld_i64(r_tmp64, cpu_env, offsetof(CPUState, CP0_YQMask));
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeschedule();
+ tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeschefback();
+ tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeopt();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- gen_op_mfc0_entrylo0();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EntryLo0";
break;
case 1:
case 3:
switch (sel) {
case 0:
- gen_op_mfc0_entrylo1();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- gen_op_mfc0_context();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "Context";
break;
case 1:
case 5:
switch (sel) {
case 0:
- gen_op_mfc0_pagemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_pagegrain();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_op_mfc0_wired();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf4();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_hwrena();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "HWREna";
break;
default:
case 8:
switch (sel) {
case 0:
- gen_op_mfc0_badvaddr();
- rn = "BadVaddr";
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ rn = "BadVAddr";
break;
default:
goto die;
case 10:
switch (sel) {
case 0:
- gen_op_mfc0_entryhi();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_op_mfc0_compare();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_op_mfc0_status();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_intctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsmap();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSMap";
break;
default:
case 13:
switch (sel) {
case 0:
- gen_op_mfc0_cause();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Cause";
break;
default:
case 14:
switch (sel) {
case 0:
- gen_op_mfc0_epc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "EPC";
break;
default:
case 15:
switch (sel) {
case 0:
- gen_op_mfc0_prid();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_ebase();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_op_mfc0_config0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config";
break;
case 1:
- gen_op_mfc0_config1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config1";
break;
case 2:
- gen_op_mfc0_config2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config2";
break;
case 3:
- gen_op_mfc0_config3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config3";
break;
/* 4,5 are reserved */
/* 6,7 are implementation dependent */
case 6:
- gen_op_mfc0_config6();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config6";
break;
case 7:
- gen_op_mfc0_config7();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config7";
break;
default:
case 20:
switch (sel) {
case 0:
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- gen_op_mfc0_xcontext();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "XContext";
break;
#endif
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mfc0_framemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Framemask";
break;
default:
case 24:
switch (sel) {
case 0:
- gen_op_mfc0_depc(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_op_mfc0_performance0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Performance0";
break;
case 1:
case 2:
case 4:
case 6:
- gen_op_mfc0_taglo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datalo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_op_mfc0_taghi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datahi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- gen_op_mfc0_errorepc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
rn = "ErrorEPC";
break;
default:
case 31:
switch (sel) {
case 0:
- gen_op_mfc0_desave(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DESAVE";
break;
default:
case 0:
switch (sel) {
case 0:
- gen_op_mtc0_index();
+ gen_op_mtc0_index();
rn = "Index";
break;
case 1:
break;
case 8:
/* ignored */
- rn = "BadVaddr";
+ rn = "BadVAddr";
break;
case 9:
switch (sel) {
case 20:
switch (sel) {
case 0:
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
gen_op_mtc0_xcontext();
rn = "XContext";
generate_exception(ctx, EXCP_RI);
}
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
if (sel != 0)
check_insn(env, ctx, ISA_MIPS64);
case 0:
switch (sel) {
case 0:
- gen_op_mfc0_index();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Index";
break;
case 1:
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpecontrol();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_op_dmfc0_yqmask();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_op_dmfc0_vpeschedule();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_op_dmfc0_vpeschefback();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_op_mfc0_vpeopt();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- gen_op_dmfc0_entrylo0();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
rn = "EntryLo0";
break;
case 1:
case 3:
switch (sel) {
case 0:
- gen_op_dmfc0_entrylo1();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- gen_op_dmfc0_context();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
rn = "Context";
break;
case 1:
case 5:
switch (sel) {
case 0:
- gen_op_mfc0_pagemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_pagegrain();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_op_mfc0_wired();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsconf4();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_hwrena();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "HWREna";
break;
default:
case 8:
switch (sel) {
case 0:
- gen_op_dmfc0_badvaddr();
- rn = "BadVaddr";
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ rn = "BadVAddr";
break;
default:
goto die;
case 10:
switch (sel) {
case 0:
- gen_op_dmfc0_entryhi();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_op_mfc0_compare();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_op_mfc0_status();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_intctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsctl();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_srsmap();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "SRSMap";
break;
default:
case 13:
switch (sel) {
case 0:
- gen_op_mfc0_cause();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Cause";
break;
default:
case 14:
switch (sel) {
case 0:
- gen_op_dmfc0_epc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
rn = "EPC";
break;
default:
case 15:
switch (sel) {
case 0:
- gen_op_mfc0_prid();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_op_mfc0_ebase();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_op_mfc0_config0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config";
break;
case 1:
- gen_op_mfc0_config1();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config1";
break;
case 2:
- gen_op_mfc0_config2();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config2";
break;
case 3:
- gen_op_mfc0_config3();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Config3";
break;
/* 6,7 are implementation dependent */
+ case 6:
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
+ rn = "Config6";
+ break;
+ case 7:
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
+ rn = "Config7";
+ break;
default:
goto die;
}
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- gen_op_dmfc0_xcontext();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
rn = "XContext";
break;
default:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_op_mfc0_framemask();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Framemask";
break;
default:
case 24:
switch (sel) {
case 0:
- gen_op_dmfc0_depc(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_op_mfc0_performance0();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "Performance0";
break;
case 1:
case 2:
case 4:
case 6:
- gen_op_mfc0_taglo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datalo();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_op_mfc0_taghi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_op_mfc0_datahi();
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- gen_op_dmfc0_errorepc();
+ tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
case 31:
switch (sel) {
case 0:
- gen_op_mfc0_desave(); /* EJTAG support */
+ /* EJTAG support */
+ tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
+ tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
rn = "DESAVE";
break;
default:
break;
case 8:
/* ignored */
- rn = "BadVaddr";
+ rn = "BadVAddr";
break;
case 9:
switch (sel) {
#endif
generate_exception(ctx, EXCP_RI);
}
-#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
+#endif /* TARGET_MIPS64 */
static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
int u, int sel, int h)
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
(env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
- gen_op_set_T0(-1);
+ tcg_gen_movi_tl(cpu_T[0], -1);
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
- gen_op_set_T0(-1);
+ tcg_gen_movi_tl(cpu_T[0], -1);
else if (u == 0) {
switch (rt) {
case 2:
return;
}
gen_mfc0(env, ctx, rd, ctx->opcode & 0x7);
- gen_op_store_T0_gpr(rt);
+ gen_store_gpr(cpu_T[0], rt);
opn = "mfc0";
break;
case OPC_MTC0:
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
save_cpu_state(ctx, 1);
gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
opn = "mtc0";
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DMFC0:
check_insn(env, ctx, ISA_MIPS3);
if (rt == 0) {
return;
}
gen_dmfc0(env, ctx, rd, ctx->opcode & 0x7);
- gen_op_store_T0_gpr(rt);
+ gen_store_gpr(cpu_T[0], rt);
opn = "dmfc0";
break;
case OPC_DMTC0:
check_insn(env, ctx, ISA_MIPS3);
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
save_cpu_state(ctx, 1);
gen_dmtc0(env, ctx, rd, ctx->opcode & 0x7);
opn = "dmtc0";
}
gen_mftr(env, ctx, rt, (ctx->opcode >> 5) & 1,
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
- gen_op_store_T0_gpr(rd);
+ gen_store_gpr(cpu_T[0], rd);
opn = "mftr";
break;
case OPC_MTTR:
check_insn(env, ctx, ASE_MT);
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1,
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
opn = "mttr";
opn = "bc1tl";
likely:
ctx->hflags |= MIPS_HFLAG_BL;
- gen_op_set_bcond();
- gen_op_save_bcond();
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
break;
case OPC_BC1FANY2:
gen_op_bc1any2f(cc);
opn = "bc1any4t";
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
- gen_op_set_bcond();
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
break;
default:
MIPS_INVAL(opn);
case OPC_MFC1:
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_mfc1();
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
opn = "mfc1";
break;
case OPC_MTC1:
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
gen_op_mtc1();
GEN_STORE_FTN_FREG(fs, WT0);
opn = "mtc1";
break;
case OPC_CFC1:
gen_op_cfc1(fs);
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
opn = "cfc1";
break;
case OPC_CTC1:
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
gen_op_ctc1(fs);
opn = "ctc1";
break;
case OPC_DMFC1:
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_dmfc1();
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
opn = "dmfc1";
break;
case OPC_DMTC1:
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
gen_op_dmtc1();
GEN_STORE_FTN_FREG(fs, DT0);
opn = "dmtc1";
case OPC_MFHC1:
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_mfhc1();
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
opn = "mfhc1";
break;
case OPC_MTHC1:
- GEN_LOAD_REG_TN(T0, rt);
+ gen_load_gpr(cpu_T[0], rt);
gen_op_mthc1();
GEN_STORE_FTN_FREG(fs, WTH0);
opn = "mthc1";
static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
{
+ int l1 = gen_new_label();
uint32_t ccbit;
+ TCGCond cond;
- GEN_LOAD_REG_TN(T0, rd);
- GEN_LOAD_REG_TN(T1, rs);
- if (cc) {
+ if (cc)
ccbit = 1 << (24 + cc);
- } else
+ else
ccbit = 1 << 23;
- if (!tf)
- gen_op_movf(ccbit);
+ if (tf)
+ cond = TCG_COND_EQ;
else
- gen_op_movt(ccbit);
- GEN_STORE_TN_REG(rd, T0);
+ cond = TCG_COND_NE;
+
+ gen_load_gpr(cpu_T[0], rd);
+ gen_load_gpr(cpu_T[1], rs);
+ {
+ TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+
+ tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
+ tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
+ tcg_temp_free(r_ptr);
+ tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
+ tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
+ }
+ tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
+
+ gen_set_label(l1);
+ gen_store_gpr(cpu_T[0], rd);
}
#define GEN_MOVCF(fmt) \
}
GEN_MOVCF(d);
GEN_MOVCF(s);
-GEN_MOVCF(ps);
#undef GEN_MOVCF
static void gen_farith (DisasContext *ctx, uint32_t op1,
opn = "floor.w.s";
break;
case FOP(17, 16):
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
gen_movcf_s(ctx, (ft >> 2) & 0x7, ft & 0x1);
opn = "movcf.s";
break;
case FOP(18, 16):
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
gen_op_float_movz_s();
opn = "movz.s";
break;
case FOP(19, 16):
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
gen_op_float_movn_s();
opn = "movn.s";
break;
case FOP(21, 16):
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_recip_s();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "recip.s";
break;
case FOP(22, 16):
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_rsqrt_s();
GEN_STORE_FTN_FREG(fd, WT2);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
if (ctx->opcode & (1 << 6)) {
- check_cp1_64bitmode(ctx);
+ check_cop1x(ctx);
gen_cmpabs_s(func-48, cc);
opn = condnames_abs[func-48];
} else {
opn = "floor.w.d";
break;
case FOP(17, 17):
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT2, fd);
gen_movcf_d(ctx, (ft >> 2) & 0x7, ft & 0x1);
opn = "movcf.d";
break;
case FOP(18, 17):
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT2, fd);
gen_op_float_movz_d();
opn = "movz.d";
break;
case FOP(19, 17):
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT2, fd);
gen_op_float_movn_d();
opn = "movn.d";
break;
case FOP(21, 17):
- check_cp1_registers(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_recip_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "recip.d";
break;
case FOP(22, 17):
- check_cp1_registers(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_rsqrt_d();
GEN_STORE_FTN_FREG(fd, DT2);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
if (ctx->opcode & (1 << 6)) {
- check_cp1_64bitmode(ctx);
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fs | ft);
gen_cmpabs_d(func-48, cc);
opn = condnames_abs[func-48];
} else {
opn = "cvt.d.l";
break;
case FOP(38, 20):
- case FOP(38, 21):
check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
break;
case FOP(17, 22):
check_cp1_64bitmode(ctx);
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
GEN_LOAD_FREG_FTN(WTH2, fd);
- gen_movcf_ps(ctx, (ft >> 2) & 0x7, ft & 0x1);
+ if (ft & 0x1)
+ gen_op_float_movt_ps ((ft >> 2) & 0x7);
+ else
+ gen_op_float_movf_ps ((ft >> 2) & 0x7);
GEN_STORE_FTN_FREG(fd, WT2);
GEN_STORE_FTN_FREG(fd, WTH2);
opn = "movcf.ps";
break;
case FOP(18, 22):
check_cp1_64bitmode(ctx);
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
break;
case FOP(19, 22):
check_cp1_64bitmode(ctx);
- GEN_LOAD_REG_TN(T0, ft);
+ gen_load_gpr(cpu_T[0], ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
const char *opn = "extended float load/store";
int store = 0;
- /* All of those work only on 64bit FPUs. */
- check_cp1_64bitmode(ctx);
if (base == 0) {
- if (index == 0)
- gen_op_reset_T0();
- else
- GEN_LOAD_REG_TN(T0, index);
+ gen_load_gpr(cpu_T[0], index);
} else if (index == 0) {
- GEN_LOAD_REG_TN(T0, base);
+ gen_load_gpr(cpu_T[0], base);
} else {
- GEN_LOAD_REG_TN(T0, base);
- GEN_LOAD_REG_TN(T1, index);
+ gen_load_gpr(cpu_T[0], base);
+ gen_load_gpr(cpu_T[1], index);
gen_op_addr_add();
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
case OPC_LWXC1:
- op_ldst(lwc1);
+ check_cop1x(ctx);
+ op_ldst_lwc1(ctx);
GEN_STORE_FTN_FREG(fd, WT0);
opn = "lwxc1";
break;
case OPC_LDXC1:
- op_ldst(ldc1);
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd);
+ op_ldst_ldc1(ctx);
GEN_STORE_FTN_FREG(fd, DT0);
opn = "ldxc1";
break;
case OPC_LUXC1:
+ check_cp1_64bitmode(ctx);
op_ldst(luxc1);
GEN_STORE_FTN_FREG(fd, DT0);
opn = "luxc1";
break;
case OPC_SWXC1:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
- op_ldst(swc1);
+ op_ldst_swc1(ctx);
opn = "swxc1";
store = 1;
break;
case OPC_SDXC1:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fs);
GEN_LOAD_FREG_FTN(DT0, fs);
- op_ldst(sdc1);
+ op_ldst_sdc1(ctx);
opn = "sdxc1";
store = 1;
break;
case OPC_SUXC1:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
op_ldst(suxc1);
opn = "suxc1";
{
const char *opn = "flt3_arith";
- /* All of those work only on 64bit FPUs. */
- check_cp1_64bitmode(ctx);
switch (opc) {
case OPC_ALNV_PS:
- GEN_LOAD_REG_TN(T0, fr);
+ check_cp1_64bitmode(ctx);
+ gen_load_gpr(cpu_T[0], fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
gen_op_float_alnv_ps();
opn = "alnv.ps";
break;
case OPC_MADD_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "madd.s";
break;
case OPC_MADD_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "madd.d";
break;
case OPC_MADD_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "madd.ps";
break;
case OPC_MSUB_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "msub.s";
break;
case OPC_MSUB_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "msub.d";
break;
case OPC_MSUB_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "msub.ps";
break;
case OPC_NMADD_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "nmadd.s";
break;
case OPC_NMADD_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "nmadd.d";
break;
case OPC_NMADD_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "nmadd.ps";
break;
case OPC_NMSUB_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "nmsub.s";
break;
case OPC_NMSUB_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "nmsub.d";
break;
case OPC_NMSUB_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
/* MIPS16 extension to MIPS32 */
/* SmartMIPS extension to MIPS32 */
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
/* MDMX extension to MIPS64 */
return;
}
+ /* Handle blikely not taken case */
if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
- int l1;
- /* Handle blikely not taken case */
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
- l1 = gen_new_label();
- gen_op_jnz_T2(l1);
+ tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
+ tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_MULT ... OPC_DIVU:
- gen_muldiv(ctx, op1, rs, rt);
+ if (sa) {
+ check_insn(env, ctx, INSN_VR54XX);
+ op1 = MASK_MUL_VR54XX(ctx->opcode);
+ gen_mul_vr54xx(ctx, op1, rd, rs, rt);
+ } else
+ gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_JR ... OPC_JALR:
gen_compute_branch(ctx, op1, rs, rd, sa);
}
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
/* MIPS64 specific opcodes */
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
}
/* Treat as NOP. */
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DCLZ ... OPC_DCLO:
check_insn(env, ctx, ISA_MIPS64);
check_mips_64(ctx);
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_WSBH:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
gen_op_wsbh();
break;
case OPC_SEB:
- GEN_LOAD_REG_TN(T1, rt);
- gen_op_seb();
+ gen_load_gpr(cpu_T[1], rt);
+ tcg_gen_ext8s_tl(cpu_T[0], cpu_T[1]);
break;
case OPC_SEH:
- GEN_LOAD_REG_TN(T1, rt);
- gen_op_seh();
+ gen_load_gpr(cpu_T[1], rt);
+ tcg_gen_ext16s_tl(cpu_T[0], cpu_T[1]);
break;
default: /* Invalid */
MIPS_INVAL("bshfl");
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rd, T0);
+ gen_store_gpr(cpu_T[0], rd);
break;
case OPC_RDHWR:
check_insn(env, ctx, ISA_MIPS32R2);
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
break;
case OPC_FORK:
check_insn(env, ctx, ASE_MT);
- GEN_LOAD_REG_TN(T0, rt);
- GEN_LOAD_REG_TN(T1, rs);
+ gen_load_gpr(cpu_T[0], rt);
+ gen_load_gpr(cpu_T[1], rs);
gen_op_fork();
break;
case OPC_YIELD:
check_insn(env, ctx, ASE_MT);
- GEN_LOAD_REG_TN(T0, rs);
+ gen_load_gpr(cpu_T[0], rs);
gen_op_yield();
- GEN_STORE_TN_REG(rd, T0);
+ gen_store_gpr(cpu_T[0], rd);
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
check_insn(env, ctx, ISA_MIPS64R2);
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DSBH:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
gen_op_dsbh();
break;
case OPC_DSHD:
- GEN_LOAD_REG_TN(T1, rt);
+ gen_load_gpr(cpu_T[1], rt);
gen_op_dshd();
break;
default: /* Invalid */
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rd, T0);
+ gen_store_gpr(cpu_T[0], rd);
+ break;
#endif
default: /* Invalid */
MIPS_INVAL("special3");
case OPC_MTC0:
case OPC_MFTR:
case OPC_MTTR:
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DMFC0:
case OPC_DMTC0:
#endif
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rt, T0);
+ gen_store_gpr(cpu_T[0], rt);
break;
case OPC_RDPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
- GEN_LOAD_SRSREG_TN(T0, rt);
- GEN_STORE_TN_REG(rd, T0);
+ gen_load_srsgpr(cpu_T[0], rt);
+ gen_store_gpr(cpu_T[0], rd);
break;
case OPC_WRPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
- GEN_LOAD_REG_TN(T0, rt);
- GEN_STORE_TN_SRSREG(rd, T0);
+ gen_load_gpr(cpu_T[0], rt);
+ gen_store_srsgpr(cpu_T[0], rd);
break;
default:
MIPS_INVAL("cp0");
case OPC_CTC1:
gen_cp1(ctx, op1, rt, rd);
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
case OPC_DMFC1:
case OPC_DMTC1:
check_insn(env, ctx, ISA_MIPS3);
#endif
case OPC_BC1ANY2:
case OPC_BC1ANY4:
+ check_cop1x(ctx);
check_insn(env, ctx, ASE_MIPS3D);
/* fall through */
case OPC_BC1:
}
break;
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
+#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
/* Conditional branch */
MIPS_DEBUG("conditional branch");
{
- int l1;
- l1 = gen_new_label();
- gen_op_jnz_T2(l1);
- gen_goto_tb(ctx, 1, ctx->pc + 4);
- gen_set_label(l1);
- gen_goto_tb(ctx, 0, ctx->btarget);
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
+ int l1 = gen_new_label();
+
+ tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
+ tcg_gen_brcondi_tl(TCG_COND_NE, r_tmp, 0, l1);
+ gen_goto_tb(ctx, 1, ctx->pc + 4);
+ gen_set_label(l1);
+ gen_goto_tb(ctx, 0, ctx->btarget);
}
break;
case MIPS_HFLAG_BR:
/* unconditional branch to register */
MIPS_DEBUG("branch to register");
- gen_op_breg();
- gen_op_reset_T0();
- gen_op_exit_tb();
+ gen_breg_pc();
+ tcg_gen_exit_tb(0);
break;
default:
MIPS_DEBUG("unknown branch");
fprintf (logfile, "search pc %d\n", search_pc);
pc_start = tb->pc;
- gen_opc_ptr = gen_opc_buf;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
- gen_opparam_ptr = gen_opparam_buf;
- nb_gen_labels = 0;
ctx.pc = pc_start;
ctx.saved_pc = -1;
ctx.tb = tb;
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
restore_cpu_state(env, &ctx);
#if defined(CONFIG_USER_ONLY)
- ctx.mem_idx = 0;
+ ctx.mem_idx = MIPS_HFLAG_UM;
#else
- ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
+ ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
#endif
#ifdef DEBUG_DISAS
if (loglevel & CPU_LOG_TB_CPU) {
#endif
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
- fprintf(logfile, "\ntb %p super %d cond %04x\n",
+ fprintf(logfile, "\ntb %p idx %d hflags %04x\n",
tb, ctx.mem_idx, ctx.hflags);
#endif
while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
} else {
switch (ctx.bstate) {
case BS_STOP:
- gen_op_interrupt_restart();
+ tcg_gen_helper_0_0(do_interrupt_restart);
gen_goto_tb(&ctx, 0, ctx.pc);
break;
case BS_NONE:
gen_goto_tb(&ctx, 0, ctx.pc);
break;
case BS_EXCP:
- gen_op_interrupt_restart();
- gen_op_reset_T0();
- gen_op_exit_tb();
+ tcg_gen_helper_0_0(do_interrupt_restart);
+ tcg_gen_exit_tb(0);
break;
case BS_BRANCH:
default:
target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
fprintf(logfile, "\n");
}
- if (loglevel & CPU_LOG_TB_OP) {
- fprintf(logfile, "OP:\n");
- dump_ops(gen_opc_buf, gen_opparam_buf);
- fprintf(logfile, "\n");
- }
if (loglevel & CPU_LOG_TB_CPU) {
fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
}
void dump_fpu (CPUState *env)
{
if (loglevel) {
- fprintf(logfile, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
- env->PC[env->current_tc], env->HI[0][env->current_tc], env->LO[0][env->current_tc], env->hflags, env->btarget, env->bcond);
+ fprintf(logfile,
+ "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
+ " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx
+ " %04x\n",
+ env->PC[env->current_tc], env->HI[env->current_tc][0],
+ env->LO[env->current_tc][0], env->hflags, env->btarget,
+ env->bcond);
fpu_dump_state(env, logfile, fprintf, 0);
}
}
-#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
/* Debug help: The architecture requires 32bit code to maintain proper
sign-extened values on 64bit machines. */
if (!SIGN_EXT_P(env->PC[env->current_tc]))
cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->PC[env->current_tc]);
- if (!SIGN_EXT_P(env->HI[env->current_tc]))
- cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI[env->current_tc]);
- if (!SIGN_EXT_P(env->LO[env->current_tc]))
- cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO[env->current_tc]);
+ if (!SIGN_EXT_P(env->HI[env->current_tc][0]))
+ cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI[env->current_tc][0]);
+ if (!SIGN_EXT_P(env->LO[env->current_tc][0]))
+ cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO[env->current_tc][0]);
if (!SIGN_EXT_P(env->btarget))
cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget);
for (i = 0; i < 32; i++) {
- if (!SIGN_EXT_P(env->gpr[i][env->current_tc]))
- cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[i][env->current_tc]);
+ if (!SIGN_EXT_P(env->gpr[env->current_tc][i]))
+ cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[env->current_tc][i]);
}
if (!SIGN_EXT_P(env->CP0_EPC))
for (i = 0; i < 32; i++) {
if ((i & 3) == 0)
cpu_fprintf(f, "GPR%02d:", i);
- cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i][env->current_tc]);
+ cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[env->current_tc][i]);
if ((i & 3) == 3)
cpu_fprintf(f, "\n");
}
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
if (env->hflags & MIPS_HFLAG_FPU)
fpu_dump_state(env, f, cpu_fprintf, flags);
-#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
#endif
}
-CPUMIPSState *cpu_mips_init (void)
+static void mips_tcg_init(void)
+{
+ static int inited;
+
+ /* Initialize various static tables. */
+ if (inited)
+ return;
+
+ cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
+ current_tc_gprs = tcg_global_mem_new(TCG_TYPE_PTR,
+ TCG_AREG0,
+ offsetof(CPUState, current_tc_gprs),
+ "current_tc_gprs");
+ current_tc_hi = tcg_global_mem_new(TCG_TYPE_PTR,
+ TCG_AREG0,
+ offsetof(CPUState, current_tc_hi),
+ "current_tc_hi");
+#if TARGET_LONG_BITS > HOST_LONG_BITS
+ cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, t0), "T0");
+ cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, t1), "T1");
+#else
+ cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
+ cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
+#endif
+
+ inited = 1;
+}
+
+#include "translate_init.c"
+
+CPUMIPSState *cpu_mips_init (const char *cpu_model)
{
CPUMIPSState *env;
+ const mips_def_t *def;
+ def = cpu_mips_find_by_name(cpu_model);
+ if (!def)
+ return NULL;
env = qemu_mallocz(sizeof(CPUMIPSState));
if (!env)
return NULL;
+ env->cpu_model = def;
+
cpu_exec_init(env);
+ env->cpu_model_str = cpu_model;
+ mips_tcg_init();
cpu_reset(env);
return env;
}
#else
env->hflags = MIPS_HFLAG_CP0;
#endif
+ cpu_mips_register(env, env->cpu_model);
}
-#include "translate_init.c"
+void gen_pc_load(CPUState *env, TranslationBlock *tb,
+ unsigned long searched_pc, int pc_pos, void *puc)
+{
+ env->PC[env->current_tc] = gen_opc_pc[pc_pos];
+ env->hflags &= ~MIPS_HFLAG_BMASK;
+ env->hflags |= gen_opc_hflags[pc_pos];
+}
projects / qemu.git / blobdiff