*
* Copyright (c) 2006 Fabrice Bellard
*
+ * Modifications:
+ * 2010-Feb-14 Artyom Tarasenko : reworked irq generation
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
-/* debug DMA */
-//#define DEBUG_DMA
+#include "hw.h"
+#include "sparc32_dma.h"
+#include "sun4m.h"
+#include "sysbus.h"
+#include "trace.h"
/*
* This is the DMA controller part of chip STP2000 (Master I/O), also
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
*/
-#ifdef DEBUG_DMA
-#define DPRINTF(fmt, args...) \
-do { printf("DMA: " fmt , ##args); } while (0)
-#else
-#define DPRINTF(fmt, args...)
-#endif
-
#define DMA_REGS 4
#define DMA_SIZE (4 * sizeof(uint32_t))
-#define DMA_MAXADDR (DMA_SIZE - 1)
+/* We need the mask, because one instance of the device is not page
+ aligned (ledma, start address 0x0010) */
+#define DMA_MASK (DMA_SIZE - 1)
+/* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
+#define DMA_ETH_SIZE (8 * sizeof(uint32_t))
+#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
#define DMA_VER 0xa0000000
#define DMA_INTR 1
#define DMA_INTREN 0x10
#define DMA_WRITE_MEM 0x100
+#define DMA_EN 0x200
#define DMA_LOADED 0x04000000
#define DMA_DRAIN_FIFO 0x40
#define DMA_RESET 0x80
+/* XXX SCSI and ethernet should have different read-only bit masks */
+#define DMA_CSR_RO_MASK 0xfe000007
+
typedef struct DMAState DMAState;
struct DMAState {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t dmaregs[DMA_REGS];
qemu_irq irq;
- void *iommu, *dev_opaque;
- void (*dev_reset)(void *dev_opaque);
- qemu_irq *pic;
+ void *iommu;
+ qemu_irq gpio[2];
+ uint32_t is_ledma;
+};
+
+enum {
+ GPIO_RESET = 0,
+ GPIO_DMA,
};
/* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
int i;
- DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
addr |= s->dmaregs[3];
+ trace_ledma_memory_read(addr);
if (do_bswap) {
sparc_iommu_memory_read(s->iommu, addr, buf, len);
} else {
}
}
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
int l, i;
uint16_t tmp_buf[32];
- DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
addr |= s->dmaregs[3];
+ trace_ledma_memory_write(addr);
if (do_bswap) {
sparc_iommu_memory_write(s->iommu, addr, buf, len);
} else {
{
DMAState *s = opaque;
if (level) {
- DPRINTF("Raise ESP IRQ\n");
s->dmaregs[0] |= DMA_INTR;
- qemu_irq_raise(s->irq);
+ if (s->dmaregs[0] & DMA_INTREN) {
+ trace_sparc32_dma_set_irq_raise();
+ qemu_irq_raise(s->irq);
+ }
} else {
- s->dmaregs[0] &= ~DMA_INTR;
- DPRINTF("Lower ESP IRQ\n");
- qemu_irq_lower(s->irq);
+ if (s->dmaregs[0] & DMA_INTR) {
+ s->dmaregs[0] &= ~DMA_INTR;
+ if (s->dmaregs[0] & DMA_INTREN) {
+ trace_sparc32_dma_set_irq_lower();
+ qemu_irq_lower(s->irq);
+ }
+ }
}
}
{
DMAState *s = opaque;
- DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
+ trace_espdma_memory_read(s->dmaregs[1]);
sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
- s->dmaregs[0] |= DMA_INTR;
s->dmaregs[1] += len;
}
{
DMAState *s = opaque;
- DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
- s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
+ trace_espdma_memory_write(s->dmaregs[1]);
sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
- s->dmaregs[0] |= DMA_INTR;
s->dmaregs[1] += len;
}
-static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t dma_mem_read(void *opaque, hwaddr addr,
+ unsigned size)
{
DMAState *s = opaque;
uint32_t saddr;
- saddr = (addr & DMA_MAXADDR) >> 2;
- DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
- s->dmaregs[saddr]);
-
+ if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
+ /* aliased to espdma, but we can't get there from here */
+ /* buggy driver if using undocumented behavior, just return 0 */
+ trace_sparc32_dma_mem_readl(addr, 0);
+ return 0;
+ }
+ saddr = (addr & DMA_MASK) >> 2;
+ trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
return s->dmaregs[saddr];
}
-static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dma_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
{
DMAState *s = opaque;
uint32_t saddr;
- saddr = (addr & DMA_MAXADDR) >> 2;
- DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
- s->dmaregs[saddr], val);
+ if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
+ /* aliased to espdma, but we can't get there from here */
+ trace_sparc32_dma_mem_writel(addr, 0, val);
+ return;
+ }
+ saddr = (addr & DMA_MASK) >> 2;
+ trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
switch (saddr) {
case 0:
- if (!(val & DMA_INTREN)) {
- DPRINTF("Lower IRQ\n");
- qemu_irq_lower(s->irq);
+ if (val & DMA_INTREN) {
+ if (s->dmaregs[0] & DMA_INTR) {
+ trace_sparc32_dma_set_irq_raise();
+ qemu_irq_raise(s->irq);
+ }
+ } else {
+ if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
+ trace_sparc32_dma_set_irq_lower();
+ qemu_irq_lower(s->irq);
+ }
}
if (val & DMA_RESET) {
- s->dev_reset(s->dev_opaque);
+ qemu_irq_raise(s->gpio[GPIO_RESET]);
+ qemu_irq_lower(s->gpio[GPIO_RESET]);
} else if (val & DMA_DRAIN_FIFO) {
val &= ~DMA_DRAIN_FIFO;
} else if (val == 0)
val = DMA_DRAIN_FIFO;
- val &= 0x0fffffff;
+
+ if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
+ trace_sparc32_dma_enable_raise();
+ qemu_irq_raise(s->gpio[GPIO_DMA]);
+ } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
+ trace_sparc32_dma_enable_lower();
+ qemu_irq_lower(s->gpio[GPIO_DMA]);
+ }
+
+ val &= ~DMA_CSR_RO_MASK;
val |= DMA_VER;
+ s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
break;
case 1:
s->dmaregs[0] |= DMA_LOADED;
- break;
+ /* fall through */
default:
+ s->dmaregs[saddr] = val;
break;
}
- s->dmaregs[saddr] = val;
}
-static CPUReadMemoryFunc *dma_mem_read[3] = {
- dma_mem_readl,
- dma_mem_readl,
- dma_mem_readl,
-};
-
-static CPUWriteMemoryFunc *dma_mem_write[3] = {
- dma_mem_writel,
- dma_mem_writel,
- dma_mem_writel,
+static const MemoryRegionOps dma_mem_ops = {
+ .read = dma_mem_read,
+ .write = dma_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static void dma_reset(void *opaque)
+static void dma_reset(DeviceState *d)
{
- DMAState *s = opaque;
+ DMAState *s = container_of(d, DMAState, busdev.qdev);
memset(s->dmaregs, 0, DMA_SIZE);
s->dmaregs[0] = DMA_VER;
}
-static void dma_save(QEMUFile *f, void *opaque)
+static const VMStateDescription vmstate_dma = {
+ .name ="sparc32_dma",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .minimum_version_id_old = 2,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static int sparc32_dma_init1(SysBusDevice *dev)
{
- DMAState *s = opaque;
- unsigned int i;
+ DMAState *s = FROM_SYSBUS(DMAState, dev);
+ int reg_size;
- for (i = 0; i < DMA_REGS; i++)
- qemu_put_be32s(f, &s->dmaregs[i]);
-}
+ sysbus_init_irq(dev, &s->irq);
-static int dma_load(QEMUFile *f, void *opaque, int version_id)
-{
- DMAState *s = opaque;
- unsigned int i;
+ reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
+ memory_region_init_io(&s->iomem, &dma_mem_ops, s, "dma", reg_size);
+ sysbus_init_mmio(dev, &s->iomem);
- if (version_id != 2)
- return -EINVAL;
- for (i = 0; i < DMA_REGS; i++)
- qemu_get_be32s(f, &s->dmaregs[i]);
+ qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
+ qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
return 0;
}
-void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
- void *iommu, qemu_irq **dev_irq)
-{
- DMAState *s;
- int dma_io_memory;
-
- s = qemu_mallocz(sizeof(DMAState));
- if (!s)
- return NULL;
-
- s->irq = parent_irq;
- s->iommu = iommu;
-
- dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
- cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
+static Property sparc32_dma_properties[] = {
+ DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
+ DEFINE_PROP_UINT32("is_ledma", DMAState, is_ledma, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
- register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
- qemu_register_reset(dma_reset, s);
- *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
+static void sparc32_dma_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- return s;
+ k->init = sparc32_dma_init1;
+ dc->reset = dma_reset;
+ dc->vmsd = &vmstate_dma;
+ dc->props = sparc32_dma_properties;
}
-void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
- void *dev_opaque)
-{
- DMAState *s = opaque;
+static const TypeInfo sparc32_dma_info = {
+ .name = "sparc32_dma",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(DMAState),
+ .class_init = sparc32_dma_class_init,
+};
- s->dev_reset = dev_reset;
- s->dev_opaque = dev_opaque;
+static void sparc32_dma_register_types(void)
+{
+ type_register_static(&sparc32_dma_info);
}
+
+type_init(sparc32_dma_register_types)
projects / qemu.git / blobdiff