#include "pc.h"
#include "isa.h"
#include "fw_cfg.h"
+#include "escc.h"
//#define DEBUG_IRQ
#define MAX_CPUS 16
#define MAX_PILS 16
+#define ESCC_CLOCK 4915200
+
struct sun4m_hwdef {
target_phys_addr_t iommu_base, slavio_base;
target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
{
}
-static int nvram_boot_set(void *opaque, const char *boot_device)
+static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
- unsigned int i;
- uint8_t image[sizeof(ohwcfg_v3_t)];
- ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
- m48t59_t *nvram = (m48t59_t *)opaque;
-
- for (i = 0; i < sizeof(image); i++)
- image[i] = m48t59_read(nvram, i) & 0xff;
-
- pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
- boot_device);
- header->nboot_devices = strlen(boot_device) & 0xff;
- header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
-
- for (i = 0; i < sizeof(image); i++)
- m48t59_write(nvram, i, image[i]);
-
+ fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
return 0;
}
unsigned int i;
uint32_t start, end;
uint8_t image[0x1ff0];
- ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
- struct sparc_arch_cfg *sparc_header;
struct OpenBIOS_nvpart_v1 *part_header;
memset(image, '\0', sizeof(image));
- // Try to match PPC NVRAM
- pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
- "QEMU_BIOS");
- header->struct_version = cpu_to_be32(3); /* structure v3 */
-
- header->nvram_size = cpu_to_be16(0x2000);
- header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
- header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
- pstrcpy((char *)header->arch, sizeof(header->arch), arch);
- header->nb_cpus = smp_cpus & 0xff;
- header->RAM0_base = 0;
- header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
- pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
- boot_devices);
- header->nboot_devices = strlen(boot_devices) & 0xff;
- header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
- header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
- if (cmdline) {
- pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
- header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
- header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
- }
- // XXX add initrd_image, initrd_size
- header->width = cpu_to_be16(width);
- header->height = cpu_to_be16(height);
- header->depth = cpu_to_be16(depth);
- if (nographic)
- header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
-
- header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
-
- // Architecture specific header
- start = sizeof(ohwcfg_v3_t);
- sparc_header = (struct sparc_arch_cfg *)&image[start];
- sparc_header->valid = 0;
- start += sizeof(struct sparc_arch_cfg);
+ start = 0;
// OpenBIOS nvram variables
// Variable partition
for (i = 0; i < sizeof(image); i++)
m48t59_write(nvram, i, image[i]);
-
- qemu_register_boot_set(nvram_boot_set, nvram);
}
static void *slavio_intctl;
-void pic_info(void)
+void pic_info(Monitor *mon)
{
if (slavio_intctl)
- slavio_pic_info(slavio_intctl);
+ slavio_pic_info(mon, slavio_intctl);
}
-void irq_info(void)
+void irq_info(Monitor *mon)
{
if (slavio_intctl)
- slavio_irq_info(slavio_intctl);
+ slavio_irq_info(mon, slavio_intctl);
}
void cpu_check_irqs(CPUState *env)
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
qemu_irq *esp_reset, *le_reset;
qemu_irq *fdc_tc;
qemu_irq *cpu_halt;
- ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset;
+ ram_addr_t ram_offset, prom_offset, idreg_offset;
unsigned long kernel_size;
int ret;
char buf[1024];
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
- tcx_offset = qemu_ram_alloc(hwdef->vram_size);
- tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
- hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
-
- if (nd_table[0].model == NULL)
- nd_table[0].model = "lance";
- if (strcmp(nd_table[0].model, "lance") == 0) {
- lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
- } else if (strcmp(nd_table[0].model, "?") == 0) {
- fprintf(stderr, "qemu: Supported NICs: lance\n");
- exit (1);
- } else {
- fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
- exit (1);
- }
+ tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
+ graphic_depth);
+
+ lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 8);
slavio_cpu_irq, smp_cpus);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
- nographic);
+ nographic, ESCC_CLOCK, 1);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
- slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
- serial_hds[1], serial_hds[0]);
+ escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
+ serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ if (kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
enum {
/* SPARCstation 5 hardware initialisation */
static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation 10 hardware initialisation */
static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCserver 600MP hardware initialisation */
static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation 20 hardware initialisation */
static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation Voyager hardware initialisation */
static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation LX hardware initialisation */
static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation 4 hardware initialisation */
static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCClassic hardware initialisation */
static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCbook hardware initialisation */
static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
.desc = "Sun4m platform, SPARCstation 5",
.init = ss5_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
};
.desc = "Sun4m platform, SPARCstation 10",
.init = ss10_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
.max_cpus = 4,
};
.desc = "Sun4m platform, SPARCserver 600MP",
.init = ss600mp_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
.max_cpus = 4,
};
.desc = "Sun4m platform, SPARCstation 20",
.init = ss20_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
.max_cpus = 4,
};
.desc = "Sun4m platform, SPARCstation Voyager",
.init = vger_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
};
.desc = "Sun4m platform, SPARCstation LX",
.init = ss_lx_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
};
.desc = "Sun4m platform, SPARCstation 4",
.init = ss4_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
};
.desc = "Sun4m platform, SPARCClassic",
.init = scls_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
};
.desc = "Sun4m platform, SPARCbook",
.init = sbook_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
};
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
*espdma_irq, *ledma_irq;
qemu_irq *esp_reset, *le_reset;
- ram_addr_t ram_offset, prom_offset, tcx_offset;
+ ram_addr_t ram_offset, prom_offset;
unsigned long kernel_size;
int ret;
char buf[1024];
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
- tcx_offset = qemu_ram_alloc(hwdef->vram_size);
- tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
- hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
-
- if (nd_table[0].model == NULL)
- nd_table[0].model = "lance";
- if (strcmp(nd_table[0].model, "lance") == 0) {
- lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
- } else if (strcmp(nd_table[0].model, "?") == 0) {
- fprintf(stderr, "qemu: Supported NICs: lance\n");
- exit (1);
- } else {
- fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
- exit (1);
- }
+ tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
+ graphic_depth);
+
+ lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 8);
sbi_cpu_irq, smp_cpus);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
- nographic);
+ nographic, ESCC_CLOCK, 1);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
- slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
- serial_hds[1], serial_hds[0]);
+ escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
+ serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
if (drive_get_max_bus(IF_SCSI) > 0) {
fprintf(stderr, "qemu: too many SCSI bus\n");
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ if (kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCserver 1000 hardware initialisation */
static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
+ sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCcenter 2000 hardware initialisation */
static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
+ sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
.desc = "Sun4d platform, SPARCserver 1000",
.init = ss1000_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
.max_cpus = 8,
};
.desc = "Sun4d platform, SPARCcenter 2000",
.init = ss2000_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
.max_cpus = 20,
};
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
qemu_irq *esp_reset, *le_reset;
qemu_irq *fdc_tc;
- ram_addr_t ram_offset, prom_offset, tcx_offset;
+ ram_addr_t ram_offset, prom_offset;
unsigned long kernel_size;
int ret;
char buf[1024];
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
- tcx_offset = qemu_ram_alloc(hwdef->vram_size);
- tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
- hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
-
- if (nd_table[0].model == NULL)
- nd_table[0].model = "lance";
- if (strcmp(nd_table[0].model, "lance") == 0) {
- lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
- } else if (strcmp(nd_table[0].model, "?") == 0) {
- fprintf(stderr, "qemu: Supported NICs: lance\n");
- exit (1);
- } else {
- fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
- exit (1);
- }
+ tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
+ graphic_depth);
+
+ lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 2);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
- nographic);
+ nographic, ESCC_CLOCK, 1);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
- slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
- serial_hds[1], serial_hds[0]);
+ escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
+ slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
+ ESCC_CLOCK, 1);
slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ if (kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCstation 2 hardware initialisation */
static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
+ sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
.desc = "Sun4c platform, SPARCstation 2",
.init = ss2_init,
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
- .nodisk_ok = 1,
.use_scsi = 1,
};
projects / qemu.git / blobdiff