qxl/update_area_io: guest_bug on invalid parameters

[qemu.git] / hw / mac_nvram.c

diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
index c1281c33df807d25e7d1a9fc28873452817499bb..ed0a2b7ef2597b99a0353b2df368815ddac01362 100644 (file)
--- a/hw/mac_nvram.c
+++ b/hw/mac_nvram.c
@@ -31,15 +31,16 @@
 //#define DEBUG_NVR
 
 #ifdef DEBUG_NVR
-#define NVR_DPRINTF(fmt, args...) \
-do { printf("NVR: " fmt , ##args); } while (0)
+#define NVR_DPRINTF(fmt, ...)                                   \
+    do { printf("NVR: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define NVR_DPRINTF(fmt, args...)
+#define NVR_DPRINTF(fmt, ...)
 #endif
 
 struct MacIONVRAMState {
-    target_phys_addr_t size;
-    int mem_index;
+    uint32_t size;
+    MemoryRegion mem;
+    unsigned int it_shift;
     uint8_t *data;
 };
 
@@ -70,72 +71,73 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
 }
 
 /* macio style NVRAM device */
-static void macio_nvram_writeb (void *opaque,
-                                target_phys_addr_t addr, uint32_t value)
+static void macio_nvram_writeb(void *opaque, target_phys_addr_t addr,
+                               uint64_t value, unsigned size)
 {
     MacIONVRAMState *s = opaque;
 
-    addr = (addr >> 4) & (s->size - 1);
+    addr = (addr >> s->it_shift) & (s->size - 1);
     s->data[addr] = value;
     NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
 }
 
-static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
+static uint64_t macio_nvram_readb(void *opaque, target_phys_addr_t addr,
+                                  unsigned size)
 {
     MacIONVRAMState *s = opaque;
     uint32_t value;
 
-    addr = (addr >> 4) & (s->size - 1);
+    addr = (addr >> s->it_shift) & (s->size - 1);
     value = s->data[addr];
     NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
 
     return value;
 }
 
-static CPUWriteMemoryFunc *nvram_write[] = {
-    &macio_nvram_writeb,
-    &macio_nvram_writeb,
-    &macio_nvram_writeb,
+static const MemoryRegionOps macio_nvram_ops = {
+    .read = macio_nvram_readb,
+    .write = macio_nvram_writeb,
+    .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static CPUReadMemoryFunc *nvram_read[] = {
-    &macio_nvram_readb,
-    &macio_nvram_readb,
-    &macio_nvram_readb,
+static const VMStateDescription vmstate_macio_nvram = {
+    .name = "macio_nvram",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_VBUFFER_UINT32(data, MacIONVRAMState, 0, NULL, 0, size),
+        VMSTATE_END_OF_LIST()
+    }
 };
 
+
 static void macio_nvram_reset(void *opaque)
 {
 }
 
-MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
+MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
+                                   unsigned int it_shift)
 {
     MacIONVRAMState *s;
 
-    s = qemu_mallocz(sizeof(MacIONVRAMState));
-    if (!s)
-        return NULL;
-    s->data = qemu_mallocz(size);
-    if (!s->data) {
-        qemu_free(s);
-       return NULL;
-    }
+    s = g_malloc0(sizeof(MacIONVRAMState));
+    s->data = g_malloc0(size);
     s->size = size;
+    s->it_shift = it_shift;
 
-    s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
-    *mem_index = s->mem_index;
+    memory_region_init_io(&s->mem, &macio_nvram_ops, s, "macio-nvram",
+                          size << it_shift);
+    vmstate_register(NULL, -1, &vmstate_macio_nvram, s);
     qemu_register_reset(macio_nvram_reset, s);
-    macio_nvram_reset(s);
 
     return s;
 }
 
-void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
+void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
+                           target_phys_addr_t mem_base)
 {
-    MacIONVRAMState *s;
-
-    s = opaque;
-    cpu_register_physical_memory(mem_base, s->size << 4, s->mem_index);
+    memory_region_add_subregion(bar, mem_base, &s->mem);
 }
 
 /* Set up a system OpenBIOS NVRAM partition */