#include "elf.h"
#include "exec/log.h"
#include "trace/control.h"
-#include "glib-compat.h"
+#include "target_elf.h"
char *exec_path;
} \
} while (0)
-#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
/*
* When running 32-on-64 we should make sure we can fit all of the possible
* guest address space into a contiguous chunk of virtual host memory.
*
* This way we will never overlap with our own libraries or binaries or stack
* or anything else that QEMU maps.
+ *
+ * Many cpus reserve the high bit (or more than one for some 64-bit cpus)
+ * of the address for the kernel. Some cpus rely on this and user space
+ * uses the high bit(s) for pointer tagging and the like. For them, we
+ * must preserve the expected address space.
*/
-# ifdef TARGET_MIPS
-/* MIPS only supports 31 bits of virtual address space for user space */
-unsigned long reserved_va = 0x77000000;
+#ifndef MAX_RESERVED_VA
+# if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
+# if TARGET_VIRT_ADDR_SPACE_BITS == 32 && \
+ (TARGET_LONG_BITS == 32 || defined(TARGET_ABI32))
+/* There are a number of places where we assign reserved_va to a variable
+ of type abi_ulong and expect it to fit. Avoid the last page. */
+# define MAX_RESERVED_VA (0xfffffffful & TARGET_PAGE_MASK)
+# else
+# define MAX_RESERVED_VA (1ul << TARGET_VIRT_ADDR_SPACE_BITS)
+# endif
# else
-unsigned long reserved_va = 0xf7000000;
+# define MAX_RESERVED_VA 0
# endif
+#endif
+
+/* That said, reserving *too* much vm space via mmap can run into problems
+ with rlimits, oom due to page table creation, etc. We will still try it,
+ if directed by the command-line option, but not by default. */
+#if HOST_LONG_BITS == 64 && TARGET_VIRT_ADDR_SPACE_BITS <= 32
+unsigned long reserved_va = MAX_RESERVED_VA;
#else
unsigned long reserved_va;
#endif
/***********************************************************/
/* Helper routines for implementing atomic operations. */
-/* To implement exclusive operations we force all cpus to syncronise.
- We don't require a full sync, only that no cpus are executing guest code.
- The alternative is to map target atomic ops onto host equivalents,
- which requires quite a lot of per host/target work. */
-static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
-static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
-static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
-static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
-static int pending_cpus;
-
/* Make sure everything is in a consistent state for calling fork(). */
void fork_start(void)
{
- qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
- pthread_mutex_lock(&exclusive_lock);
+ start_exclusive();
mmap_fork_start();
+ qemu_mutex_lock(&tb_ctx.tb_lock);
+ cpu_list_lock();
}
void fork_end(int child)
QTAILQ_REMOVE(&cpus, cpu, node);
}
}
- pending_cpus = 0;
- pthread_mutex_init(&exclusive_lock, NULL);
- pthread_mutex_init(&cpu_list_mutex, NULL);
- pthread_cond_init(&exclusive_cond, NULL);
- pthread_cond_init(&exclusive_resume, NULL);
- qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
+ qemu_mutex_init(&tb_ctx.tb_lock);
+ qemu_init_cpu_list();
gdbserver_fork(thread_cpu);
+ /* qemu_init_cpu_list() takes care of reinitializing the
+ * exclusive state, so we don't need to end_exclusive() here.
+ */
} else {
- pthread_mutex_unlock(&exclusive_lock);
- qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
- }
-}
-
-/* Wait for pending exclusive operations to complete. The exclusive lock
- must be held. */
-static inline void exclusive_idle(void)
-{
- while (pending_cpus) {
- pthread_cond_wait(&exclusive_resume, &exclusive_lock);
- }
-}
-
-/* Start an exclusive operation.
- Must only be called from outside cpu_exec. */
-static inline void start_exclusive(void)
-{
- CPUState *other_cpu;
-
- pthread_mutex_lock(&exclusive_lock);
- exclusive_idle();
-
- pending_cpus = 1;
- /* Make all other cpus stop executing. */
- CPU_FOREACH(other_cpu) {
- if (other_cpu->running) {
- pending_cpus++;
- cpu_exit(other_cpu);
- }
- }
- if (pending_cpus > 1) {
- pthread_cond_wait(&exclusive_cond, &exclusive_lock);
- }
-}
-
-/* Finish an exclusive operation. */
-static inline void __attribute__((unused)) end_exclusive(void)
-{
- pending_cpus = 0;
- pthread_cond_broadcast(&exclusive_resume);
- pthread_mutex_unlock(&exclusive_lock);
-}
-
-/* Wait for exclusive ops to finish, and begin cpu execution. */
-static inline void cpu_exec_start(CPUState *cpu)
-{
- pthread_mutex_lock(&exclusive_lock);
- exclusive_idle();
- cpu->running = true;
- pthread_mutex_unlock(&exclusive_lock);
-}
-
-/* Mark cpu as not executing, and release pending exclusive ops. */
-static inline void cpu_exec_end(CPUState *cpu)
-{
- pthread_mutex_lock(&exclusive_lock);
- cpu->running = false;
- if (pending_cpus > 1) {
- pending_cpus--;
- if (pending_cpus == 1) {
- pthread_cond_signal(&exclusive_cond);
- }
+ qemu_mutex_unlock(&tb_ctx.tb_lock);
+ cpu_list_unlock();
+ end_exclusive();
}
- exclusive_idle();
- pthread_mutex_unlock(&exclusive_lock);
-}
-
-void cpu_list_lock(void)
-{
- pthread_mutex_lock(&cpu_list_mutex);
-}
-
-void cpu_list_unlock(void)
-{
- pthread_mutex_unlock(&cpu_list_mutex);
}
-
#ifdef TARGET_I386
/***********************************************************/
/* CPUX86 core interface */
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch(trapnr) {
case 0x80:
/* linux syscall from int $0x80 */
}
}
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
pc = env->segs[R_CS].base + env->eip;
EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
return 0;
}
-/* Store exclusive handling for AArch32 */
-static int do_strex(CPUARMState *env)
-{
- uint64_t val;
- int size;
- int rc = 1;
- int segv = 0;
- uint32_t addr;
- start_exclusive();
- if (env->exclusive_addr != env->exclusive_test) {
- goto fail;
- }
- /* We know we're always AArch32 so the address is in uint32_t range
- * unless it was the -1 exclusive-monitor-lost value (which won't
- * match exclusive_test above).
- */
- assert(extract64(env->exclusive_addr, 32, 32) == 0);
- addr = env->exclusive_addr;
- size = env->exclusive_info & 0xf;
- switch (size) {
- case 0:
- segv = get_user_u8(val, addr);
- break;
- case 1:
- segv = get_user_data_u16(val, addr, env);
- break;
- case 2:
- case 3:
- segv = get_user_data_u32(val, addr, env);
- break;
- default:
- abort();
- }
- if (segv) {
- env->exception.vaddress = addr;
- goto done;
- }
- if (size == 3) {
- uint32_t valhi;
- segv = get_user_data_u32(valhi, addr + 4, env);
- if (segv) {
- env->exception.vaddress = addr + 4;
- goto done;
- }
- if (arm_cpu_bswap_data(env)) {
- val = deposit64((uint64_t)valhi, 32, 32, val);
- } else {
- val = deposit64(val, 32, 32, valhi);
- }
- }
- if (val != env->exclusive_val) {
- goto fail;
- }
-
- val = env->regs[(env->exclusive_info >> 8) & 0xf];
- switch (size) {
- case 0:
- segv = put_user_u8(val, addr);
- break;
- case 1:
- segv = put_user_data_u16(val, addr, env);
- break;
- case 2:
- case 3:
- segv = put_user_data_u32(val, addr, env);
- break;
- }
- if (segv) {
- env->exception.vaddress = addr;
- goto done;
- }
- if (size == 3) {
- val = env->regs[(env->exclusive_info >> 12) & 0xf];
- segv = put_user_data_u32(val, addr + 4, env);
- if (segv) {
- env->exception.vaddress = addr + 4;
- goto done;
- }
- }
- rc = 0;
-fail:
- env->regs[15] += 4;
- env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
-done:
- end_exclusive();
- return segv;
-}
-
void cpu_loop(CPUARMState *env)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch(trapnr) {
case EXCP_UDEF:
+ case EXCP_NOCP:
+ case EXCP_INVSTATE:
{
TaskState *ts = cs->opaque;
uint32_t opcode;
}
}
break;
+ case EXCP_SEMIHOST:
+ env->regs[0] = do_arm_semihosting(env);
+ break;
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
- case EXCP_STREX:
- if (!do_strex(env)) {
- break;
- }
- /* fall through for segv */
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
addr = env->exception.vaddress;
case EXCP_YIELD:
/* nothing to do here for user-mode, just resume guest code */
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
error:
EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
#else
-/*
- * Handle AArch64 store-release exclusive
- *
- * rs = gets the status result of store exclusive
- * rt = is the register that is stored
- * rt2 = is the second register store (in STP)
- *
- */
-static int do_strex_a64(CPUARMState *env)
-{
- uint64_t val;
- int size;
- bool is_pair;
- int rc = 1;
- int segv = 0;
- uint64_t addr;
- int rs, rt, rt2;
-
- start_exclusive();
- /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
- size = extract32(env->exclusive_info, 0, 2);
- is_pair = extract32(env->exclusive_info, 2, 1);
- rs = extract32(env->exclusive_info, 4, 5);
- rt = extract32(env->exclusive_info, 9, 5);
- rt2 = extract32(env->exclusive_info, 14, 5);
-
- addr = env->exclusive_addr;
-
- if (addr != env->exclusive_test) {
- goto finish;
- }
-
- switch (size) {
- case 0:
- segv = get_user_u8(val, addr);
- break;
- case 1:
- segv = get_user_u16(val, addr);
- break;
- case 2:
- segv = get_user_u32(val, addr);
- break;
- case 3:
- segv = get_user_u64(val, addr);
- break;
- default:
- abort();
- }
- if (segv) {
- env->exception.vaddress = addr;
- goto error;
- }
- if (val != env->exclusive_val) {
- goto finish;
- }
- if (is_pair) {
- if (size == 2) {
- segv = get_user_u32(val, addr + 4);
- } else {
- segv = get_user_u64(val, addr + 8);
- }
- if (segv) {
- env->exception.vaddress = addr + (size == 2 ? 4 : 8);
- goto error;
- }
- if (val != env->exclusive_high) {
- goto finish;
- }
- }
- /* handle the zero register */
- val = rt == 31 ? 0 : env->xregs[rt];
- switch (size) {
- case 0:
- segv = put_user_u8(val, addr);
- break;
- case 1:
- segv = put_user_u16(val, addr);
- break;
- case 2:
- segv = put_user_u32(val, addr);
- break;
- case 3:
- segv = put_user_u64(val, addr);
- break;
- }
- if (segv) {
- goto error;
- }
- if (is_pair) {
- /* handle the zero register */
- val = rt2 == 31 ? 0 : env->xregs[rt2];
- if (size == 2) {
- segv = put_user_u32(val, addr + 4);
- } else {
- segv = put_user_u64(val, addr + 8);
- }
- if (segv) {
- env->exception.vaddress = addr + (size == 2 ? 4 : 8);
- goto error;
- }
- }
- rc = 0;
-finish:
- env->pc += 4;
- /* rs == 31 encodes a write to the ZR, thus throwing away
- * the status return. This is rather silly but valid.
- */
- if (rs < 31) {
- env->xregs[rs] = rc;
- }
-error:
- /* instruction faulted, PC does not advance */
- /* either way a strex releases any exclusive lock we have */
- env->exclusive_addr = -1;
- end_exclusive();
- return segv;
-}
-
/* AArch64 main loop */
void cpu_loop(CPUARMState *env)
{
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
switch (trapnr) {
case EXCP_SWI:
info._sifields._sigfault._addr = env->pc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
- case EXCP_STREX:
- if (!do_strex_a64(env)) {
- break;
- }
- /* fall through for segv */
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
info.si_signo = TARGET_SIGSEGV;
case EXCP_YIELD:
/* nothing to do here for user-mode, just resume guest code */
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
abort();
process_pending_signals(env);
/* Exception return on AArch64 always clears the exclusive monitor,
* so any return to running guest code implies this.
- * A strex (successful or otherwise) also clears the monitor, so
- * we don't need to specialcase EXCP_STREX.
*/
env->exclusive_addr = -1;
}
#endif
-#ifdef TARGET_UNICORE32
-
-void cpu_loop(CPUUniCore32State *env)
-{
- CPUState *cs = CPU(uc32_env_get_cpu(env));
- int trapnr;
- unsigned int n, insn;
- target_siginfo_t info;
-
- for (;;) {
- cpu_exec_start(cs);
- trapnr = cpu_exec(cs);
- cpu_exec_end(cs);
- switch (trapnr) {
- case UC32_EXCP_PRIV:
- {
- /* system call */
- get_user_u32(insn, env->regs[31] - 4);
- n = insn & 0xffffff;
-
- if (n >= UC32_SYSCALL_BASE) {
- /* linux syscall */
- n -= UC32_SYSCALL_BASE;
- if (n == UC32_SYSCALL_NR_set_tls) {
- cpu_set_tls(env, env->regs[0]);
- env->regs[0] = 0;
- } else {
- abi_long ret = do_syscall(env,
- n,
- env->regs[0],
- env->regs[1],
- env->regs[2],
- env->regs[3],
- env->regs[4],
- env->regs[5],
- 0, 0);
- if (ret == -TARGET_ERESTARTSYS) {
- env->regs[31] -= 4;
- } else if (ret != -TARGET_QEMU_ESIGRETURN) {
- env->regs[0] = ret;
- }
- }
- } else {
- goto error;
- }
- }
- break;
- case UC32_EXCP_DTRAP:
- case UC32_EXCP_ITRAP:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
- case EXCP_INTERRUPT:
- /* just indicate that signals should be handled asap */
- break;
- case EXCP_DEBUG:
- {
- int sig;
-
- sig = gdb_handlesig(cs, TARGET_SIGTRAP);
- if (sig) {
- info.si_signo = sig;
- info.si_errno = 0;
- info.si_code = TARGET_TRAP_BRKPT;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- }
- break;
- default:
- goto error;
- }
- process_pending_signals(env);
- }
-
-error:
- EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
- abort();
-}
-#endif
-
#ifdef TARGET_SPARC
#define SPARC64_STACK_BIAS 2047
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
/* Compute PSR before exposing state. */
if (env->cc_op != CC_OP_FLAGS) {
/* XXX: check env->error_code */
info.si_code = TARGET_SEGV_MAPERR;
if (trapnr == TT_DFAULT)
- info._sifields._sigfault._addr = env->dmmuregs[4];
+ info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
else
info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
}
}
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch(trapnr) {
case POWERPC_EXCP_NONE:
/* Just go on */
info.si_code = TARGET_SEGV_MAPERR;
break;
}
- info._sifields._sigfault._addr = env->nip;
+ info._sifields._sigfault._addr = env->spr[SPR_DAR];
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
* in syscalls.
*/
env->crf[0] &= ~0x1;
+ env->nip += 4;
ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
env->gpr[5], env->gpr[6], env->gpr[7],
env->gpr[8], 0, 0);
if (ret == -TARGET_ERESTARTSYS) {
+ env->nip -= 4;
break;
}
- env->nip += 4;
if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
/* Returning from a successful sigreturn syscall.
Avoid corrupting register state. */
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
break;
MIPS_SYS(sys_dup3, 3)
MIPS_SYS(sys_pipe2, 2)
MIPS_SYS(sys_inotify_init1, 1)
- MIPS_SYS(sys_preadv, 6) /* 4330 */
- MIPS_SYS(sys_pwritev, 6)
+ MIPS_SYS(sys_preadv, 5) /* 4330 */
+ MIPS_SYS(sys_pwritev, 5)
MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
MIPS_SYS(sys_perf_event_open, 5)
MIPS_SYS(sys_accept4, 4)
MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
MIPS_SYS(sys_clock_adjtime, 2)
MIPS_SYS(sys_syncfs, 1)
+ MIPS_SYS(sys_sendmmsg, 4)
+ MIPS_SYS(sys_setns, 2)
+ MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
+ MIPS_SYS(sys_process_vm_writev, 6)
+ MIPS_SYS(sys_kcmp, 5)
+ MIPS_SYS(sys_finit_module, 3)
+ MIPS_SYS(sys_sched_setattr, 2)
+ MIPS_SYS(sys_sched_getattr, 3) /* 350 */
+ MIPS_SYS(sys_renameat2, 5)
+ MIPS_SYS(sys_seccomp, 3)
+ MIPS_SYS(sys_getrandom, 3)
+ MIPS_SYS(sys_memfd_create, 2)
+ MIPS_SYS(sys_bpf, 3) /* 355 */
+ MIPS_SYS(sys_execveat, 5)
+ MIPS_SYS(sys_userfaultfd, 1)
+ MIPS_SYS(sys_membarrier, 2)
+ MIPS_SYS(sys_mlock2, 3)
+ MIPS_SYS(sys_copy_file_range, 6) /* 360 */
+ MIPS_SYS(sys_preadv2, 6)
+ MIPS_SYS(sys_pwritev2, 6)
};
# undef MIPS_SYS
# endif /* O32 */
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch(trapnr) {
case EXCP_SYSCALL:
env->active_tc.PC += 4;
}
}
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
error:
EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
}
#endif
-#ifdef TARGET_OPENRISC
+#ifdef TARGET_NIOS2
-void cpu_loop(CPUOpenRISCState *env)
+void cpu_loop(CPUNios2State *env)
{
- CPUState *cs = CPU(openrisc_env_get_cpu(env));
- int trapnr, gdbsig;
- abi_long ret;
+ CPUState *cs = ENV_GET_CPU(env);
+ Nios2CPU *cpu = NIOS2_CPU(cs);
+ target_siginfo_t info;
+ int trapnr, gdbsig, ret;
for (;;) {
cpu_exec_start(cs);
gdbsig = 0;
switch (trapnr) {
- case EXCP_RESET:
- qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
- exit(EXIT_FAILURE);
- break;
- case EXCP_BUSERR:
- qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
- gdbsig = TARGET_SIGBUS;
- break;
- case EXCP_DPF:
- case EXCP_IPF:
- cpu_dump_state(cs, stderr, fprintf, 0);
- gdbsig = TARGET_SIGSEGV;
- break;
- case EXCP_TICK:
- qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
- break;
- case EXCP_ALIGN:
- qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
- gdbsig = TARGET_SIGBUS;
- break;
- case EXCP_ILLEGAL:
- qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
- gdbsig = TARGET_SIGILL;
- break;
- case EXCP_INT:
- qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
- break;
- case EXCP_DTLBMISS:
- case EXCP_ITLBMISS:
- qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
- break;
- case EXCP_RANGE:
- qemu_log_mask(CPU_LOG_INT, "\nRange\n");
- gdbsig = TARGET_SIGSEGV;
- break;
- case EXCP_SYSCALL:
- env->pc += 4; /* 0xc00; */
- ret = do_syscall(env,
- env->gpr[11], /* return value */
- env->gpr[3], /* r3 - r7 are params */
- env->gpr[4],
- env->gpr[5],
- env->gpr[6],
- env->gpr[7],
- env->gpr[8], 0, 0);
- if (ret == -TARGET_ERESTARTSYS) {
- env->pc -= 4;
- } else if (ret != -TARGET_QEMU_ESIGRETURN) {
- env->gpr[11] = ret;
- }
- break;
- case EXCP_FPE:
- qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
+ case EXCP_INTERRUPT:
+ /* just indicate that signals should be handled asap */
break;
case EXCP_TRAP:
- qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
- gdbsig = TARGET_SIGTRAP;
- break;
- case EXCP_NR:
- qemu_log_mask(CPU_LOG_INT, "\nNR\n");
+ if (env->regs[R_AT] == 0) {
+ abi_long ret;
+ qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
+
+ ret = do_syscall(env, env->regs[2],
+ env->regs[4], env->regs[5], env->regs[6],
+ env->regs[7], env->regs[8], env->regs[9],
+ 0, 0);
+
+ if (env->regs[2] == 0) { /* FIXME: syscall 0 workaround */
+ ret = 0;
+ }
+
+ env->regs[2] = abs(ret);
+ /* Return value is 0..4096 */
+ env->regs[7] = (ret > 0xfffffffffffff000ULL);
+ env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
+ env->regs[CR_STATUS] &= ~0x3;
+ env->regs[R_EA] = env->regs[R_PC] + 4;
+ env->regs[R_PC] += 4;
+ break;
+ } else {
+ qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
+
+ env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
+ env->regs[CR_STATUS] &= ~0x3;
+ env->regs[R_EA] = env->regs[R_PC] + 4;
+ env->regs[R_PC] = cpu->exception_addr;
+
+ gdbsig = TARGET_SIGTRAP;
+ break;
+ }
+ case 0xaa:
+ switch (env->regs[R_PC]) {
+ /*case 0x1000:*/ /* TODO:__kuser_helper_version */
+ case 0x1004: /* __kuser_cmpxchg */
+ start_exclusive();
+ if (env->regs[4] & 0x3) {
+ goto kuser_fail;
+ }
+ ret = get_user_u32(env->regs[2], env->regs[4]);
+ if (ret) {
+ end_exclusive();
+ goto kuser_fail;
+ }
+ env->regs[2] -= env->regs[5];
+ if (env->regs[2] == 0) {
+ put_user_u32(env->regs[6], env->regs[4]);
+ }
+ end_exclusive();
+ env->regs[R_PC] = env->regs[R_RA];
+ break;
+ /*case 0x1040:*/ /* TODO:__kuser_sigtramp */
+ default:
+ ;
+kuser_fail:
+ info.si_signo = TARGET_SIGSEGV;
+ info.si_errno = 0;
+ /* TODO: check env->error_code */
+ info.si_code = TARGET_SEGV_MAPERR;
+ info._sifields._sigfault._addr = env->regs[R_PC];
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ }
break;
default:
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
}
}
-#endif /* TARGET_OPENRISC */
+#endif /* TARGET_NIOS2 */
-#ifdef TARGET_SH4
-void cpu_loop(CPUSH4State *env)
-{
- CPUState *cs = CPU(sh_env_get_cpu(env));
- int trapnr, ret;
- target_siginfo_t info;
+#ifdef TARGET_OPENRISC
+
+void cpu_loop(CPUOpenRISCState *env)
+{
+ CPUState *cs = CPU(openrisc_env_get_cpu(env));
+ int trapnr;
+ abi_long ret;
+ target_siginfo_t info;
+
+ for (;;) {
+ cpu_exec_start(cs);
+ trapnr = cpu_exec(cs);
+ cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
+ switch (trapnr) {
+ case EXCP_SYSCALL:
+ env->pc += 4; /* 0xc00; */
+ ret = do_syscall(env,
+ cpu_get_gpr(env, 11), /* return value */
+ cpu_get_gpr(env, 3), /* r3 - r7 are params */
+ cpu_get_gpr(env, 4),
+ cpu_get_gpr(env, 5),
+ cpu_get_gpr(env, 6),
+ cpu_get_gpr(env, 7),
+ cpu_get_gpr(env, 8), 0, 0);
+ if (ret == -TARGET_ERESTARTSYS) {
+ env->pc -= 4;
+ } else if (ret != -TARGET_QEMU_ESIGRETURN) {
+ cpu_set_gpr(env, 11, ret);
+ }
+ break;
+ case EXCP_DPF:
+ case EXCP_IPF:
+ case EXCP_RANGE:
+ info.si_signo = TARGET_SIGSEGV;
+ info.si_errno = 0;
+ info.si_code = TARGET_SEGV_MAPERR;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_ALIGN:
+ info.si_signo = TARGET_SIGBUS;
+ info.si_errno = 0;
+ info.si_code = TARGET_BUS_ADRALN;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_ILLEGAL:
+ info.si_signo = TARGET_SIGILL;
+ info.si_errno = 0;
+ info.si_code = TARGET_ILL_ILLOPC;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_FPE:
+ info.si_signo = TARGET_SIGFPE;
+ info.si_errno = 0;
+ info.si_code = 0;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_INTERRUPT:
+ /* We processed the pending cpu work above. */
+ break;
+ case EXCP_DEBUG:
+ trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
+ if (trapnr) {
+ info.si_signo = trapnr;
+ info.si_errno = 0;
+ info.si_code = TARGET_TRAP_BRKPT;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ }
+ break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ process_pending_signals(env);
+ }
+}
+
+#endif /* TARGET_OPENRISC */
+
+#ifdef TARGET_SH4
+void cpu_loop(CPUSH4State *env)
+{
+ CPUState *cs = CPU(sh_env_get_cpu(env));
+ int trapnr, ret;
+ target_siginfo_t info;
while (1) {
+ bool arch_interrupt = true;
+
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
switch (trapnr) {
case 0x160:
int sig;
sig = gdb_handlesig(cs, TARGET_SIGTRAP);
- if (sig)
- {
+ if (sig) {
info.si_signo = sig;
info.si_errno = 0;
info.si_code = TARGET_TRAP_BRKPT;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
+ } else {
+ arch_interrupt = false;
+ }
}
break;
case 0xa0:
info._sifields._sigfault._addr = env->tea;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
-
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ arch_interrupt = false;
+ break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
exit(EXIT_FAILURE);
}
process_pending_signals (env);
+
+ /* Most of the traps imply an exception or interrupt, which
+ implies an REI instruction has been executed. Which means
+ that LDST (aka LOK_ADDR) should be cleared. But there are
+ a few exceptions for traps internal to QEMU. */
+ if (arch_interrupt) {
+ env->lock_addr = -1;
+ }
}
}
#endif
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch (trapnr) {
case 0xaa:
{
}
}
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch (trapnr) {
case 0xaa:
{
}
}
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch(trapnr) {
case EXCP_ILLEGAL:
{
info._sifields._sigfault._addr = env->pc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
+ case EXCP_CHK:
+ info.si_signo = TARGET_SIGFPE;
+ info.si_errno = 0;
+ info.si_code = TARGET_FPE_INTOVF;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_DIV0:
+ info.si_signo = TARGET_SIGFPE;
+ info.si_errno = 0;
+ info.si_code = TARGET_FPE_INTDIV;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
case EXCP_TRAP0:
{
abi_long ret;
}
}
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
abort();
#endif /* TARGET_M68K */
#ifdef TARGET_ALPHA
-static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
-{
- target_ulong addr, val, tmp;
- target_siginfo_t info;
- int ret = 0;
-
- addr = env->lock_addr;
- tmp = env->lock_st_addr;
- env->lock_addr = -1;
- env->lock_st_addr = 0;
-
- start_exclusive();
- mmap_lock();
-
- if (addr == tmp) {
- if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
- goto do_sigsegv;
- }
-
- if (val == env->lock_value) {
- tmp = env->ir[reg];
- if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
- goto do_sigsegv;
- }
- ret = 1;
- }
- }
- env->ir[reg] = ret;
- env->pc += 4;
-
- mmap_unlock();
- end_exclusive();
- return;
-
- do_sigsegv:
- mmap_unlock();
- end_exclusive();
-
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = addr;
- queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info);
-}
-
void cpu_loop(CPUAlphaState *env)
{
CPUState *cs = CPU(alpha_env_get_cpu(env));
abi_long sysret;
while (1) {
+ bool arch_interrupt = true;
+
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
-
- /* All of the traps imply a transition through PALcode, which
- implies an REI instruction has been executed. Which means
- that the intr_flag should be cleared. */
- env->intr_flag = 0;
+ process_queued_cpu_work(cs);
switch (trapnr) {
case EXCP_RESET:
exit(EXIT_FAILURE);
break;
case EXCP_MMFAULT:
- env->lock_addr = -1;
info.si_signo = TARGET_SIGSEGV;
info.si_errno = 0;
info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
case EXCP_UNALIGN:
- env->lock_addr = -1;
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
info.si_code = TARGET_BUS_ADRALN;
break;
case EXCP_OPCDEC:
do_sigill:
- env->lock_addr = -1;
info.si_signo = TARGET_SIGILL;
info.si_errno = 0;
info.si_code = TARGET_ILL_ILLOPC;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
case EXCP_ARITH:
- env->lock_addr = -1;
info.si_signo = TARGET_SIGFPE;
info.si_errno = 0;
info.si_code = TARGET_FPE_FLTINV;
/* No-op. Linux simply re-enables the FPU. */
break;
case EXCP_CALL_PAL:
- env->lock_addr = -1;
switch (env->error_code) {
case 0x80:
/* BPT */
case EXCP_DEBUG:
info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
if (info.si_signo) {
- env->lock_addr = -1;
info.si_errno = 0;
info.si_code = TARGET_TRAP_BRKPT;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ } else {
+ arch_interrupt = false;
}
break;
- case EXCP_STL_C:
- case EXCP_STQ_C:
- do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
- break;
case EXCP_INTERRUPT:
/* Just indicate that signals should be handled asap. */
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ arch_interrupt = false;
+ break;
default:
printf ("Unhandled trap: 0x%x\n", trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
exit(EXIT_FAILURE);
}
process_pending_signals (env);
+
+ /* Most of the traps imply a transition through PALcode, which
+ implies an REI instruction has been executed. Which means
+ that RX and LOCK_ADDR should be cleared. But there are a
+ few exceptions for traps internal to QEMU. */
+ if (arch_interrupt) {
+ env->flags &= ~ENV_FLAG_RX_FLAG;
+ env->lock_addr = -1;
+ }
}
}
#endif /* TARGET_ALPHA */
#ifdef TARGET_S390X
+
+/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */
+#define S390X_FAIL_ADDR_MASK -4096LL
+
void cpu_loop(CPUS390XState *env)
{
CPUState *cs = CPU(s390_env_get_cpu(env));
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch (trapnr) {
case EXCP_INTERRUPT:
/* Just indicate that signals should be handled asap. */
sig = TARGET_SIGSEGV;
/* XXX: check env->error_code */
n = TARGET_SEGV_MAPERR;
- addr = env->__excp_addr;
+ addr = env->__excp_addr & S390X_FAIL_ADDR_MASK;
goto do_signal;
case PGM_EXECUTE:
case PGM_SPECIFICATION:
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
cpu_exec_start(cs);
trapnr = cpu_exec(cs);
cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
switch (trapnr) {
case TILEGX_EXCP_SYSCALL:
{
case TILEGX_EXCP_REG_UDN_ACCESS:
gen_sigill_reg(env);
break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
default:
fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
g_assert_not_reached();
#endif
-THREAD CPUState *thread_cpu;
+#ifdef TARGET_RISCV
+
+void cpu_loop(CPURISCVState *env)
+{
+ CPUState *cs = CPU(riscv_env_get_cpu(env));
+ int trapnr, signum, sigcode;
+ target_ulong sigaddr;
+ target_ulong ret;
+
+ for (;;) {
+ cpu_exec_start(cs);
+ trapnr = cpu_exec(cs);
+ cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
+ signum = 0;
+ sigcode = 0;
+ sigaddr = 0;
+
+ switch (trapnr) {
+ case EXCP_INTERRUPT:
+ /* just indicate that signals should be handled asap */
+ break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
+ case RISCV_EXCP_U_ECALL:
+ env->pc += 4;
+ if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) {
+ /* riscv_flush_icache_syscall is a no-op in QEMU as
+ self-modifying code is automatically detected */
+ ret = 0;
+ } else {
+ ret = do_syscall(env,
+ env->gpr[xA7],
+ env->gpr[xA0],
+ env->gpr[xA1],
+ env->gpr[xA2],
+ env->gpr[xA3],
+ env->gpr[xA4],
+ env->gpr[xA5],
+ 0, 0);
+ }
+ if (ret == -TARGET_ERESTARTSYS) {
+ env->pc -= 4;
+ } else if (ret != -TARGET_QEMU_ESIGRETURN) {
+ env->gpr[xA0] = ret;
+ }
+ if (cs->singlestep_enabled) {
+ goto gdbstep;
+ }
+ break;
+ case RISCV_EXCP_ILLEGAL_INST:
+ signum = TARGET_SIGILL;
+ sigcode = TARGET_ILL_ILLOPC;
+ break;
+ case RISCV_EXCP_BREAKPOINT:
+ signum = TARGET_SIGTRAP;
+ sigcode = TARGET_TRAP_BRKPT;
+ sigaddr = env->pc;
+ break;
+ case RISCV_EXCP_INST_PAGE_FAULT:
+ case RISCV_EXCP_LOAD_PAGE_FAULT:
+ case RISCV_EXCP_STORE_PAGE_FAULT:
+ signum = TARGET_SIGSEGV;
+ sigcode = TARGET_SEGV_MAPERR;
+ break;
+ case EXCP_DEBUG:
+ gdbstep:
+ signum = gdb_handlesig(cs, TARGET_SIGTRAP);
+ sigcode = TARGET_TRAP_BRKPT;
+ break;
+ default:
+ EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
+ trapnr);
+ exit(EXIT_FAILURE);
+ }
+
+ if (signum) {
+ target_siginfo_t info = {
+ .si_signo = signum,
+ .si_errno = 0,
+ .si_code = sigcode,
+ ._sifields._sigfault._addr = sigaddr
+ };
+ queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
+ }
+
+ process_pending_signals(env);
+ }
+}
+
+#endif /* TARGET_RISCV */
+
+#ifdef TARGET_HPPA
+
+static abi_ulong hppa_lws(CPUHPPAState *env)
+{
+ uint32_t which = env->gr[20];
+ abi_ulong addr = env->gr[26];
+ abi_ulong old = env->gr[25];
+ abi_ulong new = env->gr[24];
+ abi_ulong size, ret;
+
+ switch (which) {
+ default:
+ return -TARGET_ENOSYS;
+
+ case 0: /* elf32 atomic 32bit cmpxchg */
+ if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) {
+ return -TARGET_EFAULT;
+ }
+ old = tswap32(old);
+ new = tswap32(new);
+ ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
+ ret = tswap32(ret);
+ break;
+
+ case 2: /* elf32 atomic "new" cmpxchg */
+ size = env->gr[23];
+ if (size >= 4) {
+ return -TARGET_ENOSYS;
+ }
+ if (((addr | old | new) & ((1 << size) - 1))
+ || !access_ok(VERIFY_WRITE, addr, 1 << size)
+ || !access_ok(VERIFY_READ, old, 1 << size)
+ || !access_ok(VERIFY_READ, new, 1 << size)) {
+ return -TARGET_EFAULT;
+ }
+ /* Note that below we use host-endian loads so that the cmpxchg
+ can be host-endian as well. */
+ switch (size) {
+ case 0:
+ old = *(uint8_t *)g2h(old);
+ new = *(uint8_t *)g2h(new);
+ ret = atomic_cmpxchg((uint8_t *)g2h(addr), old, new);
+ ret = ret != old;
+ break;
+ case 1:
+ old = *(uint16_t *)g2h(old);
+ new = *(uint16_t *)g2h(new);
+ ret = atomic_cmpxchg((uint16_t *)g2h(addr), old, new);
+ ret = ret != old;
+ break;
+ case 2:
+ old = *(uint32_t *)g2h(old);
+ new = *(uint32_t *)g2h(new);
+ ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
+ ret = ret != old;
+ break;
+ case 3:
+ {
+ uint64_t o64, n64, r64;
+ o64 = *(uint64_t *)g2h(old);
+ n64 = *(uint64_t *)g2h(new);
+#ifdef CONFIG_ATOMIC64
+ r64 = atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64, n64);
+ ret = r64 != o64;
+#else
+ start_exclusive();
+ r64 = *(uint64_t *)g2h(addr);
+ ret = 1;
+ if (r64 == o64) {
+ *(uint64_t *)g2h(addr) = n64;
+ ret = 0;
+ }
+ end_exclusive();
+#endif
+ }
+ break;
+ }
+ break;
+ }
+
+ env->gr[28] = ret;
+ return 0;
+}
+
+void cpu_loop(CPUHPPAState *env)
+{
+ CPUState *cs = CPU(hppa_env_get_cpu(env));
+ target_siginfo_t info;
+ abi_ulong ret;
+ int trapnr;
+
+ while (1) {
+ cpu_exec_start(cs);
+ trapnr = cpu_exec(cs);
+ cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
+ switch (trapnr) {
+ case EXCP_SYSCALL:
+ ret = do_syscall(env, env->gr[20],
+ env->gr[26], env->gr[25],
+ env->gr[24], env->gr[23],
+ env->gr[22], env->gr[21], 0, 0);
+ switch (ret) {
+ default:
+ env->gr[28] = ret;
+ /* We arrived here by faking the gateway page. Return. */
+ env->iaoq_f = env->gr[31];
+ env->iaoq_b = env->gr[31] + 4;
+ break;
+ case -TARGET_ERESTARTSYS:
+ case -TARGET_QEMU_ESIGRETURN:
+ break;
+ }
+ break;
+ case EXCP_SYSCALL_LWS:
+ env->gr[21] = hppa_lws(env);
+ /* We arrived here by faking the gateway page. Return. */
+ env->iaoq_f = env->gr[31];
+ env->iaoq_b = env->gr[31] + 4;
+ break;
+ case EXCP_ITLB_MISS:
+ case EXCP_DTLB_MISS:
+ case EXCP_NA_ITLB_MISS:
+ case EXCP_NA_DTLB_MISS:
+ case EXCP_IMP:
+ case EXCP_DMP:
+ case EXCP_DMB:
+ case EXCP_PAGE_REF:
+ case EXCP_DMAR:
+ case EXCP_DMPI:
+ info.si_signo = TARGET_SIGSEGV;
+ info.si_errno = 0;
+ info.si_code = TARGET_SEGV_ACCERR;
+ info._sifields._sigfault._addr = env->cr[CR_IOR];
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_UNALIGN:
+ info.si_signo = TARGET_SIGBUS;
+ info.si_errno = 0;
+ info.si_code = 0;
+ info._sifields._sigfault._addr = env->cr[CR_IOR];
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_ILL:
+ case EXCP_PRIV_OPR:
+ case EXCP_PRIV_REG:
+ info.si_signo = TARGET_SIGILL;
+ info.si_errno = 0;
+ info.si_code = TARGET_ILL_ILLOPN;
+ info._sifields._sigfault._addr = env->iaoq_f;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_OVERFLOW:
+ case EXCP_COND:
+ case EXCP_ASSIST:
+ info.si_signo = TARGET_SIGFPE;
+ info.si_errno = 0;
+ info.si_code = 0;
+ info._sifields._sigfault._addr = env->iaoq_f;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_DEBUG:
+ trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
+ if (trapnr) {
+ info.si_signo = trapnr;
+ info.si_errno = 0;
+ info.si_code = TARGET_TRAP_BRKPT;
+ queue_signal(env, trapnr, QEMU_SI_FAULT, &info);
+ }
+ break;
+ case EXCP_INTERRUPT:
+ /* just indicate that signals should be handled asap */
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ process_pending_signals(env);
+ }
+}
+
+#endif /* TARGET_HPPA */
+
+__thread CPUState *thread_cpu;
+
+bool qemu_cpu_is_self(CPUState *cpu)
+{
+ return thread_cpu == cpu;
+}
+
+void qemu_cpu_kick(CPUState *cpu)
+{
+ cpu_exit(cpu);
+}
void task_settid(TaskState *ts)
{
qemu_set_log(mask);
}
+static void handle_arg_dfilter(const char *arg)
+{
+ qemu_set_dfilter_ranges(arg, NULL);
+}
+
static void handle_arg_log_filename(const char *arg)
{
qemu_set_log_filename(arg, &error_fatal);
unsigned long unshifted = reserved_va;
p++;
reserved_va <<= shift;
- if (((reserved_va >> shift) != unshifted)
-#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
- || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
-#endif
- ) {
+ if (reserved_va >> shift != unshifted
+ || (MAX_RESERVED_VA && reserved_va > MAX_RESERVED_VA)) {
fprintf(stderr, "Reserved virtual address too big\n");
exit(EXIT_FAILURE);
}
static void handle_arg_version(const char *arg)
{
printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
- ", " QEMU_COPYRIGHT "\n");
+ "\n" QEMU_COPYRIGHT "\n");
exit(EXIT_SUCCESS);
}
{"d", "QEMU_LOG", true, handle_arg_log,
"item[,...]", "enable logging of specified items "
"(use '-d help' for a list of items)"},
+ {"dfilter", "QEMU_DFILTER", true, handle_arg_dfilter,
+ "range[,...]","filter logging based on address range"},
{"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
"logfile", "write logs to 'logfile' (default stderr)"},
{"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
" -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
" QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
"Note that if you provide several changes to a single variable\n"
- "the last change will stay in effect.\n");
+ "the last change will stay in effect.\n"
+ "\n"
+ QEMU_HELP_BOTTOM "\n");
exit(exitcode);
}
int ret;
int execfd;
+ module_call_init(MODULE_INIT_TRACE);
+ qemu_init_cpu_list();
module_call_init(MODULE_INIT_QOM);
- if ((envlist = envlist_create()) == NULL) {
- (void) fprintf(stderr, "Unable to allocate envlist\n");
- exit(EXIT_FAILURE);
- }
+ envlist = envlist_create();
/* add current environment into the list */
for (wrk = environ; *wrk != NULL; wrk++) {
init_qemu_uname_release();
+ execfd = qemu_getauxval(AT_EXECFD);
+ if (execfd == 0) {
+ execfd = open(filename, O_RDONLY);
+ if (execfd < 0) {
+ printf("Error while loading %s: %s\n", filename, strerror(errno));
+ _exit(EXIT_FAILURE);
+ }
+ }
+
if (cpu_model == NULL) {
-#if defined(TARGET_I386)
-#ifdef TARGET_X86_64
- cpu_model = "qemu64";
-#else
- cpu_model = "qemu32";
-#endif
-#elif defined(TARGET_ARM)
- cpu_model = "any";
-#elif defined(TARGET_UNICORE32)
- cpu_model = "any";
-#elif defined(TARGET_M68K)
- cpu_model = "any";
-#elif defined(TARGET_SPARC)
-#ifdef TARGET_SPARC64
- cpu_model = "TI UltraSparc II";
-#else
- cpu_model = "Fujitsu MB86904";
-#endif
-#elif defined(TARGET_MIPS)
-#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
- cpu_model = "5KEf";
-#else
- cpu_model = "24Kf";
-#endif
-#elif defined TARGET_OPENRISC
- cpu_model = "or1200";
-#elif defined(TARGET_PPC)
-# ifdef TARGET_PPC64
- cpu_model = "POWER8";
-# else
- cpu_model = "750";
-# endif
-#elif defined TARGET_SH4
- cpu_model = TYPE_SH7785_CPU;
-#else
- cpu_model = "any";
-#endif
+ cpu_model = cpu_get_model(get_elf_eflags(execfd));
}
tcg_exec_init(0);
/* NOTE: we need to init the CPU at this stage to get
qemu_host_page_size */
cpu = cpu_init(cpu_model);
- if (!cpu) {
- fprintf(stderr, "Unable to find CPU definition\n");
- exit(EXIT_FAILURE);
- }
env = cpu->env_ptr;
cpu_reset(cpu);
cpu->opaque = ts;
task_settid(ts);
- execfd = qemu_getauxval(AT_EXECFD);
- if (execfd == 0) {
- execfd = open(filename, O_RDONLY);
- if (execfd < 0) {
- printf("Error while loading %s: %s\n", filename, strerror(errno));
- _exit(EXIT_FAILURE);
- }
- }
-
ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
info, &bprm);
if (ret != 0) {
}
for (wrk = target_environ; *wrk; wrk++) {
- free(*wrk);
+ g_free(*wrk);
}
- free(target_environ);
+ g_free(target_environ);
if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
qemu_log("guest_base 0x%lx\n", guest_base);
qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
- qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
- info->start_code);
- qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
- info->start_data);
+ qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", info->start_code);
+ qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", info->start_data);
qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
- qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
- info->start_stack);
+ qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", info->start_stack);
qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
+ qemu_log("argv_start 0x" TARGET_ABI_FMT_lx "\n", info->arg_start);
+ qemu_log("env_start 0x" TARGET_ABI_FMT_lx "\n",
+ info->arg_end + (abi_ulong)sizeof(abi_ulong));
+ qemu_log("auxv_start 0x" TARGET_ABI_FMT_lx "\n", info->saved_auxv);
}
target_set_brk(info->brk);
/* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
generating the prologue until now so that the prologue can take
the real value of GUEST_BASE into account. */
- tcg_prologue_init(&tcg_ctx);
+ tcg_prologue_init(tcg_ctx);
+ tcg_region_init();
#if defined(TARGET_I386)
env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
}
env->pc = regs->pc;
env->xregs[31] = regs->sp;
+#ifdef TARGET_WORDS_BIGENDIAN
+ env->cp15.sctlr_el[1] |= SCTLR_E0E;
+ for (i = 1; i < 4; ++i) {
+ env->cp15.sctlr_el[i] |= SCTLR_EE;
+ }
+#endif
}
#elif defined(TARGET_ARM)
{
}
#endif
}
-#elif defined(TARGET_UNICORE32)
- {
- int i;
- cpu_asr_write(env, regs->uregs[32], 0xffffffff);
- for (i = 0; i < 32; i++) {
- env->regs[i] = regs->uregs[i];
- }
- }
#elif defined(TARGET_SPARC)
{
int i;
restore_snan_bit_mode(env);
}
}
+#elif defined(TARGET_NIOS2)
+ {
+ env->regs[0] = 0;
+ env->regs[1] = regs->r1;
+ env->regs[2] = regs->r2;
+ env->regs[3] = regs->r3;
+ env->regs[4] = regs->r4;
+ env->regs[5] = regs->r5;
+ env->regs[6] = regs->r6;
+ env->regs[7] = regs->r7;
+ env->regs[8] = regs->r8;
+ env->regs[9] = regs->r9;
+ env->regs[10] = regs->r10;
+ env->regs[11] = regs->r11;
+ env->regs[12] = regs->r12;
+ env->regs[13] = regs->r13;
+ env->regs[14] = regs->r14;
+ env->regs[15] = regs->r15;
+ /* TODO: unsigned long orig_r2; */
+ env->regs[R_RA] = regs->ra;
+ env->regs[R_FP] = regs->fp;
+ env->regs[R_SP] = regs->sp;
+ env->regs[R_GP] = regs->gp;
+ env->regs[CR_ESTATUS] = regs->estatus;
+ env->regs[R_EA] = regs->ea;
+ /* TODO: unsigned long orig_r7; */
+
+ /* Emulate eret when starting thread. */
+ env->regs[R_PC] = regs->ea;
+ }
#elif defined(TARGET_OPENRISC)
{
int i;
for (i = 0; i < 32; i++) {
- env->gpr[i] = regs->gpr[i];
+ cpu_set_gpr(env, i, regs->gpr[i]);
}
-
- env->sr = regs->sr;
env->pc = regs->pc;
+ cpu_set_sr(env, regs->sr);
+ }
+#elif defined(TARGET_RISCV)
+ {
+ env->pc = regs->sepc;
+ env->gpr[xSP] = regs->sp;
}
#elif defined(TARGET_SH4)
{
}
env->pc = regs->pc;
}
+#elif defined(TARGET_HPPA)
+ {
+ int i;
+ for (i = 1; i < 32; i++) {
+ env->gr[i] = regs->gr[i];
+ }
+ env->iaoq_f = regs->iaoq[0];
+ env->iaoq_b = regs->iaoq[1];
+ }
#else
#error unsupported target CPU
#endif
-#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
+#if defined(TARGET_ARM) || defined(TARGET_M68K)
ts->stack_base = info->start_stack;
ts->heap_base = info->brk;
/* This will be filled in on the first SYS_HEAPINFO call. */
}
gdb_handlesig(cpu, 0);
}
- trace_init_vcpu_events();
cpu_loop(env);
/* never exits */
return 0;
projects / qemu.git / blobdiff