/* save the vga display in a PPM image even if no display is
available */
-static void vmsvga_screen_dump(void *opaque, const char *filename)
+static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch)
{
struct vmsvga_state_s *s = opaque;
if (!s->enable) {
- s->vga.screen_dump(&s->vga, filename);
+ s->vga.screen_dump(&s->vga, filename, cswitch);
return;
}
}
};
-static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size,
+static void vmsvga_init(struct vmsvga_state_s *s,
MemoryRegion *address_space, MemoryRegion *io)
{
s->scratch_size = SVGA_SCRATCH_SIZE;
vmstate_register_ram_global(&s->fifo_ram);
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
- vga_common_init(&s->vga, vga_ram_size);
+ vga_common_init(&s->vga);
vga_init(&s->vga, address_space, io, true);
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
switch (addr) {
case SVGA_IO_MUL * SVGA_INDEX_PORT:
- return vmsvga_index_write(s, addr, data);
+ vmsvga_index_write(s, addr, data);
+ break;
case SVGA_IO_MUL * SVGA_VALUE_PORT:
- return vmsvga_value_write(s, addr, data);
+ vmsvga_value_write(s, addr, data);
+ break;
case SVGA_IO_MUL * SVGA_BIOS_PORT:
- return vmsvga_bios_write(s, addr, data);
+ vmsvga_bios_write(s, addr, data);
+ break;
}
}
"vmsvga-io", 0x10);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
- vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev),
+ vmsvga_init(&s->chip, pci_address_space(dev),
pci_address_space_io(dev));
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
return 0;
}
+static Property vga_vmware_properties[] = {
+ DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
+ chip.vga.vram_size_mb, 16),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void vmsvga_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
k->subsystem_id = SVGA_PCI_DEVICE_ID;
dc->reset = vmsvga_reset;
dc->vmsd = &vmstate_vmware_vga;
+ dc->props = vga_vmware_properties;
}
static TypeInfo vmsvga_info = {