struct fs_dma_ctrl
{
CPUState *env;
- target_phys_addr_t base;
int nr_channels;
struct fs_dma_channel *channels;
&& ctrl->channels[c].client;
}
-static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
+static inline int fs_channel(target_phys_addr_t addr)
{
/* Every channel has a 0x2000 ctrl register map. */
- return (addr - base) >> 13;
+ return addr >> 13;
}
#ifdef USE_THIS_DEAD_CODE
uint32_t r = 0;
/* Make addr relative to this instances base. */
- c = fs_channel(ctrl->base, addr);
+ c = fs_channel(addr);
addr &= 0x1fff;
switch (addr)
{
int c;
/* Make addr relative to this instances base. */
- c = fs_channel(ctrl->base, addr);
+ c = fs_channel(addr);
addr &= 0x1fff;
switch (addr)
{
ctrl->bh = qemu_bh_new(DMA_run, ctrl);
- ctrl->base = base;
ctrl->env = env;
ctrl->nr_channels = nr_channels;
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
dma_read,
dma_write,
ctrl);
- cpu_register_physical_memory (base + i * 0x2000,
- sizeof ctrl->channels[i].regs,
- ctrl->channels[i].regmap);
+ cpu_register_physical_memory_offset (base + i * 0x2000,
+ sizeof ctrl->channels[i].regs, ctrl->channels[i].regmap,
+ i * 0x2000);
}
return ctrl;