hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query

[qemu.git] / target-unicore32 / helper.c

diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index e5ebbf4b180a787c13866c5fdcfcdf9a2e3d45e3..ae63277c84cc672f9656b8d50100578589366cfb 100644 (file)
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -25,15 +25,9 @@
 #define DPRINTF(fmt, ...) do {} while (0)
 #endif
 
-CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
+UniCore32CPU *uc32_cpu_init(const char *cpu_model)
 {
-    UniCore32CPU *cpu;
-
-    cpu = UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
-    if (cpu == NULL) {
-        return NULL;
-    }
-    return &cpu->env;
+    return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
 }
 
 uint32_t HELPER(clo)(uint32_t x)
@@ -250,3 +244,18 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
     return 1;
 }
 #endif
+
+bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+    if (interrupt_request & CPU_INTERRUPT_HARD) {
+        UniCore32CPU *cpu = UNICORE32_CPU(cs);
+        CPUUniCore32State *env = &cpu->env;
+
+        if (!(env->uncached_asr & ASR_I)) {
+            cs->exception_index = UC32_EXCP_INTR;
+            uc32_cpu_do_interrupt(cs);
+            return true;
+        }
+    }
+    return false;
+}