* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "cpu.h"
#include "disas/disas.h"
+#include "exec/exec-all.h"
#include "tcg-op.h"
#include "qemu/log.h"
+#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+#include "trace-tcg.h"
+#include "exec/log.h"
+
+
//#define DEBUG_DISPATCH 1
/* Fake floating point. */
static TCGv_i32 cpu_halted;
static TCGv_i32 cpu_exception_index;
-static TCGv_ptr cpu_env;
+static TCGv_env cpu_env;
static char cpu_reg_names[3*8*3 + 5*4];
static TCGv cpu_dregs[8];
char *p;
int i;
-#define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
-#define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
-#define DEFF64(name, offset) DEFO64(name, offset)
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
+
+#define DEFO32(name, offset) \
+ QREG_##name = tcg_global_mem_new_i32(cpu_env, \
+ offsetof(CPUM68KState, offset), #name);
+#define DEFO64(name, offset) \
+ QREG_##name = tcg_global_mem_new_i64(cpu_env, \
+ offsetof(CPUM68KState, offset), #name);
+#define DEFF64(name, offset) DEFO64(name, offset)
#include "qregs.def"
#undef DEFO32
#undef DEFO64
#undef DEFF64
- cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
+ cpu_halted = tcg_global_mem_new_i32(cpu_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, halted), "HALTED");
- cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0,
+ cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, exception_index),
"EXCEPTION");
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
-
p = cpu_reg_names;
for (i = 0; i < 8; i++) {
sprintf(p, "D%d", i);
- cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0,
+ cpu_dregs[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUM68KState, dregs[i]), p);
p += 3;
sprintf(p, "A%d", i);
- cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0,
+ cpu_aregs[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUM68KState, aregs[i]), p);
p += 3;
sprintf(p, "F%d", i);
- cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUM68KState, fregs[i]), p);
p += 3;
}
for (i = 0; i < 4; i++) {
sprintf(p, "ACC%d", i);
- cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUM68KState, macc[i]), p);
p += 5;
}
- NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");
- store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");
+ NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
+ store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
}
/* internal defines */
uint32_t fpcr;
struct TranslationBlock *tb;
int singlestep_enabled;
- int is_mem;
TCGv_i64 mactmp;
int done_mac;
} DisasContext;
uint16_t insn) \
{ \
qemu_log("Dispatch " #name "\n"); \
- real_disas_##name(s, env, insn); \
+ real_disas_##name(env, s, insn); \
} \
static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
uint16_t insn)
{
TCGv tmp;
int index = IS_USER(s);
- s->is_mem = 1;
tmp = tcg_temp_new_i32();
switch(opsize) {
case OS_BYTE:
{
TCGv_i64 tmp;
int index = IS_USER(s);
- s->is_mem = 1;
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ldf64(tmp, addr, index);
gen_throws_exception = gen_last_qop;
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
{
int index = IS_USER(s);
- s->is_mem = 1;
switch(opsize) {
case OS_BYTE:
tcg_gen_qemu_st8(val, addr, index);
static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
{
int index = IS_USER(s);
- s->is_mem = 1;
tcg_gen_qemu_stf64(val, addr, index);
gen_throws_exception = gen_last_qop;
}
}
}
+/* Read a 16-bit immediate constant */
+static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
+{
+ uint16_t im;
+ im = cpu_lduw_code(env, s->pc);
+ s->pc += 2;
+ return im;
+}
+
+/* Read an 8-bit immediate constant */
+static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
+{
+ return read_im16(env, s);
+}
+
/* Read a 32-bit immediate constant. */
static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
{
uint32_t im;
- im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
- s->pc += 2;
- im |= cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ im = read_im16(env, s) << 16;
+ im |= 0xffff & read_im16(env, s);
return im;
}
/* Handle a base + index + displacement effective addresss.
A NULL_QREG base means pc-relative. */
-static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize,
- TCGv base)
+static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
{
uint32_t offset;
uint16_t ext;
uint32_t bd, od;
offset = s->pc;
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
return NULL_QREG;
+ if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
+ !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
+ ext &= ~(3 << 9);
+ }
+
if (ext & 0x100) {
/* full extension word format */
if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
if ((ext & 0x30) > 0x10) {
/* base displacement */
if ((ext & 0x30) == 0x20) {
- bd = (int16_t)cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ bd = (int16_t)read_im16(env, s);
} else {
bd = read_im32(env, s);
}
if ((ext & 3) > 1) {
/* outer displacement */
if ((ext & 3) == 2) {
- od = (int16_t)cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ od = (int16_t)read_im16(env, s);
} else {
od = read_im32(env, s);
}
case 5: /* Indirect displacement. */
reg = AREG(insn, 0);
tmp = tcg_temp_new();
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
return tmp;
case 6: /* Indirect index + displacement. */
reg = AREG(insn, 0);
- return gen_lea_indexed(env, s, opsize, reg);
+ return gen_lea_indexed(env, s, reg);
case 7: /* Other */
switch (insn & 7) {
case 0: /* Absolute short. */
- offset = cpu_ldsw_code(env, s->pc);
- s->pc += 2;
+ offset = (int16_t)read_im16(env, s);
return tcg_const_i32(offset);
case 1: /* Absolute long. */
offset = read_im32(env, s);
return tcg_const_i32(offset);
case 2: /* pc displacement */
offset = s->pc;
- offset += cpu_ldsw_code(env, s->pc);
- s->pc += 2;
+ offset += (int16_t)read_im16(env, s);
return tcg_const_i32(offset);
case 3: /* pc index+displacement. */
- return gen_lea_indexed(env, s, opsize, NULL_QREG);
+ return gen_lea_indexed(env, s, NULL_QREG);
case 4: /* Immediate. */
default:
return NULL_QREG;
switch (opsize) {
case OS_BYTE:
if (what == EA_LOADS) {
- offset = cpu_ldsb_code(env, s->pc + 1);
+ offset = (int8_t)read_im8(env, s);
} else {
- offset = cpu_ldub_code(env, s->pc + 1);
+ offset = read_im8(env, s);
}
- s->pc += 2;
break;
case OS_WORD:
if (what == EA_LOADS) {
- offset = cpu_ldsw_code(env, s->pc);
+ offset = (int16_t)read_im16(env, s);
} else {
- offset = cpu_lduw_code(env, s->pc);
+ offset = read_im16(env, s);
}
- s->pc += 2;
break;
case OS_LONG:
offset = read_im32(env, s);
}
/* This generates a conditional branch, clobbering all temporaries. */
-static void gen_jmpcc(DisasContext *s, int cond, int l1)
+static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
{
TCGv tmp;
DISAS_INSN(scc)
{
- int l1;
+ TCGLabel *l1;
int cond;
TCGv reg;
} \
} while (0)
+static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
+{
+#ifndef CONFIG_USER_ONLY
+ return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
+ (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
+#else
+ return true;
+#endif
+}
+
/* Generate a jump to an immediate address. */
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
{
- TranslationBlock *tb;
-
- tb = s->tb;
if (unlikely(s->singlestep_enabled)) {
gen_exception(s, dest, EXCP_DEBUG);
- } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
- (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
+ } else if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(QREG_PC, dest);
- tcg_gen_exit_tb((uintptr_t)tb + n);
+ tcg_gen_exit_tb((uintptr_t)s->tb + n);
} else {
gen_jmp_im(s, dest);
tcg_gen_exit_tb(0);
TCGv reg;
uint16_t ext;
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
if (ext & 0x87f8) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
return;
TCGv tmp;
int is_load;
- mask = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ mask = read_im16(env, s);
tmp = gen_lea(env, s, insn, OS_LONG);
if (IS_NULL_QREG(tmp)) {
gen_addr_fault(s);
opsize = OS_LONG;
op = (insn >> 6) & 3;
- bitnum = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ bitnum = read_im16(env, s);
if (bitnum & 0xff00) {
disas_undef(env, s, insn);
return;
else if ((insn & 0x3f) == 0x3c)
{
uint16_t val;
- val = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ val = read_im16(env, s);
gen_set_sr_im(s, val, ccr_only);
}
else
/* The upper 32 bits of the product are discarded, so
muls.l and mulu.l are functionally equivalent. */
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
if (ext & 0x87ff) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
return;
int32_t offset;
uint32_t base;
int op;
- int l1;
+ TCGLabel *l1;
base = s->pc;
op = (insn >> 8) & 0xf;
offset = (int8_t)insn;
if (offset == 0) {
- offset = cpu_ldsw_code(env, s->pc);
- s->pc += 2;
+ offset = (int16_t)read_im16(env, s);
} else if (offset == -1) {
offset = read_im32(env, s);
}
uint32_t addr;
addr = s->pc - 2;
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
if (ext != 0x46FC) {
gen_exception(s, addr, EXCP_UNSUPPORTED);
return;
}
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
if (IS_USER(s) || (ext & SR_S) == 0) {
gen_exception(s, addr, EXCP_PRIVILEGE);
return;
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return;
}
- /* TODO: Implement USP. */
- gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
+ tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
+ offsetof(CPUM68KState, sp[M68K_USP]));
}
DISAS_INSN(move_to_usp)
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return;
}
- /* TODO: Implement USP. */
- gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
+ tcg_gen_st_i32(AREG(insn, 0), cpu_env,
+ offsetof(CPUM68KState, sp[M68K_USP]));
}
DISAS_INSN(halt)
return;
}
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
gen_set_sr_im(s, ext, 0);
tcg_gen_movi_i32(cpu_halted, 1);
return;
}
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
if (ext & 0x8000) {
reg = AREG(ext, 12);
int set_dest;
int opsize;
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
opmode = ext & 0x7f;
switch ((ext >> 13) & 7) {
case 0: case 2:
mask = 0x80;
for (i = 0; i < 8; i++) {
if (ext & mask) {
- s->is_mem = 1;
dest = FREG(i, 0);
if (ext & (1 << 13)) {
/* store */
uint32_t offset;
uint32_t addr;
TCGv flag;
- int l1;
+ TCGLabel *l1;
addr = s->pc;
offset = cpu_ldsw_code(env, s->pc);
s->pc += 2;
if (insn & (1 << 6)) {
- offset = (offset << 16) | cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ offset = (offset << 16) | read_im16(env, s);
}
l1 = gen_new_label();
s->done_mac = 1;
}
- ext = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ ext = read_im16(env, s);
acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
if (s->env->macsr & MACSR_FI) {
gen_helper_get_macf(rx, cpu_env, acc);
} else if ((s->env->macsr & MACSR_OMC) == 0) {
- tcg_gen_trunc_i64_i32(rx, acc);
+ tcg_gen_extrl_i64_i32(rx, acc);
} else if (s->env->macsr & MACSR_SU) {
gen_helper_get_macs(rx, acc);
} else {
Later insn override earlier ones. */
void register_m68k_insns (CPUM68KState *env)
{
+ /* Build the opcode table only once to avoid
+ multithreading issues. */
+ if (opcode_table[0] != NULL) {
+ return;
+ }
+
+ /* use BASE() for instruction available
+ * for CF_ISA_A and M68000.
+ */
+#define BASE(name, opcode, mask) \
+ register_opcode(disas_##name, 0x##opcode, 0x##mask)
#define INSN(name, opcode, mask, feature) do { \
if (m68k_feature(env, M68K_FEATURE_##feature)) \
- register_opcode(disas_##name, 0x##opcode, 0x##mask); \
+ BASE(name, opcode, mask); \
} while(0)
- INSN(undef, 0000, 0000, CF_ISA_A);
+ BASE(undef, 0000, 0000);
INSN(arith_im, 0080, fff8, CF_ISA_A);
+ INSN(arith_im, 0000, ff00, M68000);
+ INSN(undef, 00c0, ffc0, M68000);
INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
- INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
- INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
- INSN(bitop_reg, 0180, f1c0, CF_ISA_A);
- INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);
+ BASE(bitop_reg, 0100, f1c0);
+ BASE(bitop_reg, 0140, f1c0);
+ BASE(bitop_reg, 0180, f1c0);
+ BASE(bitop_reg, 01c0, f1c0);
INSN(arith_im, 0280, fff8, CF_ISA_A);
+ INSN(arith_im, 0200, ff00, M68000);
+ INSN(undef, 02c0, ffc0, M68000);
INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
INSN(arith_im, 0480, fff8, CF_ISA_A);
+ INSN(arith_im, 0400, ff00, M68000);
+ INSN(undef, 04c0, ffc0, M68000);
+ INSN(arith_im, 0600, ff00, M68000);
+ INSN(undef, 06c0, ffc0, M68000);
INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
INSN(arith_im, 0680, fff8, CF_ISA_A);
- INSN(bitop_im, 0800, ffc0, CF_ISA_A);
- INSN(bitop_im, 0840, ffc0, CF_ISA_A);
- INSN(bitop_im, 0880, ffc0, CF_ISA_A);
- INSN(bitop_im, 08c0, ffc0, CF_ISA_A);
- INSN(arith_im, 0a80, fff8, CF_ISA_A);
INSN(arith_im, 0c00, ff38, CF_ISA_A);
- INSN(move, 1000, f000, CF_ISA_A);
- INSN(move, 2000, f000, CF_ISA_A);
- INSN(move, 3000, f000, CF_ISA_A);
+ INSN(arith_im, 0c00, ff00, M68000);
+ BASE(bitop_im, 0800, ffc0);
+ BASE(bitop_im, 0840, ffc0);
+ BASE(bitop_im, 0880, ffc0);
+ BASE(bitop_im, 08c0, ffc0);
+ INSN(arith_im, 0a80, fff8, CF_ISA_A);
+ INSN(arith_im, 0a00, ff00, M68000);
+ BASE(move, 1000, f000);
+ BASE(move, 2000, f000);
+ BASE(move, 3000, f000);
INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
INSN(negx, 4080, fff8, CF_ISA_A);
INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
- INSN(lea, 41c0, f1c0, CF_ISA_A);
- INSN(clr, 4200, ff00, CF_ISA_A);
- INSN(undef, 42c0, ffc0, CF_ISA_A);
+ INSN(move_from_sr, 40c0, ffc0, M68000);
+ BASE(lea, 41c0, f1c0);
+ BASE(clr, 4200, ff00);
+ BASE(undef, 42c0, ffc0);
INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
INSN(neg, 4480, fff8, CF_ISA_A);
- INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);
+ INSN(neg, 4400, ff00, M68000);
+ INSN(undef, 44c0, ffc0, M68000);
+ BASE(move_to_ccr, 44c0, ffc0);
INSN(not, 4680, fff8, CF_ISA_A);
+ INSN(not, 4600, ff00, M68000);
+ INSN(undef, 46c0, ffc0, M68000);
INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
- INSN(pea, 4840, ffc0, CF_ISA_A);
- INSN(swap, 4840, fff8, CF_ISA_A);
- INSN(movem, 48c0, fbc0, CF_ISA_A);
- INSN(ext, 4880, fff8, CF_ISA_A);
- INSN(ext, 48c0, fff8, CF_ISA_A);
- INSN(ext, 49c0, fff8, CF_ISA_A);
- INSN(tst, 4a00, ff00, CF_ISA_A);
+ BASE(pea, 4840, ffc0);
+ BASE(swap, 4840, fff8);
+ BASE(movem, 48c0, fbc0);
+ BASE(ext, 4880, fff8);
+ BASE(ext, 48c0, fff8);
+ BASE(ext, 49c0, fff8);
+ BASE(tst, 4a00, ff00);
INSN(tas, 4ac0, ffc0, CF_ISA_B);
+ INSN(tas, 4ac0, ffc0, M68000);
INSN(halt, 4ac8, ffff, CF_ISA_A);
INSN(pulse, 4acc, ffff, CF_ISA_A);
- INSN(illegal, 4afc, ffff, CF_ISA_A);
+ BASE(illegal, 4afc, ffff);
INSN(mull, 4c00, ffc0, CF_ISA_A);
+ INSN(mull, 4c00, ffc0, LONG_MULDIV);
INSN(divl, 4c40, ffc0, CF_ISA_A);
+ INSN(divl, 4c40, ffc0, LONG_MULDIV);
INSN(sats, 4c80, fff8, CF_ISA_B);
- INSN(trap, 4e40, fff0, CF_ISA_A);
- INSN(link, 4e50, fff8, CF_ISA_A);
- INSN(unlk, 4e58, fff8, CF_ISA_A);
+ BASE(trap, 4e40, fff0);
+ BASE(link, 4e50, fff8);
+ BASE(unlk, 4e58, fff8);
INSN(move_to_usp, 4e60, fff8, USP);
INSN(move_from_usp, 4e68, fff8, USP);
- INSN(nop, 4e71, ffff, CF_ISA_A);
- INSN(stop, 4e72, ffff, CF_ISA_A);
- INSN(rte, 4e73, ffff, CF_ISA_A);
- INSN(rts, 4e75, ffff, CF_ISA_A);
+ BASE(nop, 4e71, ffff);
+ BASE(stop, 4e72, ffff);
+ BASE(rte, 4e73, ffff);
+ BASE(rts, 4e75, ffff);
INSN(movec, 4e7b, ffff, CF_ISA_A);
- INSN(jump, 4e80, ffc0, CF_ISA_A);
+ BASE(jump, 4e80, ffc0);
INSN(jump, 4ec0, ffc0, CF_ISA_A);
INSN(addsubq, 5180, f1c0, CF_ISA_A);
+ INSN(jump, 4ec0, ffc0, M68000);
+ INSN(addsubq, 5000, f080, M68000);
+ INSN(addsubq, 5080, f0c0, M68000);
INSN(scc, 50c0, f0f8, CF_ISA_A);
INSN(addsubq, 5080, f1c0, CF_ISA_A);
INSN(tpf, 51f8, fff8, CF_ISA_A);
/* Branch instructions. */
- INSN(branch, 6000, f000, CF_ISA_A);
+ BASE(branch, 6000, f000);
/* Disable long branch instructions, then add back the ones we want. */
- INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */
+ BASE(undef, 60ff, f0ff); /* All long branches. */
INSN(branch, 60ff, f0ff, CF_ISA_B);
INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
INSN(branch, 60ff, ffff, BRAL);
+ INSN(branch, 60ff, f0ff, BCCL);
- INSN(moveq, 7000, f100, CF_ISA_A);
+ BASE(moveq, 7000, f100);
INSN(mvzs, 7100, f100, CF_ISA_B);
- INSN(or, 8000, f000, CF_ISA_A);
- INSN(divw, 80c0, f0c0, CF_ISA_A);
- INSN(addsub, 9000, f000, CF_ISA_A);
+ BASE(or, 8000, f000);
+ BASE(divw, 80c0, f0c0);
+ BASE(addsub, 9000, f000);
INSN(subx, 9180, f1f8, CF_ISA_A);
INSN(suba, 91c0, f1c0, CF_ISA_A);
- INSN(undef_mac, a000, f000, CF_ISA_A);
+ BASE(undef_mac, a000, f000);
INSN(mac, a000, f100, CF_EMAC);
INSN(from_mac, a180, f9b0, CF_EMAC);
INSN(move_mac, a110, f9fc, CF_EMAC);
INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
INSN(cmp, b080, f1c0, CF_ISA_A);
INSN(cmpa, b1c0, f1c0, CF_ISA_A);
+ INSN(cmp, b000, f100, M68000);
+ INSN(eor, b100, f100, M68000);
+ INSN(cmpa, b0c0, f0c0, M68000);
INSN(eor, b180, f1c0, CF_ISA_A);
- INSN(and, c000, f000, CF_ISA_A);
- INSN(mulw, c0c0, f0c0, CF_ISA_A);
- INSN(addsub, d000, f000, CF_ISA_A);
+ BASE(and, c000, f000);
+ BASE(mulw, c0c0, f0c0);
+ BASE(addsub, d000, f000);
INSN(addx, d180, f1f8, CF_ISA_A);
INSN(adda, d1c0, f1c0, CF_ISA_A);
+ INSN(adda, d0c0, f0c0, M68000);
INSN(shift_im, e080, f0f0, CF_ISA_A);
INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
INSN(undef_fpu, f000, f000, CF_ISA_A);
{
uint16_t insn;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
- tcg_gen_debug_insn_start(s->pc);
- }
-
- insn = cpu_lduw_code(env, s->pc);
- s->pc += 2;
+ insn = read_im16(env, s);
opcode_table[insn](env, s, insn);
}
/* generate intermediate code for basic block 'tb'. */
-static inline void
-gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
- bool search_pc)
+void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
{
+ M68kCPU *cpu = m68k_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- CPUM68KState *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
- uint16_t *gen_opc_end;
- CPUBreakpoint *bp;
- int j, lj;
target_ulong pc_start;
int pc_offset;
int num_insns;
dc->tb = tb;
- gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
-
dc->env = env;
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->singlestep_enabled = cs->singlestep_enabled;
dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
- dc->is_mem = 0;
dc->done_mac = 0;
- lj = -1;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0)
+ if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
- gen_tb_start();
+ gen_tb_start(tb);
do {
pc_offset = dc->pc - pc_start;
gen_throws_exception = NULL;
- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
- if (bp->pc == dc->pc) {
- gen_exception(dc, dc->pc, EXCP_DEBUG);
- dc->is_jmp = DISAS_JUMP;
- break;
- }
- }
- if (dc->is_jmp)
- break;
- }
- if (search_pc) {
- j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
- if (lj < j) {
- lj++;
- while (lj < j)
- tcg_ctx.gen_opc_instr_start[lj++] = 0;
- }
- tcg_ctx.gen_opc_pc[lj] = dc->pc;
- tcg_ctx.gen_opc_instr_start[lj] = 1;
- tcg_ctx.gen_opc_icount[lj] = num_insns;
+ tcg_gen_insn_start(dc->pc);
+ num_insns++;
+
+ if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ gen_exception(dc, dc->pc, EXCP_DEBUG);
+ dc->is_jmp = DISAS_JUMP;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->pc += 2;
+ break;
}
- if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
+
+ if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
+ }
+
dc->insn_pc = dc->pc;
disas_m68k_insn(env, dc);
- num_insns++;
- } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
+ } while (!dc->is_jmp && !tcg_op_buf_full() &&
!cs->singlestep_enabled &&
!singlestep &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
}
}
gen_tb_end(tb, num_insns);
- *tcg_ctx.gen_opc_ptr = INDEX_op_end;
#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
+ && qemu_log_in_addr_range(pc_start)) {
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(env, pc_start, dc->pc - pc_start, 0);
+ log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
qemu_log("\n");
}
#endif
- if (search_pc) {
- j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
- lj++;
- while (lj <= j)
- tcg_ctx.gen_opc_instr_start[lj++] = 0;
- } else {
- tb->size = dc->pc - pc_start;
- tb->icount = num_insns;
- }
-
- //optimize_flags();
- //expand_target_qops();
-}
-
-void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
-{
- gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, false);
-}
-
-void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb)
-{
- gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, true);
+ tb->size = dc->pc - pc_start;
+ tb->icount = num_insns;
}
void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
}
-void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
+ target_ulong *data)
{
- env->pc = tcg_ctx.gen_opc_pc[pc_pos];
+ env->pc = data[0];
}
projects / qemu.git / blobdiff