-/*
+/*
* Arm PrimeCell PL181 MultiMedia Card Interface
*
* Copyright (c) 2007 CodeSourcery.
* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "sysbus.h"
#include "sd.h"
+#include "sysemu.h"
//#define DEBUG_PL181 1
#ifdef DEBUG_PL181
-#define DPRINTF(fmt, args...) \
-do { printf("pl181: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...) \
+do { printf("pl181: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define DPRINTF(fmt, args...) do {} while(0)
+#define DPRINTF(fmt, ...) do {} while(0)
#endif
#define PL181_FIFO_LEN 16
typedef struct {
+ SysBusDevice busdev;
SDState *card;
- uint32_t base;
uint32_t clock;
uint32_t power;
uint32_t cmdarg;
static void pl181_send_command(pl181_state *s)
{
- struct sd_request_s request;
+ SDRequest request;
uint8_t response[16];
int rlen;
s->response[2] = RWORD(8);
s->response[3] = RWORD(12) & ~1;
}
- DPRINTF("Response recieved\n");
+ DPRINTF("Response received\n");
s->status |= PL181_STATUS_CMDRESPEND;
#undef RWORD
} else {
s->status |= PL181_STATUS_CMDTIMEOUT;
}
-/* Transfer data between teh card and the FIFO. This is complicated by
+/* Transfer data between the card and the FIFO. This is complicated by
the FIFO holding 32-bit words and the card taking data in single byte
chunks. FIFO bytes are transferred in little-endian order. */
-
+
static void pl181_fifo_run(pl181_state *s)
{
uint32_t bits;
}
}
-static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
+static uint32_t pl181_read(void *opaque, a_target_phys_addr offset)
{
pl181_state *s = (pl181_state *)opaque;
uint32_t tmp;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl181_id[(offset - 0xfe0) >> 2];
}
return value;
}
default:
- cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset);
+ hw_error("pl181_read: Bad offset %x\n", (int)offset);
return 0;
}
}
-static void pl181_write(void *opaque, target_phys_addr_t offset,
+static void pl181_write(void *opaque, a_target_phys_addr offset,
uint32_t value)
{
pl181_state *s = (pl181_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* Power */
s->power = value & 0xff;
}
break;
default:
- cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset);
+ hw_error("pl181_write: Bad offset %x\n", (int)offset);
}
pl181_update(s);
}
-static CPUReadMemoryFunc *pl181_readfn[] = {
+static CPUReadMemoryFunc * const pl181_readfn[] = {
pl181_read,
pl181_read,
pl181_read
};
-static CPUWriteMemoryFunc *pl181_writefn[] = {
+static CPUWriteMemoryFunc * const pl181_writefn[] = {
pl181_write,
pl181_write,
pl181_write
s->mask[1] = 0;
}
-void pl181_init(uint32_t base, BlockDriverState *bd,
- qemu_irq irq0, qemu_irq irq1)
+static int pl181_init(SysBusDevice *dev)
{
int iomemtype;
- pl181_state *s;
+ pl181_state *s = FROM_SYSBUS(pl181_state, dev);
+ BlockDriverState *bd;
- s = (pl181_state *)qemu_mallocz(sizeof(pl181_state));
- iomemtype = cpu_register_io_memory(0, pl181_readfn,
+ iomemtype = cpu_register_io_memory(pl181_readfn,
pl181_writefn, s);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
- s->card = sd_init(bd);
- s->irq[0] = irq0;
- s->irq[1] = irq1;
+ sysbus_init_mmio(dev, 0x1000, iomemtype);
+ sysbus_init_irq(dev, &s->irq[0]);
+ sysbus_init_irq(dev, &s->irq[1]);
+ bd = qdev_init_bdrv(&dev->qdev, IF_SD);
+ s->card = sd_init(bd, 0);
qemu_register_reset(pl181_reset, s);
pl181_reset(s);
/* ??? Save/restore. */
+ return 0;
}
+
+static void pl181_register_devices(void)
+{
+ sysbus_register_dev("pl181", sizeof(pl181_state), pl181_init);
+}
+
+device_init(pl181_register_devices)