Sparc64: fix PCI probe problems

[qemu.git] / hw / ppc405.h

diff --git a/hw/ppc405.h b/hw/ppc405.h
index b3f3b3d80647eeca62b7f284aaaf4f94ed366c87..e042a05b3b5fe3c945e112ce0b743120d57dccf6 100644 (file)
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -25,6 +25,8 @@
 #if !defined(PPC_405_H)
 #define PPC_405_H
 
+#include "ppc4xx.h"
+
 /* Bootinfo as set-up by u-boot */
 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
 struct ppc4xx_bd_info_t {
@@ -54,68 +56,17 @@ struct ppc4xx_bd_info_t {
 };
 
 /* PowerPC 405 core */
-CPUState *ppc405_init (const unsigned char *cpu_model,
-                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
-                       uint32_t sysclk);
-ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd);
+ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
+                                uint32_t flags);
 
-/* */
-typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
-int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
-                          target_phys_addr_t offset, uint32_t len,
-                          CPUReadMemoryFunc **mem_read,
-                          CPUWriteMemoryFunc **mem_write, void *opaque);
-ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
-/* PowerPC 4xx peripheral local bus arbitrer */
-void ppc4xx_plb_init (CPUState *env);
-/* PLB to OPB bridge */
-void ppc4xx_pob_init (CPUState *env);
-/* OPB arbitrer */
-void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
-                       target_phys_addr_t offset);
-/* PowerPC 4xx universal interrupt controller */
-enum {
-    PPCUIC_OUTPUT_INT = 0,
-    PPCUIC_OUTPUT_CINT = 1,
-    PPCUIC_OUTPUT_NB,
-};
-qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
-                       uint32_t dcr_base, int has_ssr, int has_vr);
-/* SDRAM controller */
-void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
-                        target_phys_addr_t *ram_bases,
-                        target_phys_addr_t *ram_sizes,
-                        int do_init);
-/* Peripheral controller */
-void ppc405_ebc_init (CPUState *env);
-/* DMA controller */
-void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
-/* GPIO */
-void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
-                       target_phys_addr_t offset);
-/* Serial ports */
-void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
-                         target_phys_addr_t offset, qemu_irq irq,
-                         CharDriverState *chr);
-/* On Chip Memory */
-void ppc405_ocm_init (CPUState *env, unsigned long offset);
-/* I2C controller */
-void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
-                      target_phys_addr_t offset, qemu_irq irq);
-/* General purpose timers */
-void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
-                      target_phys_addr_t offset, qemu_irq irq[5]);
-/* Memory access layer */
-void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
-/* PowerPC 405 microcontrollers */
 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
                          target_phys_addr_t ram_sizes[4],
                          uint32_t sysclk, qemu_irq **picp,
-                         ram_addr_t *offsetp, int do_init);
+                         int do_init);
 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
                          target_phys_addr_t ram_sizes[2],
                          uint32_t sysclk, qemu_irq **picp,
-                         ram_addr_t *offsetp, int do_init);
+                         int do_init);
 /* IBM STBxxx microcontrollers */
 CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
                            target_phys_addr_t ram_sizes[2],