/*
- * PPC emulation helpers for qemu.
- *
- * Copyright (c) 2003 Jocelyn Mayer
+ * PowerPC emulation helpers for qemu.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include "exec.h"
-#if defined (USE_OPEN_FIRMWARE)
-#include <time.h>
-#include "of.h"
-#endif
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <signal.h>
+#include <assert.h>
+
+#include "cpu.h"
+#include "exec-all.h"
//#define DEBUG_MMU
//#define DEBUG_BATS
+//#define DEBUG_SOFTWARE_TLB
//#define DEBUG_EXCEPTIONS
+//#define FLUSH_ALL_TLBS
-extern FILE *logfile, *stdout, *stderr;
-void exit (int);
-void abort (void);
+/*****************************************************************************/
+/* PowerPC MMU emulation */
-void cpu_loop_exit(void)
+#if defined(CONFIG_USER_ONLY)
+int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu)
{
- longjmp(env->jmp_env, 1);
+ int exception, error_code;
+
+ if (rw == 2) {
+ exception = POWERPC_EXCP_ISI;
+ error_code = 0;
+ } else {
+ exception = POWERPC_EXCP_DSI;
+ error_code = 0;
+ if (rw)
+ error_code |= 0x02000000;
+ env->spr[SPR_DAR] = address;
+ env->spr[SPR_DSISR] = error_code;
+ }
+ env->exception_index = exception;
+ env->error_code = error_code;
+
+ return 1;
}
-void do_process_exceptions (void)
+target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
{
- cpu_loop_exit();
+ return addr;
}
-int check_exception_state (CPUState *env)
+#else
+/* Common routines used by software and hardware TLBs emulation */
+static inline int pte_is_valid (target_ulong pte0)
{
- int i;
+ return pte0 & 0x80000000 ? 1 : 0;
+}
- /* Process PPC exceptions */
- for (i = 1; i < EXCP_PPC_MAX; i++) {
- if (env->exceptions & (1 << i)) {
- switch (i) {
- case EXCP_EXTERNAL:
- case EXCP_DECR:
- if (msr_ee == 0)
- return 0;
- break;
- case EXCP_PROGRAM:
- if (env->errors[EXCP_PROGRAM] == EXCP_FP &&
- msr_fe0 == 0 && msr_fe1 == 0)
- return 0;
- break;
- default:
- break;
+static inline void pte_invalidate (target_ulong *pte0)
+{
+ *pte0 &= ~0x80000000;
+}
+
+#if defined(TARGET_PPC64)
+static inline int pte64_is_valid (target_ulong pte0)
+{
+ return pte0 & 0x0000000000000001ULL ? 1 : 0;
+}
+
+static inline void pte64_invalidate (target_ulong *pte0)
+{
+ *pte0 &= ~0x0000000000000001ULL;
+}
+#endif
+
+#define PTE_PTEM_MASK 0x7FFFFFBF
+#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
+#if defined(TARGET_PPC64)
+#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
+#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
+#endif
+
+static inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
+ target_ulong pte0, target_ulong pte1,
+ int h, int rw)
+{
+ target_ulong ptem, mmask;
+ int access, ret, pteh, ptev;
+
+ access = 0;
+ ret = -1;
+ /* Check validity and table match */
+#if defined(TARGET_PPC64)
+ if (is_64b) {
+ ptev = pte64_is_valid(pte0);
+ pteh = (pte0 >> 1) & 1;
+ } else
+#endif
+ {
+ ptev = pte_is_valid(pte0);
+ pteh = (pte0 >> 6) & 1;
+ }
+ if (ptev && h == pteh) {
+ /* Check vsid & api */
+#if defined(TARGET_PPC64)
+ if (is_64b) {
+ ptem = pte0 & PTE64_PTEM_MASK;
+ mmask = PTE64_CHECK_MASK;
+ } else
+#endif
+ {
+ ptem = pte0 & PTE_PTEM_MASK;
+ mmask = PTE_CHECK_MASK;
+ }
+ if (ptem == ctx->ptem) {
+ if (ctx->raddr != (target_ulong)-1) {
+ /* all matches should have equal RPN, WIMG & PP */
+ if ((ctx->raddr & mmask) != (pte1 & mmask)) {
+ if (loglevel != 0)
+ fprintf(logfile, "Bad RPN/WIMG/PP\n");
+ return -3;
+ }
+ }
+ /* Compute access rights */
+ if (ctx->key == 0) {
+ access = PAGE_READ;
+ if ((pte1 & 0x00000003) != 0x3)
+ access |= PAGE_WRITE;
+ } else {
+ switch (pte1 & 0x00000003) {
+ case 0x0:
+ access = 0;
+ break;
+ case 0x1:
+ case 0x3:
+ access = PAGE_READ;
+ break;
+ case 0x2:
+ access = PAGE_READ | PAGE_WRITE;
+ break;
+ }
+ }
+ /* Keep the matching PTE informations */
+ ctx->raddr = pte1;
+ ctx->prot = access;
+ if ((rw == 0 && (access & PAGE_READ)) ||
+ (rw == 1 && (access & PAGE_WRITE))) {
+ /* Access granted */
+#if defined (DEBUG_MMU)
+ if (loglevel != 0)
+ fprintf(logfile, "PTE access granted !\n");
+#endif
+ ret = 0;
+ } else {
+ /* Access right violation */
+#if defined (DEBUG_MMU)
+ if (loglevel != 0)
+ fprintf(logfile, "PTE access rejected\n");
+#endif
+ ret = -2;
}
- env->exception_index = i;
- env->error_code = env->errors[i];
- return 1;
}
}
- return 0;
+ return ret;
}
-/*****************************************************************************/
-/* PPC MMU emulation */
-int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
- int is_user, int is_softmmu);
+static int pte32_check (mmu_ctx_t *ctx,
+ target_ulong pte0, target_ulong pte1, int h, int rw)
+{
+ return _pte_check(ctx, 0, pte0, pte1, h, rw);
+}
+
+#if defined(TARGET_PPC64)
+static int pte64_check (mmu_ctx_t *ctx,
+ target_ulong pte0, target_ulong pte1, int h, int rw)
+{
+ return _pte_check(ctx, 1, pte0, pte1, h, rw);
+}
+#endif
+
+static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
+ int ret, int rw)
+{
+ int store = 0;
+
+ /* Update page flags */
+ if (!(*pte1p & 0x00000100)) {
+ /* Update accessed flag */
+ *pte1p |= 0x00000100;
+ store = 1;
+ }
+ if (!(*pte1p & 0x00000080)) {
+ if (rw == 1 && ret == 0) {
+ /* Update changed flag */
+ *pte1p |= 0x00000080;
+ store = 1;
+ } else {
+ /* Force page fault for first write access */
+ ctx->prot &= ~PAGE_WRITE;
+ }
+ }
+
+ return store;
+}
+
+/* Software driven TLB helpers */
+static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
+ int way, int is_code)
+{
+ int nr;
+
+ /* Select TLB num in a way from address */
+ nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
+ /* Select TLB way */
+ nr += env->tlb_per_way * way;
+ /* 6xx have separate TLBs for instructions and data */
+ if (is_code && env->id_tlbs == 1)
+ nr += env->nb_tlb;
+
+ return nr;
+}
+
+void ppc6xx_tlb_invalidate_all (CPUState *env)
+{
+ ppc6xx_tlb_t *tlb;
+ int nr, max;
+
+#if defined (DEBUG_SOFTWARE_TLB) && 0
+ if (loglevel != 0) {
+ fprintf(logfile, "Invalidate all TLBs\n");
+ }
+#endif
+ /* Invalidate all defined software TLB */
+ max = env->nb_tlb;
+ if (env->id_tlbs == 1)
+ max *= 2;
+ for (nr = 0; nr < max; nr++) {
+ tlb = &env->tlb[nr].tlb6;
+#if !defined(FLUSH_ALL_TLBS)
+ tlb_flush_page(env, tlb->EPN);
+#endif
+ pte_invalidate(&tlb->pte0);
+ }
+#if defined(FLUSH_ALL_TLBS)
+ tlb_flush(env, 1);
+#endif
+}
+
+static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
+ target_ulong eaddr,
+ int is_code, int match_epn)
+{
+#if !defined(FLUSH_ALL_TLBS)
+ ppc6xx_tlb_t *tlb;
+ int way, nr;
+
+ /* Invalidate ITLB + DTLB, all ways */
+ for (way = 0; way < env->nb_ways; way++) {
+ nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
+ tlb = &env->tlb[nr].tlb6;
+ if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
+ nr, env->nb_tlb, eaddr);
+ }
+#endif
+ pte_invalidate(&tlb->pte0);
+ tlb_flush_page(env, tlb->EPN);
+ }
+ }
+#else
+ /* XXX: PowerPC specification say this is valid as well */
+ ppc6xx_tlb_invalidate_all(env);
+#endif
+}
+
+void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
+ int is_code)
+{
+ __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
+}
+
+void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
+ target_ulong pte0, target_ulong pte1)
+{
+ ppc6xx_tlb_t *tlb;
+ int nr;
+
+ nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
+ tlb = &env->tlb[nr].tlb6;
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
+ " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
+ }
+#endif
+ /* Invalidate any pending reference in Qemu for this virtual address */
+ __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
+ tlb->pte0 = pte0;
+ tlb->pte1 = pte1;
+ tlb->EPN = EPN;
+ /* Store last way for LRU mechanism */
+ env->last_way = way;
+}
+
+static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
+{
+ ppc6xx_tlb_t *tlb;
+ int nr, best, way;
+ int ret;
+
+ best = -1;
+ ret = -1; /* No TLB found */
+ for (way = 0; way < env->nb_ways; way++) {
+ nr = ppc6xx_tlb_getnum(env, eaddr, way,
+ access_type == ACCESS_CODE ? 1 : 0);
+ tlb = &env->tlb[nr].tlb6;
+ /* This test "emulates" the PTE index match for hardware TLBs */
+ if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
+ "] <> " ADDRX "\n",
+ nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
+ }
+#endif
+ continue;
+ }
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
+ " %c %c\n",
+ nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, eaddr, tlb->pte1,
+ rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
+ }
+#endif
+ switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
+ case -3:
+ /* TLB inconsistency */
+ return -1;
+ case -2:
+ /* Access violation */
+ ret = -2;
+ best = nr;
+ break;
+ case -1:
+ default:
+ /* No match */
+ break;
+ case 0:
+ /* access granted */
+ /* XXX: we should go on looping to check all TLBs consistency
+ * but we can speed-up the whole thing as the
+ * result would be undefined if TLBs are not consistent.
+ */
+ ret = 0;
+ best = nr;
+ goto done;
+ }
+ }
+ if (best != -1) {
+ done:
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
+ ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
+ }
+#endif
+ /* Update page flags */
+ pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
+ }
+
+ return ret;
+}
/* Perform BAT hit & translation */
-static int get_bat (CPUState *env, uint32_t *real, int *prot,
- uint32_t virtual, int rw, int type)
+static int get_bat (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong virtual, int rw, int type)
{
- uint32_t *BATlt, *BATut, *BATu, *BATl;
- uint32_t base, BEPIl, BEPIu, bl;
+ target_ulong *BATlt, *BATut, *BATu, *BATl;
+ target_ulong base, BEPIl, BEPIu, bl;
int i;
int ret = -1;
#if defined (DEBUG_BATS)
- if (loglevel > 0) {
- fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', virtual);
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
+ type == ACCESS_CODE ? 'I' : 'D', virtual);
}
#endif
switch (type) {
break;
}
#if defined (DEBUG_BATS)
- if (loglevel > 0) {
- fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', virtual);
+ if (loglevel != 0) {
+ fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
+ type == ACCESS_CODE ? 'I' : 'D', virtual);
}
#endif
base = virtual & 0xFFFC0000;
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
#if defined (DEBUG_BATS)
- if (loglevel > 0) {
- fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
+ " BATl 0x" ADDRX "\n",
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
*BATu, *BATl);
}
if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
(msr_pr == 1 && (*BATu & 0x00000001))) {
/* Get physical address */
- *real = (*BATl & 0xF0000000) |
+ ctx->raddr = (*BATl & 0xF0000000) |
((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
(virtual & 0x0001F000);
if (*BATl & 0x00000001)
- *prot = PAGE_READ;
+ ctx->prot = PAGE_READ;
if (*BATl & 0x00000002)
- *prot = PAGE_WRITE | PAGE_READ;
+ ctx->prot = PAGE_WRITE | PAGE_READ;
#if defined (DEBUG_BATS)
- if (loglevel > 0) {
- fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
- i, *real, *prot & PAGE_READ ? 'R' : '-',
- *prot & PAGE_WRITE ? 'W' : '-');
+ if (loglevel != 0) {
+ fprintf(logfile, "BAT %d match: r 0x" PADDRX
+ " prot=%c%c\n",
+ i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
+ ctx->prot & PAGE_WRITE ? 'W' : '-');
}
#endif
ret = 0;
}
if (ret < 0) {
#if defined (DEBUG_BATS)
- printf("no BAT match for 0x%08x:\n", virtual);
- for (i = 0; i < 4; i++) {
- BATu = &BATut[i];
- BATl = &BATlt[i];
- BEPIu = *BATu & 0xF0000000;
- BEPIl = *BATu & 0x0FFE0000;
- bl = (*BATu & 0x00001FFC) << 15;
- printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
- "0x%08x 0x%08x 0x%08x\n",
- __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
- *BATu, *BATl, BEPIu, BEPIl, bl);
+ if (loglevel != 0) {
+ fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
+ for (i = 0; i < 4; i++) {
+ BATu = &BATut[i];
+ BATl = &BATlt[i];
+ BEPIu = *BATu & 0xF0000000;
+ BEPIl = *BATu & 0x0FFE0000;
+ bl = (*BATu & 0x00001FFC) << 15;
+ fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
+ " BATl 0x" ADDRX " \n\t"
+ "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
+ __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
+ *BATu, *BATl, BEPIu, BEPIl, bl);
+ }
}
#endif
}
}
/* PTE table lookup */
-static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
- int h, int key, int rw)
+static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
{
- uint32_t pte0, pte1, keep = 0, access = 0;
- int i, good = -1, store = 0;
- int ret = -1; /* No entry found */
+ target_ulong base, pte0, pte1;
+ int i, good = -1;
+ int ret, r;
+ ret = -1; /* No entry found */
+ base = ctx->pg_addr[h];
for (i = 0; i < 8; i++) {
- pte0 = ldl_raw(phys_ram_base + base + (i * 8));
- pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
-#if defined (DEBUG_MMU)
- if (loglevel > 0) {
- fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
- "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
- pte0 >> 31, h, (pte0 >> 6) & 1, va);
- }
-#endif
- /* Check validity and table match */
- if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
- /* Check vsid & api */
- if ((pte0 & 0x7FFFFFBF) == va) {
- if (good == -1) {
- good = i;
- keep = pte1;
- } else {
- /* All matches should have equal RPN, WIMG & PP */
- if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
- if (loglevel > 0)
- fprintf(logfile, "Bad RPN/WIMG/PP\n");
- return -1;
- }
- }
- /* Check access rights */
- if (key == 0) {
- access = PAGE_READ;
- if ((pte1 & 0x00000003) != 0x3)
- access |= PAGE_WRITE;
- } else {
- switch (pte1 & 0x00000003) {
- case 0x0:
- access = 0;
- break;
- case 0x1:
- case 0x3:
- access = PAGE_READ;
- break;
- case 0x2:
- access = PAGE_READ | PAGE_WRITE;
- break;
- }
- }
- if (ret < 0) {
- if ((rw == 0 && (access & PAGE_READ)) ||
- (rw == 1 && (access & PAGE_WRITE))) {
-#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "PTE access granted !\n");
+#if defined(TARGET_PPC64)
+ if (is_64b) {
+ pte0 = ldq_phys(base + (i * 16));
+ pte1 = ldq_phys(base + (i * 16) + 8);
+ r = pte64_check(ctx, pte0, pte1, h, rw);
+ } else
#endif
- good = i;
- keep = pte1;
- ret = 0;
- } else {
- /* Access right violation */
- ret = -2;
+ {
+ pte0 = ldl_phys(base + (i * 8));
+ pte1 = ldl_phys(base + (i * 8) + 4);
+ r = pte32_check(ctx, pte0, pte1, h, rw);
+ }
#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "PTE access rejected\n");
+ if (loglevel != 0) {
+ fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
+ " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
+ base + (i * 8), pte0, pte1,
+ (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem);
+ }
#endif
- }
- *prot = access;
- }
- }
+ switch (r) {
+ case -3:
+ /* PTE inconsistency */
+ return -1;
+ case -2:
+ /* Access violation */
+ ret = -2;
+ good = i;
+ break;
+ case -1:
+ default:
+ /* No PTE match */
+ break;
+ case 0:
+ /* access granted */
+ /* XXX: we should go on looping to check all PTEs consistency
+ * but if we can speed-up the whole thing as the
+ * result would be undefined if PTEs are not consistent.
+ */
+ ret = 0;
+ good = i;
+ goto done;
}
}
if (good != -1) {
- *RPN = keep & 0xFFFFF000;
+ done:
#if defined (DEBUG_MMU)
- if (loglevel > 0) {
- fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
- *RPN, *prot, ret);
- }
+ if (loglevel != 0) {
+ fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
+ "ret=%d\n",
+ ctx->raddr, ctx->prot, ret);
+ }
#endif
/* Update page flags */
- if (!(keep & 0x00000100)) {
- /* Access flag */
- keep |= 0x00000100;
- store = 1;
- }
- if (!(keep & 0x00000080)) {
- if (rw && ret == 0) {
- /* Change flag */
- keep |= 0x00000080;
- store = 1;
- } else {
- /* Force page fault for first write access */
- *prot &= ~PAGE_WRITE;
+ pte1 = ctx->raddr;
+ if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
+#if defined(TARGET_PPC64)
+ if (is_64b) {
+ stq_phys_notdirty(base + (good * 16) + 8, pte1);
+ } else
+#endif
+ {
+ stl_phys_notdirty(base + (good * 8) + 4, pte1);
}
}
- if (store) {
- stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
- }
}
return ret;
}
-static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
+static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
{
- return (sdr1 & 0xFFFF0000) | (hash & mask);
+ return _find_pte(ctx, 0, h, rw);
}
-/* Perform segment based translation */
-static int get_segment (CPUState *env, uint32_t *real, int *prot,
- uint32_t virtual, int rw, int type)
+#if defined(TARGET_PPC64)
+static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
+{
+ return _find_pte(ctx, 1, h, rw);
+}
+#endif
+
+static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw)
{
- uint32_t pg_addr, sdr, ptem, vsid, pgidx;
- uint32_t hash, mask;
- uint32_t sr;
- int key;
- int ret = -1, ret2;
+#if defined(TARGET_PPC64)
+ if (env->mmu_model == POWERPC_MMU_64B ||
+ env->mmu_model == POWERPC_MMU_64BRIDGE)
+ return find_pte64(ctx, h, rw);
+#endif
- sr = env->sr[virtual >> 28];
-#if defined (DEBUG_MMU)
- if (loglevel > 0) {
- fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
- "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
- virtual, virtual >> 28, sr, env->nip,
- env->lr, msr_ir, msr_dr, msr_pr, rw, type);
+ return find_pte32(ctx, h, rw);
+}
+
+static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
+ int sdr_sh,
+ target_phys_addr_t hash,
+ target_phys_addr_t mask)
+{
+ return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
+}
+
+#if defined(TARGET_PPC64)
+static int slb_lookup (CPUState *env, target_ulong eaddr,
+ target_ulong *vsid, target_ulong *page_mask, int *attr)
+{
+ target_phys_addr_t sr_base;
+ target_ulong mask;
+ uint64_t tmp64;
+ uint32_t tmp;
+ int n, ret;
+ int slb_nr;
+
+ ret = -5;
+ sr_base = env->spr[SPR_ASR];
+ mask = 0x0000000000000000ULL; /* Avoid gcc warning */
+#if 0 /* XXX: Fix this */
+ slb_nr = env->slb_nr;
+#else
+ slb_nr = 32;
+#endif
+ for (n = 0; n < slb_nr; n++) {
+ tmp64 = ldq_phys(sr_base);
+ if (tmp64 & 0x0000000008000000ULL) {
+ /* SLB entry is valid */
+ switch (tmp64 & 0x0000000006000000ULL) {
+ case 0x0000000000000000ULL:
+ /* 256 MB segment */
+ mask = 0xFFFFFFFFF0000000ULL;
+ break;
+ case 0x0000000002000000ULL:
+ /* 1 TB segment */
+ mask = 0xFFFF000000000000ULL;
+ break;
+ case 0x0000000004000000ULL:
+ case 0x0000000006000000ULL:
+ /* Reserved => segment is invalid */
+ continue;
+ }
+ if ((eaddr & mask) == (tmp64 & mask)) {
+ /* SLB match */
+ tmp = ldl_phys(sr_base + 8);
+ *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
+ *page_mask = ~mask;
+ *attr = tmp & 0xFF;
+ ret = 0;
+ break;
+ }
+ }
+ sr_base += 12;
}
+
+ return ret;
+}
+#endif /* defined(TARGET_PPC64) */
+
+/* Perform segment based translation */
+static int get_segment (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
+{
+ target_phys_addr_t sdr, hash, mask, sdr_mask;
+ target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
+#if defined(TARGET_PPC64)
+ int attr;
#endif
- key = (((sr & 0x20000000) && msr_pr == 1) ||
- ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
- if ((sr & 0x80000000) == 0) {
+ int ds, nx, vsid_sh, sdr_sh;
+ int ret, ret2;
+
+#if defined(TARGET_PPC64)
+ if (env->mmu_model == POWERPC_MMU_64B) {
+ ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
+ if (ret < 0)
+ return ret;
+ ctx->key = ((attr & 0x40) && msr_pr == 1) ||
+ ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
+ ds = 0;
+ nx = attr & 0x20 ? 1 : 0;
+ vsid_mask = 0x00003FFFFFFFFF80ULL;
+ vsid_sh = 7;
+ sdr_sh = 18;
+ sdr_mask = 0x3FF80;
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ sr = env->sr[eaddr >> 28];
+ page_mask = 0x0FFFFFFF;
+ ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
+ ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
+ ds = sr & 0x80000000 ? 1 : 0;
+ nx = sr & 0x10000000 ? 1 : 0;
+ vsid = sr & 0x00FFFFFF;
+ vsid_mask = 0x01FFFFC0;
+ vsid_sh = 6;
+ sdr_sh = 16;
+ sdr_mask = 0xFFC0;
#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
- key, sr & 0x10000000);
+ if (loglevel != 0) {
+ fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
+ " nip=0x" ADDRX " lr=0x" ADDRX
+ " ir=%d dr=%d pr=%d %d t=%d\n",
+ eaddr, (int)(eaddr >> 28), sr, env->nip,
+ env->lr, msr_ir, msr_dr, msr_pr, rw, type);
+ }
+ if (!ds && loglevel != 0) {
+ fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
+ ctx->key, sr & 0x10000000);
+ }
#endif
+ }
+ ret = -1;
+ if (!ds) {
/* Check if instruction fetch is allowed, if needed */
- if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
+ if (type != ACCESS_CODE || nx == 0) {
/* Page address translation */
- vsid = sr & 0x00FFFFFF;
- pgidx = (virtual >> 12) & 0xFFFF;
+ pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
+ hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
+ /* Primary table address */
sdr = env->sdr1;
- hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
- mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
- pg_addr = get_pgaddr(sdr, hash, mask);
- ptem = (vsid << 7) | (pgidx >> 10);
+ mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
+ ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
+ /* Secondary table address */
+ hash = (~hash) & vsid_mask;
+ ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
+#if defined(TARGET_PPC64)
+ if (env->mmu_model == POWERPC_MMU_64B ||
+ env->mmu_model == POWERPC_MMU_64BRIDGE) {
+ /* Only 5 bits of the page index are used in the AVPN */
+ ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
+ } else
+#endif
+ {
+ ctx->ptem = (vsid << 7) | (pgidx >> 10);
+ }
+ /* Initialize real address with an invalid value */
+ ctx->raddr = (target_ulong)-1;
+ if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
+ /* Software TLB search */
+ ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
+ } else {
#if defined (DEBUG_MMU)
- if (loglevel > 0) {
- fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
- "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
- pg_addr);
- }
-#endif
- /* Primary table lookup */
- ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
- if (ret < 0) {
- /* Secondary table lookup */
- hash = (~hash) & 0x01FFFFC0;
- pg_addr = get_pgaddr(sdr, hash, mask);
+ if (loglevel != 0) {
+ fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
+ "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
+ sdr, (uint32_t)vsid, (uint32_t)pgidx,
+ (uint32_t)hash, ctx->pg_addr[0]);
+ }
+#endif
+ /* Primary table lookup */
+ ret = find_pte(env, ctx, 0, rw);
+ if (ret < 0) {
+ /* Secondary table lookup */
#if defined (DEBUG_MMU)
- if (virtual != 0xEFFFFFFF && loglevel > 0) {
- fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
- "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
- hash, pg_addr);
- }
-#endif
- ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
- if (ret2 != -1)
- ret = ret2;
+ if (eaddr != 0xEFFFFFFF && loglevel != 0) {
+ fprintf(logfile,
+ "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
+ "hash=0x%05x pg_addr=0x" PADDRX "\n",
+ sdr, (uint32_t)vsid, (uint32_t)pgidx,
+ (uint32_t)hash, ctx->pg_addr[1]);
+ }
+#endif
+ ret2 = find_pte(env, ctx, 1, rw);
+ if (ret2 != -1)
+ ret = ret2;
+ }
}
} else {
#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "No access allowed\n");
+ if (loglevel != 0)
+ fprintf(logfile, "No access allowed\n");
#endif
- ret = -3;
+ ret = -3;
}
} else {
#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "direct store...\n");
+ if (loglevel != 0)
+ fprintf(logfile, "direct store...\n");
#endif
/* Direct-store segment : absolutely *BUGGY* for now */
switch (type) {
/* Should make the instruction do no-op.
* As it already do no-op, it's quite easy :-)
*/
- *real = virtual;
+ ctx->raddr = eaddr;
return 0;
case ACCESS_EXT:
/* eciwx or ecowx */
fprintf(logfile, "ERROR: instruction should not need "
"address translation\n");
}
- printf("ERROR: instruction should not need "
- "address translation\n");
return -4;
}
- if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
- *real = virtual;
+ if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
+ ctx->raddr = eaddr;
ret = 2;
} else {
ret = -2;
return ret;
}
-int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
- uint32_t address, int rw, int access_type)
+/* Generic TLB check function for embedded PowerPC implementations */
+static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
+ target_phys_addr_t *raddrp,
+ target_ulong address,
+ uint32_t pid, int ext, int i)
{
- int ret;
+ target_ulong mask;
- if (loglevel > 0) {
- fprintf(logfile, "%s\n", __func__);
- }
-
- if ((access_type == ACCESS_CODE && msr_ir == 0) || msr_dr == 0) {
- /* No address translation */
- *physical = address & ~0xFFF;
- *prot = PAGE_READ | PAGE_WRITE;
- ret = 0;
- } else {
- /* Try to find a BAT */
- ret = get_bat(env, physical, prot, address, rw, access_type);
- if (ret < 0) {
- /* We didn't match any BAT entry */
- ret = get_segment(env, physical, prot, address, rw, access_type);
- }
+ /* Check valid flag */
+ if (!(tlb->prot & PAGE_VALID)) {
+ if (loglevel != 0)
+ fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
+ return -1;
}
- if (loglevel > 0) {
- fprintf(logfile, "%s address %08x => %08x\n",
- __func__, address, *physical);
+ mask = ~(tlb->size - 1);
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
+ ADDRX " " ADDRX " %d\n",
+ __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
}
-
- return ret;
-}
-
-#if defined(CONFIG_USER_ONLY)
-target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
-{
- return addr;
-}
-#else
-target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
-{
- uint32_t phys_addr;
- int prot;
-
- if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
+ /* Check PID */
+ if (tlb->PID != 0 && tlb->PID != pid)
return -1;
- return phys_addr;
-}
+ /* Check effective address */
+ if ((address & mask) != tlb->EPN)
+ return -1;
+ *raddrp = (tlb->RPN & mask) | (address & ~mask);
+#if (TARGET_PHYS_ADDR_BITS >= 36)
+ if (ext) {
+ /* Extend the physical address to 36 bits */
+ *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
+ }
#endif
-#if !defined(CONFIG_USER_ONLY)
-
-#define MMUSUFFIX _mmu
-#define GETPC() (__builtin_return_address(0))
-
-#define SHIFT 0
-#include "softmmu_template.h"
+ return 0;
+}
-#define SHIFT 1
-#include "softmmu_template.h"
+/* Generic TLB search function for PowerPC embedded implementations */
+int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
+{
+ ppcemb_tlb_t *tlb;
+ target_phys_addr_t raddr;
+ int i, ret;
-#define SHIFT 2
-#include "softmmu_template.h"
+ /* Default return value is no match */
+ ret = -1;
+ for (i = 0; i < env->nb_tlb; i++) {
+ tlb = &env->tlb[i].tlbe;
+ if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
+ ret = i;
+ break;
+ }
+ }
-#define SHIFT 3
-#include "softmmu_template.h"
+ return ret;
+}
-/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
+void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
+ uint32_t pid)
{
- TranslationBlock *tb;
- CPUState *saved_env;
- unsigned long pc;
- int ret;
+ ppcemb_tlb_t *tlb;
+ target_phys_addr_t raddr;
+ target_ulong page, end;
+ int i;
- /* XXX: hack to restore env in all cases, even if not called from
- generated code */
- saved_env = env;
- env = cpu_single_env;
- {
- unsigned long tlb_addrr, tlb_addrw;
- int index;
- index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- tlb_addrr = env->tlb_read[is_user][index].address;
- tlb_addrw = env->tlb_write[is_user][index].address;
-#if 0
- printf("%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
- "(0x%08lx 0x%08lx)\n", __func__, env,
- &env->tlb_read[is_user][index], index, addr,
- tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
- tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
-#endif
- }
- ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
- if (ret) {
- if (retaddr) {
- /* now we have a real cpu fault */
- pc = (unsigned long)retaddr;
- tb = tb_find_pc(pc);
- if (tb) {
- /* the PC is inside the translated code. It means that we have
- a virtual CPU fault */
- cpu_restore_state(tb, env, pc, NULL);
- }
+ for (i = 0; i < env->nb_tlb; i++) {
+ tlb = &env->tlb[i].tlbe;
+ if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
+ end = tlb->EPN + tlb->size;
+ for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
+ tlb_flush_page(env, page);
+ tlb->prot &= ~PAGE_VALID;
+ break;
}
- do_queue_exception_err(env->exception_index, env->error_code);
- do_process_exceptions();
- }
- {
- unsigned long tlb_addrr, tlb_addrw;
- int index;
- index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- tlb_addrr = env->tlb_read[is_user][index].address;
- tlb_addrw = env->tlb_write[is_user][index].address;
-#if 0
- printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
- "(0x%08lx 0x%08lx)\n", __func__, env,
- &env->tlb_read[is_user][index], index, addr,
- tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
- tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
-#endif
}
- env = saved_env;
}
-void cpu_ppc_init_mmu(CPUState *env)
+/* Helpers specific to PowerPC 40x implementations */
+void ppc4xx_tlb_invalidate_all (CPUState *env)
{
- /* Nothing to do: all translation are disabled */
-}
+ ppcemb_tlb_t *tlb;
+ int i;
+
+ for (i = 0; i < env->nb_tlb; i++) {
+ tlb = &env->tlb[i].tlbe;
+ if (tlb->prot & PAGE_VALID) {
+#if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
+ end = tlb->EPN + tlb->size;
+ for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
+ tlb_flush_page(env, page);
#endif
+ tlb->prot &= ~PAGE_VALID;
+ }
+ }
+ tlb_flush(env, 1);
+}
-/* Perform address translation */
-int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
- int is_user, int is_softmmu)
+int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong address, int rw, int access_type)
{
- uint32_t physical;
- int prot;
- int exception = 0, error_code = 0;
- int access_type;
- int ret = 0;
+ ppcemb_tlb_t *tlb;
+ target_phys_addr_t raddr;
+ int i, ret, zsel, zpr;
-// printf("%s 0\n", __func__);
- access_type = env->access_type;
- if (env->user_mode_only) {
- /* user mode only emulation */
- ret = -2;
- goto do_fault;
- }
- /* NASTY BUG workaround */
- if (access_type == ACCESS_CODE && rw) {
- printf("%s: ERROR WRITE CODE ACCESS\n", __func__);
- access_type = ACCESS_INT;
- }
- ret = get_physical_address(env, &physical, &prot,
- address, rw, access_type);
- if (ret == 0) {
- ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
- is_user, is_softmmu);
- } else if (ret < 0) {
- do_fault:
-#if defined (DEBUG_MMU)
- if (loglevel > 0)
- cpu_ppc_dump_state(env, logfile, 0);
-#endif
+ ret = -1;
+ raddr = -1;
+ for (i = 0; i < env->nb_tlb; i++) {
+ tlb = &env->tlb[i].tlbe;
+ if (ppcemb_tlb_check(env, tlb, &raddr, address,
+ env->spr[SPR_40x_PID], 0, i) < 0)
+ continue;
+ zsel = (tlb->attr >> 4) & 0xF;
+ zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
+ __func__, i, zsel, zpr, rw, tlb->attr);
+ }
if (access_type == ACCESS_CODE) {
- exception = EXCP_ISI;
- switch (ret) {
- case -1:
- /* No matches in page tables */
- error_code = EXCP_ISI_TRANSLATE;
- break;
- case -2:
- /* Access rights violation */
- error_code = EXCP_ISI_PROT;
- break;
+ /* Check execute enable bit */
+ switch (zpr) {
+ case 0x2:
+ if (msr_pr)
+ goto check_exec_perm;
+ goto exec_granted;
+ case 0x0:
+ if (msr_pr) {
+ ctx->prot = 0;
+ ret = -3;
+ break;
+ }
+ /* No break here */
+ case 0x1:
+ check_exec_perm:
+ /* Check from TLB entry */
+ if (!(tlb->prot & PAGE_EXEC)) {
+ ret = -3;
+ } else {
+ if (tlb->prot & PAGE_WRITE) {
+ ctx->prot = PAGE_READ | PAGE_WRITE;
+ } else {
+ ctx->prot = PAGE_READ;
+ }
+ ret = 0;
+ }
+ break;
+ case 0x3:
+ exec_granted:
+ /* All accesses granted */
+ ctx->prot = PAGE_READ | PAGE_WRITE;
+ ret = 0;
+ break;
+ }
+ } else {
+ switch (zpr) {
+ case 0x2:
+ if (msr_pr)
+ goto check_rw_perm;
+ goto rw_granted;
+ case 0x0:
+ if (msr_pr) {
+ ctx->prot = 0;
+ ret = -2;
+ break;
+ }
+ /* No break here */
+ case 0x1:
+ check_rw_perm:
+ /* Check from TLB entry */
+ /* Check write protection bit */
+ if (tlb->prot & PAGE_WRITE) {
+ ctx->prot = PAGE_READ | PAGE_WRITE;
+ ret = 0;
+ } else {
+ ctx->prot = PAGE_READ;
+ if (rw)
+ ret = -2;
+ else
+ ret = 0;
+ }
+ break;
+ case 0x3:
+ rw_granted:
+ /* All accesses granted */
+ ctx->prot = PAGE_READ | PAGE_WRITE;
+ ret = 0;
+ break;
+ }
+ }
+ if (ret >= 0) {
+ ctx->raddr = raddr;
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: access granted " ADDRX " => " REGX
+ " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
+ ret);
+ }
+ return 0;
+ }
+ }
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: access refused " ADDRX " => " REGX
+ " %d %d\n", __func__, address, raddr, ctx->prot,
+ ret);
+ }
+
+ return ret;
+}
+
+void store_40x_sler (CPUPPCState *env, uint32_t val)
+{
+ /* XXX: TO BE FIXED */
+ if (val != 0x00000000) {
+ cpu_abort(env, "Little-endian regions are not supported by now\n");
+ }
+ env->spr[SPR_405_SLER] = val;
+}
+
+int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong address, int rw,
+ int access_type)
+{
+ ppcemb_tlb_t *tlb;
+ target_phys_addr_t raddr;
+ int i, prot, ret;
+
+ ret = -1;
+ raddr = -1;
+ for (i = 0; i < env->nb_tlb; i++) {
+ tlb = &env->tlb[i].tlbe;
+ if (ppcemb_tlb_check(env, tlb, &raddr, address,
+ env->spr[SPR_BOOKE_PID], 1, i) < 0)
+ continue;
+ if (msr_pr)
+ prot = tlb->prot & 0xF;
+ else
+ prot = (tlb->prot >> 4) & 0xF;
+ /* Check the address space */
+ if (access_type == ACCESS_CODE) {
+ if (msr_is != (tlb->attr & 1))
+ continue;
+ ctx->prot = prot;
+ if (prot & PAGE_EXEC) {
+ ret = 0;
+ break;
+ }
+ ret = -3;
+ } else {
+ if (msr_ds != (tlb->attr & 1))
+ continue;
+ ctx->prot = prot;
+ if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
+ ret = 0;
+ break;
+ }
+ ret = -2;
+ }
+ }
+ if (ret >= 0)
+ ctx->raddr = raddr;
+
+ return ret;
+}
+
+static int check_physical (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw)
+{
+ int in_plb, ret;
+
+ ctx->raddr = eaddr;
+ ctx->prot = PAGE_READ;
+ ret = 0;
+ switch (env->mmu_model) {
+ case POWERPC_MMU_32B:
+ case POWERPC_MMU_SOFT_6xx:
+ case POWERPC_MMU_601:
+ case POWERPC_MMU_SOFT_4xx:
+ case POWERPC_MMU_REAL_4xx:
+ ctx->prot |= PAGE_WRITE;
+ break;
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_64BRIDGE:
+ /* Real address are 60 bits long */
+ ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
+ ctx->prot |= PAGE_WRITE;
+ break;
+#endif
+ case POWERPC_MMU_SOFT_4xx_Z:
+ if (unlikely(msr_pe != 0)) {
+ /* 403 family add some particular protections,
+ * using PBL/PBU registers for accesses with no translation.
+ */
+ in_plb =
+ /* Check PLB validity */
+ (env->pb[0] < env->pb[1] &&
+ /* and address in plb area */
+ eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
+ (env->pb[2] < env->pb[3] &&
+ eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
+ if (in_plb ^ msr_px) {
+ /* Access in protected area */
+ if (rw == 1) {
+ /* Access is not allowed */
+ ret = -2;
+ }
+ } else {
+ /* Read-write access is allowed */
+ ctx->prot |= PAGE_WRITE;
+ }
+ }
+ break;
+ case POWERPC_MMU_BOOKE:
+ ctx->prot |= PAGE_WRITE;
+ break;
+ case POWERPC_MMU_BOOKE_FSL:
+ /* XXX: TODO */
+ cpu_abort(env, "BookE FSL MMU model not implemented\n");
+ break;
+ default:
+ cpu_abort(env, "Unknown or invalid MMU model\n");
+ return -1;
+ }
+
+ return ret;
+}
+
+int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
+ int rw, int access_type, int check_BATs)
+{
+ int ret;
+#if 0
+ if (loglevel != 0) {
+ fprintf(logfile, "%s\n", __func__);
+ }
+#endif
+ if ((access_type == ACCESS_CODE && msr_ir == 0) ||
+ (access_type != ACCESS_CODE && msr_dr == 0)) {
+ /* No address translation */
+ ret = check_physical(env, ctx, eaddr, rw);
+ } else {
+ ret = -1;
+ switch (env->mmu_model) {
+ case POWERPC_MMU_32B:
+ case POWERPC_MMU_SOFT_6xx:
+ /* Try to find a BAT */
+ if (check_BATs)
+ ret = get_bat(env, ctx, eaddr, rw, access_type);
+ /* No break here */
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_64BRIDGE:
+#endif
+ if (ret < 0) {
+ /* We didn't match any BAT entry or don't have BATs */
+ ret = get_segment(env, ctx, eaddr, rw, access_type);
+ }
+ break;
+ case POWERPC_MMU_SOFT_4xx:
+ case POWERPC_MMU_SOFT_4xx_Z:
+ ret = mmu40x_get_physical_address(env, ctx, eaddr,
+ rw, access_type);
+ break;
+ case POWERPC_MMU_601:
+ /* XXX: TODO */
+ cpu_abort(env, "601 MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_BOOKE:
+ ret = mmubooke_get_physical_address(env, ctx, eaddr,
+ rw, access_type);
+ break;
+ case POWERPC_MMU_BOOKE_FSL:
+ /* XXX: TODO */
+ cpu_abort(env, "BookE FSL MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_REAL_4xx:
+ cpu_abort(env, "PowerPC 401 does not do any translation\n");
+ return -1;
+ default:
+ cpu_abort(env, "Unknown or invalid MMU model\n");
+ return -1;
+ }
+ }
+#if 0
+ if (loglevel != 0) {
+ fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
+ __func__, eaddr, ret, ctx->raddr);
+ }
+#endif
+
+ return ret;
+}
+
+target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
+{
+ mmu_ctx_t ctx;
+
+ if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
+ return -1;
+
+ return ctx.raddr & TARGET_PAGE_MASK;
+}
+
+/* Perform address translation */
+int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu)
+{
+ mmu_ctx_t ctx;
+ int exception = 0, error_code = 0;
+ int access_type;
+ int ret = 0;
+
+ if (rw == 2) {
+ /* code access */
+ rw = 0;
+ access_type = ACCESS_CODE;
+ } else {
+ /* data access */
+ /* XXX: put correct access by using cpu_restore_state()
+ correctly */
+ access_type = ACCESS_INT;
+ // access_type = env->access_type;
+ }
+ ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
+ if (ret == 0) {
+ ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
+ ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
+ is_user, is_softmmu);
+ } else if (ret < 0) {
+#if defined (DEBUG_MMU)
+ if (loglevel != 0)
+ cpu_dump_state(env, logfile, fprintf, 0);
+#endif
+ if (access_type == ACCESS_CODE) {
+ exception = POWERPC_EXCP_ISI;
+ switch (ret) {
+ case -1:
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_6xx:
+ exception = POWERPC_EXCP_IFTLB;
+ env->spr[SPR_IMISS] = address;
+ env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
+ error_code = 1 << 18;
+ goto tlb_miss;
+ case POWERPC_MMU_SOFT_4xx:
+ case POWERPC_MMU_SOFT_4xx_Z:
+ exception = POWERPC_EXCP_ITLB;
+ error_code = 0;
+ env->spr[SPR_40x_DEAR] = address;
+ env->spr[SPR_40x_ESR] = 0x00000000;
+ break;
+ case POWERPC_MMU_32B:
+ error_code = 0x40000000;
+ break;
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_64B:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_64BRIDGE:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+#endif
+ case POWERPC_MMU_601:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_BOOKE:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_BOOKE_FSL:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_REAL_4xx:
+ cpu_abort(env, "PowerPC 401 should never raise any MMU "
+ "exceptions\n");
+ return -1;
+ default:
+ cpu_abort(env, "Unknown or invalid MMU model\n");
+ return -1;
+ }
+ break;
+ case -2:
+ /* Access rights violation */
+ error_code = 0x08000000;
+ break;
case -3:
- /* No execute protection violation */
- error_code = EXCP_ISI_NOEXEC;
+ /* No execute protection violation */
+ error_code = 0x10000000;
break;
case -4:
/* Direct store exception */
/* No code fetch is allowed in direct-store areas */
- error_code = EXCP_ISI_DIRECT;
+ error_code = 0x10000000;
break;
+#if defined(TARGET_PPC64)
+ case -5:
+ /* No match in segment table */
+ exception = POWERPC_EXCP_ISEG;
+ error_code = 0;
+ break;
+#endif
}
} else {
- exception = EXCP_DSI;
+ exception = POWERPC_EXCP_DSI;
switch (ret) {
case -1:
- /* No matches in page tables */
- error_code = EXCP_DSI_TRANSLATE;
+ /* No matches in page tables or TLB */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_6xx:
+ if (rw == 1) {
+ exception = POWERPC_EXCP_DSTLB;
+ error_code = 1 << 16;
+ } else {
+ exception = POWERPC_EXCP_DLTLB;
+ error_code = 0;
+ }
+ env->spr[SPR_DMISS] = address;
+ env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
+ tlb_miss:
+ error_code |= ctx.key << 19;
+ env->spr[SPR_HASH1] = ctx.pg_addr[0];
+ env->spr[SPR_HASH2] = ctx.pg_addr[1];
+ /* Do not alter DAR nor DSISR */
+ goto out;
+ case POWERPC_MMU_SOFT_4xx:
+ case POWERPC_MMU_SOFT_4xx_Z:
+ exception = POWERPC_EXCP_DTLB;
+ error_code = 0;
+ env->spr[SPR_40x_DEAR] = address;
+ if (rw)
+ env->spr[SPR_40x_ESR] = 0x00800000;
+ else
+ env->spr[SPR_40x_ESR] = 0x00000000;
+ break;
+ case POWERPC_MMU_32B:
+ error_code = 0x40000000;
+ break;
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_64B:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_64BRIDGE:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+#endif
+ case POWERPC_MMU_601:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_BOOKE:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_BOOKE_FSL:
+ /* XXX: TODO */
+ cpu_abort(env, "MMU model not implemented\n");
+ return -1;
+ case POWERPC_MMU_REAL_4xx:
+ cpu_abort(env, "PowerPC 401 should never raise any MMU "
+ "exceptions\n");
+ return -1;
+ default:
+ cpu_abort(env, "Unknown or invalid MMU model\n");
+ return -1;
+ }
break;
case -2:
/* Access rights violation */
- error_code = EXCP_DSI_PROT;
+ error_code = 0x08000000;
break;
case -4:
/* Direct store exception */
switch (access_type) {
case ACCESS_FLOAT:
/* Floating point load/store */
- exception = EXCP_ALIGN;
- error_code = EXCP_ALIGN_FP;
+ exception = POWERPC_EXCP_ALIGN;
+ error_code = POWERPC_EXCP_ALIGN_FP;
break;
case ACCESS_RES:
/* lwarx, ldarx or srwcx. */
- exception = EXCP_DSI;
- error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
+ error_code = 0x04000000;
break;
case ACCESS_EXT:
/* eciwx or ecowx */
- exception = EXCP_DSI;
- error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
- EXCP_DSI_ECXW;
+ error_code = 0x04100000;
break;
default:
- printf("DSI: invalid exception (%d)\n", ret);
- exception = EXCP_PROGRAM;
- error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
+ printf("DSI: invalid exception (%d)\n", ret);
+ exception = POWERPC_EXCP_PROGRAM;
+ error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
break;
}
+ break;
+#if defined(TARGET_PPC64)
+ case -5:
+ /* No match in segment table */
+ exception = POWERPC_EXCP_DSEG;
+ error_code = 0;
+ break;
+#endif
}
- if (rw)
- error_code |= EXCP_DSI_STORE;
- /* Store fault address */
- env->spr[DAR] = address;
+ if (exception == POWERPC_EXCP_DSI && rw == 1)
+ error_code |= 0x02000000;
+ /* Store fault address */
+ env->spr[SPR_DAR] = address;
+ env->spr[SPR_DSISR] = error_code;
}
+ out:
#if 0
printf("%s: set exception to %d %02x\n",
__func__, exception, error_code);
return ret;
}
-uint32_t _load_xer (CPUState *env)
+/*****************************************************************************/
+/* BATs management */
+#if !defined(FLUSH_ALL_TLBS)
+static inline void do_invalidate_BAT (CPUPPCState *env,
+ target_ulong BATu, target_ulong mask)
+{
+ target_ulong base, end, page;
+
+ base = BATu & ~0x0001FFFF;
+ end = base + mask + 0x00020000;
+#if defined (DEBUG_BATS)
+ if (loglevel != 0) {
+ fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
+ base, end, mask);
+ }
+#endif
+ for (page = base; page != end; page += TARGET_PAGE_SIZE)
+ tlb_flush_page(env, page);
+#if defined (DEBUG_BATS)
+ if (loglevel != 0)
+ fprintf(logfile, "Flush done\n");
+#endif
+}
+#endif
+
+static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
+ target_ulong value)
+{
+#if defined (DEBUG_BATS)
+ if (loglevel != 0) {
+ fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
+ ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
+ }
+#endif
+}
+
+target_ulong do_load_ibatu (CPUPPCState *env, int nr)
+{
+ return env->IBAT[0][nr];
+}
+
+target_ulong do_load_ibatl (CPUPPCState *env, int nr)
+{
+ return env->IBAT[1][nr];
+}
+
+void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
+{
+ target_ulong mask;
+
+ dump_store_bat(env, 'I', 0, nr, value);
+ if (env->IBAT[0][nr] != value) {
+ mask = (value << 15) & 0x0FFE0000UL;
+#if !defined(FLUSH_ALL_TLBS)
+ do_invalidate_BAT(env, env->IBAT[0][nr], mask);
+#endif
+ /* When storing valid upper BAT, mask BEPI and BRPN
+ * and invalidate all TLBs covered by this BAT
+ */
+ mask = (value << 15) & 0x0FFE0000UL;
+ env->IBAT[0][nr] = (value & 0x00001FFFUL) |
+ (value & ~0x0001FFFFUL & ~mask);
+ env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
+ (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
+#if !defined(FLUSH_ALL_TLBS)
+ do_invalidate_BAT(env, env->IBAT[0][nr], mask);
+#else
+ tlb_flush(env, 1);
+#endif
+ }
+}
+
+void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
+{
+ dump_store_bat(env, 'I', 1, nr, value);
+ env->IBAT[1][nr] = value;
+}
+
+target_ulong do_load_dbatu (CPUPPCState *env, int nr)
+{
+ return env->DBAT[0][nr];
+}
+
+target_ulong do_load_dbatl (CPUPPCState *env, int nr)
+{
+ return env->DBAT[1][nr];
+}
+
+void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
+{
+ target_ulong mask;
+
+ dump_store_bat(env, 'D', 0, nr, value);
+ if (env->DBAT[0][nr] != value) {
+ /* When storing valid upper BAT, mask BEPI and BRPN
+ * and invalidate all TLBs covered by this BAT
+ */
+ mask = (value << 15) & 0x0FFE0000UL;
+#if !defined(FLUSH_ALL_TLBS)
+ do_invalidate_BAT(env, env->DBAT[0][nr], mask);
+#endif
+ mask = (value << 15) & 0x0FFE0000UL;
+ env->DBAT[0][nr] = (value & 0x00001FFFUL) |
+ (value & ~0x0001FFFFUL & ~mask);
+ env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
+ (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
+#if !defined(FLUSH_ALL_TLBS)
+ do_invalidate_BAT(env, env->DBAT[0][nr], mask);
+#else
+ tlb_flush(env, 1);
+#endif
+ }
+}
+
+void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
+{
+ dump_store_bat(env, 'D', 1, nr, value);
+ env->DBAT[1][nr] = value;
+}
+
+
+/*****************************************************************************/
+/* TLB management */
+void ppc_tlb_invalidate_all (CPUPPCState *env)
+{
+ if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
+ ppc6xx_tlb_invalidate_all(env);
+ } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) {
+ ppc4xx_tlb_invalidate_all(env);
+ } else {
+ tlb_flush(env, 1);
+ }
+}
+
+/*****************************************************************************/
+/* Special registers manipulation */
+#if defined(TARGET_PPC64)
+target_ulong ppc_load_asr (CPUPPCState *env)
+{
+ return env->asr;
+}
+
+void ppc_store_asr (CPUPPCState *env, target_ulong value)
+{
+ if (env->asr != value) {
+ env->asr = value;
+ tlb_flush(env, 1);
+ }
+}
+#endif
+
+target_ulong do_load_sdr1 (CPUPPCState *env)
+{
+ return env->sdr1;
+}
+
+void do_store_sdr1 (CPUPPCState *env, target_ulong value)
+{
+#if defined (DEBUG_MMU)
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
+ }
+#endif
+ if (env->sdr1 != value) {
+ env->sdr1 = value;
+ tlb_flush(env, 1);
+ }
+}
+
+target_ulong do_load_sr (CPUPPCState *env, int srnum)
+{
+ return env->sr[srnum];
+}
+
+void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
+{
+#if defined (DEBUG_MMU)
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
+ __func__, srnum, value, env->sr[srnum]);
+ }
+#endif
+ if (env->sr[srnum] != value) {
+ env->sr[srnum] = value;
+#if !defined(FLUSH_ALL_TLBS) && 0
+ {
+ target_ulong page, end;
+ /* Invalidate 256 MB of virtual memory */
+ page = (16 << 20) * srnum;
+ end = page + (16 << 20);
+ for (; page != end; page += TARGET_PAGE_SIZE)
+ tlb_flush_page(env, page);
+ }
+#else
+ tlb_flush(env, 1);
+#endif
+ }
+}
+#endif /* !defined (CONFIG_USER_ONLY) */
+
+uint32_t ppc_load_xer (CPUPPCState *env)
+{
+ return (xer_so << XER_SO) |
+ (xer_ov << XER_OV) |
+ (xer_ca << XER_CA) |
+ (xer_bc << XER_BC) |
+ (xer_cmp << XER_CMP);
+}
+
+void ppc_store_xer (CPUPPCState *env, uint32_t value)
+{
+ xer_so = (value >> XER_SO) & 0x01;
+ xer_ov = (value >> XER_OV) & 0x01;
+ xer_ca = (value >> XER_CA) & 0x01;
+ xer_cmp = (value >> XER_CMP) & 0xFF;
+ xer_bc = (value >> XER_BC) & 0x7F;
+}
+
+/* Swap temporary saved registers with GPRs */
+static inline void swap_gpr_tgpr (CPUPPCState *env)
+{
+ ppc_gpr_t tmp;
+
+ tmp = env->gpr[0];
+ env->gpr[0] = env->tgpr[0];
+ env->tgpr[0] = tmp;
+ tmp = env->gpr[1];
+ env->gpr[1] = env->tgpr[1];
+ env->tgpr[1] = tmp;
+ tmp = env->gpr[2];
+ env->gpr[2] = env->tgpr[2];
+ env->tgpr[2] = tmp;
+ tmp = env->gpr[3];
+ env->gpr[3] = env->tgpr[3];
+ env->tgpr[3] = tmp;
+}
+
+/* GDBstub can read and write MSR... */
+target_ulong do_load_msr (CPUPPCState *env)
+{
+ return
+#if defined (TARGET_PPC64)
+ ((target_ulong)msr_sf << MSR_SF) |
+ ((target_ulong)msr_isf << MSR_ISF) |
+ ((target_ulong)msr_hv << MSR_HV) |
+#endif
+ ((target_ulong)msr_ucle << MSR_UCLE) |
+ ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
+ ((target_ulong)msr_ap << MSR_AP) |
+ ((target_ulong)msr_sa << MSR_SA) |
+ ((target_ulong)msr_key << MSR_KEY) |
+ ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
+ ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
+ ((target_ulong)msr_ile << MSR_ILE) |
+ ((target_ulong)msr_ee << MSR_EE) |
+ ((target_ulong)msr_pr << MSR_PR) |
+ ((target_ulong)msr_fp << MSR_FP) |
+ ((target_ulong)msr_me << MSR_ME) |
+ ((target_ulong)msr_fe0 << MSR_FE0) |
+ ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
+ ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
+ ((target_ulong)msr_fe1 << MSR_FE1) |
+ ((target_ulong)msr_al << MSR_AL) |
+ ((target_ulong)msr_ip << MSR_IP) |
+ ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
+ ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
+ ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
+ ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
+ ((target_ulong)msr_ri << MSR_RI) |
+ ((target_ulong)msr_le << MSR_LE);
+}
+
+void do_store_msr (CPUPPCState *env, target_ulong value)
+{
+ int enter_pm;
+
+ value &= env->msr_mask;
+ if (((value >> MSR_IR) & 1) != msr_ir ||
+ ((value >> MSR_DR) & 1) != msr_dr) {
+ /* Flush all tlb when changing translation mode */
+ tlb_flush(env, 1);
+ env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ }
+#if 0
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
+ }
+#endif
+ switch (env->excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_603E:
+ case POWERPC_EXCP_G2:
+ if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
+ /* Swap temporary saved registers with GPRs */
+ swap_gpr_tgpr(env);
+ }
+ break;
+ default:
+ break;
+ }
+#if defined (TARGET_PPC64)
+ msr_sf = (value >> MSR_SF) & 1;
+ msr_isf = (value >> MSR_ISF) & 1;
+ msr_hv = (value >> MSR_HV) & 1;
+#endif
+ msr_ucle = (value >> MSR_UCLE) & 1;
+ msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
+ msr_ap = (value >> MSR_AP) & 1;
+ msr_sa = (value >> MSR_SA) & 1;
+ msr_key = (value >> MSR_KEY) & 1;
+ msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
+ msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
+ msr_ile = (value >> MSR_ILE) & 1;
+ msr_ee = (value >> MSR_EE) & 1;
+ msr_pr = (value >> MSR_PR) & 1;
+ msr_fp = (value >> MSR_FP) & 1;
+ msr_me = (value >> MSR_ME) & 1;
+ msr_fe0 = (value >> MSR_FE0) & 1;
+ msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
+ msr_be = (value >> MSR_BE) & 1; /* BE / DE */
+ msr_fe1 = (value >> MSR_FE1) & 1;
+ msr_al = (value >> MSR_AL) & 1;
+ msr_ip = (value >> MSR_IP) & 1;
+ msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
+ msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
+ msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
+ msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
+ msr_ri = (value >> MSR_RI) & 1;
+ msr_le = (value >> MSR_LE) & 1;
+ do_compute_hflags(env);
+
+ enter_pm = 0;
+ switch (env->excp_model) {
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_603E:
+ case POWERPC_EXCP_G2:
+ /* Don't handle SLEEP mode: we should disable all clocks...
+ * No dynamic power-management.
+ */
+ if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
+ enter_pm = 1;
+ break;
+ case POWERPC_EXCP_604:
+ if (msr_pow == 1)
+ enter_pm = 1;
+ break;
+ case POWERPC_EXCP_7x0:
+ if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
+ enter_pm = 1;
+ break;
+ default:
+ break;
+ }
+ if (enter_pm) {
+ if (likely(!env->halted)) {
+ /* power save: exit cpu loop */
+ env->halted = 1;
+ env->exception_index = EXCP_HLT;
+ cpu_loop_exit();
+ }
+ }
+}
+
+#if defined(TARGET_PPC64)
+void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
+{
+ do_store_msr(env,
+ (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
+}
+#endif
+
+void do_compute_hflags (CPUPPCState *env)
+{
+ /* Compute current hflags */
+ env->hflags = (msr_vr << MSR_VR) |
+ (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
+ (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
+ (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
+#if defined (TARGET_PPC64)
+ env->hflags |= msr_cm << MSR_CM;
+ env->hflags |= (uint64_t)msr_sf << MSR_SF;
+ env->hflags |= (uint64_t)msr_hv << MSR_HV;
+#endif
+}
+
+/*****************************************************************************/
+/* Exception processing */
+#if defined (CONFIG_USER_ONLY)
+void do_interrupt (CPUState *env)
{
- return (xer_so << XER_SO) |
- (xer_ov << XER_OV) |
- (xer_ca << XER_CA) |
- (xer_bc << XER_BC);
+ env->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
}
-void _store_xer (CPUState *env, uint32_t value)
+void ppc_hw_interrupt (CPUState *env)
{
- xer_so = (value >> XER_SO) & 0x01;
- xer_ov = (value >> XER_OV) & 0x01;
- xer_ca = (value >> XER_CA) & 0x01;
- xer_bc = (value >> XER_BC) & 0x1f;
-}
-
-uint32_t _load_msr (CPUState *env)
-{
- return (msr_pow << MSR_POW) |
- (msr_ile << MSR_ILE) |
- (msr_ee << MSR_EE) |
- (msr_pr << MSR_PR) |
- (msr_fp << MSR_FP) |
- (msr_me << MSR_ME) |
- (msr_fe0 << MSR_FE0) |
- (msr_se << MSR_SE) |
- (msr_be << MSR_BE) |
- (msr_fe1 << MSR_FE1) |
- (msr_ip << MSR_IP) |
- (msr_ir << MSR_IR) |
- (msr_dr << MSR_DR) |
- (msr_ri << MSR_RI) |
- (msr_le << MSR_LE);
-}
-
-void _store_msr (CPUState *env, uint32_t value)
-{
- if (((value >> MSR_IR) & 0x01) != msr_ir ||
- ((value >> MSR_DR) & 0x01) != msr_dr) {
- /* Flush all tlb when changing translation mode or privilege level */
- tlb_flush(env, 1);
- }
- msr_pow = (value >> MSR_POW) & 0x03;
- msr_ile = (value >> MSR_ILE) & 0x01;
- msr_ee = (value >> MSR_EE) & 0x01;
- msr_pr = (value >> MSR_PR) & 0x01;
- msr_fp = (value >> MSR_FP) & 0x01;
- msr_me = (value >> MSR_ME) & 0x01;
- msr_fe0 = (value >> MSR_FE0) & 0x01;
- msr_se = (value >> MSR_SE) & 0x01;
- msr_be = (value >> MSR_BE) & 0x01;
- msr_fe1 = (value >> MSR_FE1) & 0x01;
- msr_ip = (value >> MSR_IP) & 0x01;
- msr_ir = (value >> MSR_IR) & 0x01;
- msr_dr = (value >> MSR_DR) & 0x01;
- msr_ri = (value >> MSR_RI) & 0x01;
- msr_le = (value >> MSR_LE) & 0x01;
+ env->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+}
+#else /* defined (CONFIG_USER_ONLY) */
+static void dump_syscall (CPUState *env)
+{
+ fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
+ " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
+ env->gpr[0], env->gpr[3], env->gpr[4],
+ env->gpr[5], env->gpr[6], env->nip);
}
-void do_interrupt (CPUState *env)
+/* Note that this function should be greatly optimized
+ * when called with a constant excp, from ppc_hw_interrupt
+ */
+static always_inline void powerpc_excp (CPUState *env,
+ int excp_model, int excp)
{
-#if defined (CONFIG_USER_ONLY)
- env->exception_index |= 0x100;
-#else
- uint32_t msr;
- int excp = env->exception_index;
+ target_ulong msr, vector;
+ int srr0, srr1, asrr0, asrr1;
- /* Dequeue PPC exceptions */
- if (excp < EXCP_PPC_MAX)
- env->exceptions &= ~(1 << excp);
- msr = _load_msr(env);
-#if defined (DEBUG_EXCEPTIONS)
- if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
- {
- if (loglevel > 0) {
- fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
- env->nip, excp << 8, env->error_code);
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
+ env->nip, excp, env->error_code);
}
- if (loglevel > 0)
- cpu_ppc_dump_state(env, logfile, 0);
- }
-#endif
- /* Generate informations in save/restore registers */
+ msr = do_load_msr(env);
+ srr0 = SPR_SRR0;
+ srr1 = SPR_SRR1;
+ asrr0 = -1;
+ asrr1 = -1;
+ msr &= ~((target_ulong)0x783F0000);
switch (excp) {
- case EXCP_OFCALL:
-#if defined (USE_OPEN_FIRMWARE)
- env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
-#endif
- return;
- case EXCP_RTASCALL:
-#if defined (USE_OPEN_FIRMWARE)
- printf("RTAS call !\n");
- env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
- printf("RTAS call done\n");
-#endif
- return;
- case EXCP_NONE:
- /* Do nothing */
-#if defined (DEBUG_EXCEPTIONS)
- printf("%s: escape EXCP_NONE\n", __func__);
-#endif
+ case POWERPC_EXCP_NONE:
+ /* Should never happen */
return;
- case EXCP_RESET:
- if (msr_ip)
- excp += 0xFFC00;
+ case POWERPC_EXCP_CRITICAL: /* Critical input */
+ msr_ri = 0; /* XXX: check this */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_G2:
+ break;
+ default:
+ goto excp_invalid;
+ }
goto store_next;
- case EXCP_MACHINE_CHECK:
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
- printf("Machine check exception while not allowed !\n");
- if (loglevel) {
- fprintf(logfile,
- "Machine check exception while not allowed !\n");
+ /* Machine check exception is not enabled */
+ /* XXX: we may just stop the processor here, to allow debugging */
+ excp = POWERPC_EXCP_RESET;
+ goto excp_reset;
}
- abort();
- }
+ msr_ri = 0;
msr_me = 0;
- break;
- case EXCP_DSI:
- /* Store exception cause */
- /* data location address has been stored
- * when the fault has been detected
- */
- msr &= ~0xFFFF0000;
- env->spr[DSISR] = 0;
- if (env->error_code & EXCP_DSI_TRANSLATE)
- env->spr[DSISR] |= 0x40000000;
- else if (env->error_code & EXCP_DSI_PROT)
- env->spr[DSISR] |= 0x08000000;
- else if (env->error_code & EXCP_DSI_NOTSUP) {
- env->spr[DSISR] |= 0x80000000;
- if (env->error_code & EXCP_DSI_DIRECT)
- env->spr[DSISR] |= 0x04000000;
- }
- if (env->error_code & EXCP_DSI_STORE)
- env->spr[DSISR] |= 0x02000000;
- if ((env->error_code & 0xF) == EXCP_DSI_DABR)
- env->spr[DSISR] |= 0x00400000;
- if (env->error_code & EXCP_DSI_ECXW)
- env->spr[DSISR] |= 0x00100000;
-#if defined (DEBUG_EXCEPTIONS)
- if (loglevel) {
- fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
- env->spr[DSISR], env->spr[DAR]);
- } else {
- printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
- env->spr[DSISR], env->spr[DAR], env->nip);
- }
-#endif
- goto store_next;
- case EXCP_ISI:
- /* Store exception cause */
- msr &= ~0xFFFF0000;
- if (env->error_code == EXCP_ISI_TRANSLATE)
- msr |= 0x40000000;
- else if (env->error_code == EXCP_ISI_NOEXEC ||
- env->error_code == EXCP_ISI_GUARD ||
- env->error_code == EXCP_ISI_DIRECT)
- msr |= 0x10000000;
- else
- msr |= 0x08000000;
+#if defined(TARGET_PPC64H)
+ msr_hv = 1;
+#endif
+ /* XXX: should also have something loaded in DAR / DSISR */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+ asrr0 = SPR_BOOKE_CSRR0;
+ asrr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ goto store_next;
+ case POWERPC_EXCP_DSI: /* Data storage exception */
#if defined (DEBUG_EXCEPTIONS)
- if (loglevel) {
- fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
- msr, env->nip);
- } else {
- printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
- msr, env->nip, env->spr[V_TBL]);
- }
+ if (loglevel != 0) {
+ fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
+ "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ }
+#endif
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
#endif
goto store_next;
- case EXCP_EXTERNAL:
- if (msr_ee == 0) {
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
#if defined (DEBUG_EXCEPTIONS)
- if (loglevel > 0) {
- fprintf(logfile, "Skipping hardware interrupt\n");
- }
+ if (loglevel != 0) {
+ fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
+ "\n", msr, env->nip);
+ }
+#endif
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ msr |= env->error_code;
+ goto store_next;
+ case POWERPC_EXCP_EXTERNAL: /* External input */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes0 == 1)
+ msr_hv = 1;
#endif
- /* Requeue it */
- do_queue_exception(EXCP_EXTERNAL);
- return;
- }
goto store_next;
- case EXCP_ALIGN:
- /* Store exception cause */
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ /* XXX: this is false */
/* Get rS/rD and rA from faulting opcode */
- env->spr[DSISR] |=
- (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
- /* data location address has been stored
- * when the fault has been detected
- */
+ env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
goto store_current;
- case EXCP_PROGRAM:
- msr &= ~0xFFFF0000;
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
- case EXCP_FP:
- if (msr_fe0 == 0 && msr_fe1 == 0) {
+ case POWERPC_EXCP_FP:
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
#if defined (DEBUG_EXCEPTIONS)
- printf("Ignore floating point exception\n");
+ if (loglevel != 0) {
+ fprintf(logfile, "Ignore floating point exception\n");
+ }
#endif
return;
- }
+ }
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
msr |= 0x00100000;
/* Set FX */
env->fpscr[7] |= 0x8;
if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
env->fpscr[7] |= 0x4;
- break;
- case EXCP_INVAL:
- printf("Invalid instruction at 0x%08x\n", env->nip);
+ if (msr_fe0 != msr_fe1) {
+ msr |= 0x00010000;
+ goto store_current;
+ }
+ break;
+ case POWERPC_EXCP_INVAL:
+#if defined (DEBUG_EXCEPTIONS)
+ if (loglevel != 0) {
+ fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
+ env->nip);
+ }
+#endif
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
msr |= 0x00080000;
- break;
- case EXCP_PRIV:
+ break;
+ case POWERPC_EXCP_PRIV:
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
msr |= 0x00040000;
- break;
- case EXCP_TRAP:
+ break;
+ case POWERPC_EXCP_TRAP:
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
msr |= 0x00020000;
break;
default:
/* Should never occur */
- break;
- }
- msr |= 0x00010000;
- goto store_current;
- case EXCP_NO_FP:
+ cpu_abort(env, "Invalid program exception %d. Aborting\n",
+ env->error_code);
+ break;
+ }
+ goto store_next;
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
goto store_current;
- case EXCP_DECR:
- if (msr_ee == 0) {
- /* Requeue it */
- do_queue_exception(EXCP_DECR);
- return;
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
+ /* NOTE: this is a temporary hack to support graphics OSI
+ calls from the MOL driver */
+ /* XXX: To be removed */
+ if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
+ env->osi_call) {
+ if (env->osi_call(env) != 0)
+ return;
}
+ if (loglevel & CPU_LOG_INT) {
+ dump_syscall(env);
+ }
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
+ msr_hv = 1;
+#endif
+ goto store_next;
+ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
+ msr_ri = 0;
+ goto store_current;
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ goto store_next;
+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
+ /* FIT on 4xx */
+#if defined (DEBUG_EXCEPTIONS)
+ if (loglevel != 0)
+ fprintf(logfile, "FIT exception\n");
+#endif
+ msr_ri = 0; /* XXX: check this */
goto store_next;
- case EXCP_SYSCALL:
+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
#if defined (DEBUG_EXCEPTIONS)
- if (msr_pr) {
- if (loglevel) {
- fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
- env->gpr[0], env->gpr[3], env->gpr[4],
- env->gpr[5], env->gpr[6]);
- } else {
- printf("syscall %d from 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
- env->gpr[0], env->nip, env->gpr[3], env->gpr[4],
- env->gpr[5], env->gpr[6]);
- }
- }
+ if (loglevel != 0)
+ fprintf(logfile, "WDT exception\n");
#endif
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ msr_ri = 0; /* XXX: check this */
goto store_next;
- case EXCP_TRACE:
+ case POWERPC_EXCP_DTLB: /* Data TLB error */
+ msr_ri = 0; /* XXX: check this */
goto store_next;
- case EXCP_FP_ASSIST:
+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
+ msr_ri = 0; /* XXX: check this */
goto store_next;
- case EXCP_MTMSR:
- /* Nothing to do */
- return;
- case EXCP_BRANCH:
- /* Nothing to do */
- return;
- case EXCP_RFI:
- /* Restore user-mode state */
- tb_flush(env);
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_DSRR0;
+ srr1 = SPR_BOOKE_DSRR1;
+ asrr0 = SPR_BOOKE_CSRR0;
+ asrr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ /* XXX: TODO */
+ cpu_abort(env, "Debug exception is not implemented yet !\n");
+ goto store_next;
+#if defined(TARGET_PPCEMB)
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
+ msr_ri = 0; /* XXX: check this */
+ goto store_current;
+ case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
+ /* XXX: TODO */
+ cpu_abort(env, "Embedded floating point data exception "
+ "is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
+ /* XXX: TODO */
+ cpu_abort(env, "Embedded floating point round exception "
+ "is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
+ msr_ri = 0;
+ /* XXX: TODO */
+ cpu_abort(env,
+ "Performance counter exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ /* XXX: TODO */
+ cpu_abort(env,
+ "Embedded doorbell interrupt is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ /* XXX: TODO */
+ cpu_abort(env, "Embedded doorbell critical interrupt "
+ "is not implemented yet !\n");
+ goto store_next;
+#endif /* defined(TARGET_PPCEMB) */
+ case POWERPC_EXCP_RESET: /* System reset exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ msr_hv = 1;
+#endif
+ excp_reset:
+ goto store_next;
+#if defined(TARGET_PPC64)
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ /* XXX: TODO */
+ cpu_abort(env, "Data segment exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ /* XXX: TODO */
+ cpu_abort(env,
+ "Instruction segment exception is not implemented yet !\n");
+ goto store_next;
+#endif /* defined(TARGET_PPC64) */
+#if defined(TARGET_PPC64H)
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSSR1;
+ msr_hv = 1;
+ goto store_next;
+#endif
+ case POWERPC_EXCP_TRACE: /* Trace exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ goto store_next;
+#if defined(TARGET_PPC64H)
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSSR1;
+ msr_hv = 1;
+ goto store_next;
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSSR1;
+ msr_hv = 1;
+ /* XXX: TODO */
+ cpu_abort(env, "Hypervisor instruction storage exception "
+ "is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSSR1;
+ msr_hv = 1;
+ goto store_next;
+ case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSSR1;
+ msr_hv = 1;
+ goto store_next;
+#endif /* defined(TARGET_PPC64H) */
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ goto store_current;
+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
#if defined (DEBUG_EXCEPTIONS)
- if (msr_pr == 1)
- printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
+ if (loglevel != 0)
+ fprintf(logfile, "PIT exception\n");
#endif
- return;
+ msr_ri = 0; /* XXX: check this */
+ goto store_next;
+ case POWERPC_EXCP_IO: /* IO error exception */
+ /* XXX: TODO */
+ cpu_abort(env, "601 IO error exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_RUNM: /* Run mode exception */
+ /* XXX: TODO */
+ cpu_abort(env, "601 run mode exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_EMUL: /* Emulation trap exception */
+ /* XXX: TODO */
+ cpu_abort(env, "602 emulation trap exception "
+ "is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
+ msr_ri = 0; /* XXX: check this */
+#if defined(TARGET_PPC64H) /* XXX: check this */
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ switch (excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_603E:
+ case POWERPC_EXCP_G2:
+ goto tlb_miss_tgpr;
+ case POWERPC_EXCP_7x5:
+ goto tlb_miss;
+ default:
+ cpu_abort(env, "Invalid instruction TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
+ msr_ri = 0; /* XXX: check this */
+#if defined(TARGET_PPC64H) /* XXX: check this */
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ switch (excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_603E:
+ case POWERPC_EXCP_G2:
+ goto tlb_miss_tgpr;
+ case POWERPC_EXCP_7x5:
+ goto tlb_miss;
+ default:
+ cpu_abort(env, "Invalid data load TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
+ msr_ri = 0; /* XXX: check this */
+#if defined(TARGET_PPC64H) /* XXX: check this */
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ switch (excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_603E:
+ case POWERPC_EXCP_G2:
+ tlb_miss_tgpr:
+ /* Swap temporary saved registers with GPRs */
+ swap_gpr_tgpr(env);
+ msr_tgpr = 1;
+ goto tlb_miss;
+ case POWERPC_EXCP_7x5:
+ tlb_miss:
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ const unsigned char *es;
+ target_ulong *miss, *cmp;
+ int en;
+ if (excp == 0x1000) {
+ es = "I";
+ en = 'I';
+ miss = &env->spr[SPR_IMISS];
+ cmp = &env->spr[SPR_ICMP];
+ } else {
+ if (excp == 0x1100)
+ es = "DL";
+ else
+ es = "DS";
+ en = 'D';
+ miss = &env->spr[SPR_DMISS];
+ cmp = &env->spr[SPR_DCMP];
+ }
+ fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
+ " H1 " ADDRX " H2 " ADDRX " %08x\n",
+ es, en, *miss, en, *cmp,
+ env->spr[SPR_HASH1], env->spr[SPR_HASH2],
+ env->error_code);
+ }
+#endif
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+ break;
+ default:
+ cpu_abort(env, "Invalid data store TLB miss exception\n");
+ break;
+ }
+ goto store_next;
+ case POWERPC_EXCP_FPA: /* Floating-point assist exception */
+ /* XXX: TODO */
+ cpu_abort(env, "Floating point assist exception "
+ "is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
+ /* XXX: TODO */
+ cpu_abort(env, "IABR exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_SMI: /* System management interrupt */
+ /* XXX: TODO */
+ cpu_abort(env, "SMI exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
+ /* XXX: TODO */
+ cpu_abort(env, "Thermal management exception "
+ "is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
+ msr_ri = 0;
+#if defined(TARGET_PPC64H)
+ if (lpes1 == 0)
+ msr_hv = 1;
+#endif
+ /* XXX: TODO */
+ cpu_abort(env,
+ "Performance counter exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
+ /* XXX: TODO */
+ cpu_abort(env, "VPU assist exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_SOFTP: /* Soft patch exception */
+ /* XXX: TODO */
+ cpu_abort(env,
+ "970 soft-patch exception is not implemented yet !\n");
+ goto store_next;
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
+ /* XXX: TODO */
+ cpu_abort(env,
+ "970 maintenance exception is not implemented yet !\n");
+ goto store_next;
+ default:
+ excp_invalid:
+ cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
+ break;
store_current:
- /* SRR0 is set to current instruction */
- env->spr[SRR0] = (uint32_t)env->nip - 4;
+ /* save current instruction location */
+ env->spr[srr0] = env->nip - 4;
break;
store_next:
- /* SRR0 is set to next instruction */
- env->spr[SRR0] = (uint32_t)env->nip;
+ /* save next instruction location */
+ env->spr[srr0] = env->nip;
break;
}
- env->spr[SRR1] = msr;
+ /* Save MSR */
+ env->spr[srr1] = msr;
+ /* If any alternate SRR register are defined, duplicate saved values */
+ if (asrr0 != -1)
+ env->spr[asrr0] = env->spr[srr0];
+ if (asrr1 != -1)
+ env->spr[asrr1] = env->spr[srr1];
+ /* If we disactivated any translation, flush TLBs */
+ if (msr_ir || msr_dr)
+ tlb_flush(env, 1);
/* reload MSR with correct bits */
- msr_pow = 0;
msr_ee = 0;
msr_pr = 0;
msr_fp = 0;
msr_fe1 = 0;
msr_ir = 0;
msr_dr = 0;
- msr_ri = 0;
+#if 0 /* Fix this: not on all targets */
+ msr_pmm = 0;
+#endif
msr_le = msr_ile;
+ do_compute_hflags(env);
/* Jump to handler */
- env->nip = excp << 8;
- env->exception_index = EXCP_NONE;
- /* Invalidate all TLB as we may have changed translation mode */
- tlb_flush(env, 1);
- /* ensure that no TB jump will be modified as
- the program flow was changed */
-#ifdef __sparc__
- tmp_T0 = 0;
-#else
- T0 = 0;
+ vector = env->excp_vectors[excp];
+ if (vector == (target_ulong)-1) {
+ cpu_abort(env, "Raised an exception without defined vector %d\n",
+ excp);
+ }
+ vector |= env->excp_prefix;
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ msr_cm = msr_icm;
+ if (!msr_cm)
+ vector = (uint32_t)vector;
+ } else {
+ msr_sf = msr_isf;
+ if (!msr_sf)
+ vector = (uint32_t)vector;
+ }
+#endif
+ env->nip = vector;
+ /* Reset exception state */
+ env->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+}
+
+void do_interrupt (CPUState *env)
+{
+ powerpc_excp(env, env->excp_model, env->exception_index);
+}
+
+void ppc_hw_interrupt (CPUPPCState *env)
+{
+#if 1
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
+ __func__, env, env->pending_interrupts,
+ env->interrupt_request, msr_me, msr_ee);
+ }
+#endif
+ /* External reset */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
+ return;
+ }
+ /* Machine check exception */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
+ return;
+ }
+#if 0 /* TODO */
+ /* External debug exception */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
+ return;
+ }
+#endif
+#if defined(TARGET_PPC64H)
+ if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
+ /* Hypervisor decrementer exception */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
+ return;
+ }
+ }
+#endif
+ if (msr_ce != 0) {
+ /* External critical interrupt */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
+ /* Taking a critical external interrupt does not clear the external
+ * critical interrupt status
+ */
+#if 0
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
+#endif
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
+ return;
+ }
+ }
+ if (msr_ee != 0) {
+ /* Watchdog timer on embedded PowerPC */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
+ return;
+ }
+#if defined(TARGET_PPCEMB)
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
+ return;
+ }
+#endif
+#if defined(TARGET_PPCEMB)
+ /* External interrupt */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
+ /* Taking an external interrupt does not clear the external
+ * interrupt status
+ */
+#if 0
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
+#endif
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
+ return;
+ }
+#endif
+ /* Fixed interval timer on embedded PowerPC */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
+ return;
+ }
+ /* Programmable interval timer on embedded PowerPC */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
+ return;
+ }
+ /* Decrementer exception */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
+ return;
+ }
+#if !defined(TARGET_PPCEMB)
+ /* External interrupt */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
+ /* Taking an external interrupt does not clear the external
+ * interrupt status
+ */
+#if 0
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
+#endif
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
+ return;
+ }
+#endif
+#if defined(TARGET_PPCEMB)
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
+ return;
+ }
+#endif
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
+ return;
+ }
+ /* Thermal interrupt */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
+ powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
+ return;
+ }
+ }
+}
+#endif /* !CONFIG_USER_ONLY */
+
+void cpu_dump_EA (target_ulong EA)
+{
+ FILE *f;
+
+ if (logfile) {
+ f = logfile;
+ } else {
+ f = stdout;
+ return;
+ }
+ fprintf(f, "Memory access at address " ADDRX "\n", EA);
+}
+
+void cpu_dump_rfi (target_ulong RA, target_ulong msr)
+{
+ FILE *f;
+
+ if (logfile) {
+ f = logfile;
+ } else {
+ f = stdout;
+ return;
+ }
+ fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
+ RA, msr);
+}
+
+void cpu_ppc_reset (void *opaque)
+{
+ CPUPPCState *env;
+ int i;
+
+ env = opaque;
+ /* XXX: some of those flags initialisation values could depend
+ * on the actual PowerPC implementation
+ */
+ for (i = 0; i < 63; i++)
+ env->msr[i] = 0;
+#if defined(TARGET_PPC64)
+ msr_hv = 0; /* Should be 1... */
+#endif
+ msr_ap = 0; /* TO BE CHECKED */
+ msr_sa = 0; /* TO BE CHECKED */
+ msr_ip = 0; /* TO BE CHECKED */
+#if defined (DO_SINGLE_STEP) && 0
+ /* Single step trace mode */
+ msr_se = 1;
+ msr_be = 1;
#endif
+#if defined(CONFIG_USER_ONLY)
+ msr_fp = 1; /* Allow floating point exceptions */
+ msr_pr = 1;
+#else
+ env->nip = 0xFFFFFFFC;
+ ppc_tlb_invalidate_all(env);
#endif
+ do_compute_hflags(env);
+ env->reserve = -1;
+ /* Be sure no exception or interrupt is pending */
+ env->pending_interrupts = 0;
+ env->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ /* Flush all TLBs */
+ tlb_flush(env, 1);
+}
+
+CPUPPCState *cpu_ppc_init (void)
+{
+ CPUPPCState *env;
+
+ env = qemu_mallocz(sizeof(CPUPPCState));
+ if (!env)
+ return NULL;
+ cpu_exec_init(env);
+ cpu_ppc_reset(env);
+
+ return env;
+}
+
+void cpu_ppc_close (CPUPPCState *env)
+{
+ /* Should also remove all opcode tables... */
+ free(env);
}
projects / qemu.git / blobdiff