spapr: make irq customizable via qdev

[qemu.git] / hw / omap_dss.c

diff --git a/hw/omap_dss.c b/hw/omap_dss.c
index 4917c59c86d1a48f8ca9fdb6ce9da3624bec0560..c8387a8cc1b2be9ba5015c7a1b67ea950d557b19 100644 (file)
--- a/hw/omap_dss.c
+++ b/hw/omap_dss.c
@@ -15,8 +15,7 @@
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "hw.h"
 #include "console.h"
@@ -231,13 +230,13 @@ static void omap_diss_write(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *omap_diss1_readfn[] = {
+static CPUReadMemoryFunc * const omap_diss1_readfn[] = {
     omap_badwidth_read32,
     omap_badwidth_read32,
     omap_diss_read,
 };
 
-static CPUWriteMemoryFunc *omap_diss1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_diss1_writefn[] = {
     omap_badwidth_write32,
     omap_badwidth_write32,
     omap_diss_write,
@@ -570,13 +569,13 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *omap_disc1_readfn[] = {
+static CPUReadMemoryFunc * const omap_disc1_readfn[] = {
     omap_badwidth_read32,
     omap_badwidth_read32,
     omap_disc_read,
 };
 
-static CPUWriteMemoryFunc *omap_disc1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_disc1_writefn[] = {
     omap_badwidth_write32,
     omap_badwidth_write32,
     omap_disc_write,
@@ -628,7 +627,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
     }
     if (!data) {
         if (len > bounce_len) {
-            bounce_buffer = qemu_realloc(bounce_buffer, len);
+            bounce_buffer = g_realloc(bounce_buffer, len);
         }
         data = bounce_buffer;
         cpu_physical_memory_read(data_addr, data, len);
@@ -842,13 +841,13 @@ static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *omap_rfbi1_readfn[] = {
+static CPUReadMemoryFunc * const omap_rfbi1_readfn[] = {
     omap_badwidth_read32,
     omap_badwidth_read32,
     omap_rfbi_read,
 };
 
-static CPUWriteMemoryFunc *omap_rfbi1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = {
     omap_badwidth_write32,
     omap_badwidth_write32,
     omap_rfbi_write,
@@ -961,13 +960,13 @@ static void omap_venc_write(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *omap_venc1_readfn[] = {
+static CPUReadMemoryFunc * const omap_venc1_readfn[] = {
     omap_badwidth_read32,
     omap_badwidth_read32,
     omap_venc_read,
 };
 
-static CPUWriteMemoryFunc *omap_venc1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_venc1_writefn[] = {
     omap_badwidth_write32,
     omap_badwidth_write32,
     omap_venc_write,
@@ -1011,13 +1010,13 @@ static void omap_im3_write(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *omap_im3_readfn[] = {
+static CPUReadMemoryFunc * const omap_im3_readfn[] = {
     omap_badwidth_read32,
     omap_badwidth_read32,
     omap_im3_read,
 };
 
-static CPUWriteMemoryFunc *omap_im3_writefn[] = {
+static CPUWriteMemoryFunc * const omap_im3_writefn[] = {
     omap_badwidth_write32,
     omap_badwidth_write32,
     omap_im3_write,
@@ -1031,22 +1030,22 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
 {
     int iomemtype[5];
     struct omap_dss_s *s = (struct omap_dss_s *)
-            qemu_mallocz(sizeof(struct omap_dss_s));
+            g_malloc0(sizeof(struct omap_dss_s));
 
     s->irq = irq;
     s->drq = drq;
     omap_dss_reset(s);
 
-    iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn,
+    iomemtype[0] = l4_register_io_memory(omap_diss1_readfn,
                     omap_diss1_writefn, s);
-    iomemtype[1] = l4_register_io_memory(0, omap_disc1_readfn,
+    iomemtype[1] = l4_register_io_memory(omap_disc1_readfn,
                     omap_disc1_writefn, s);
-    iomemtype[2] = l4_register_io_memory(0, omap_rfbi1_readfn,
+    iomemtype[2] = l4_register_io_memory(omap_rfbi1_readfn,
                     omap_rfbi1_writefn, s);
-    iomemtype[3] = l4_register_io_memory(0, omap_venc1_readfn,
+    iomemtype[3] = l4_register_io_memory(omap_venc1_readfn,
                     omap_venc1_writefn, s);
-    iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn,
-                    omap_im3_writefn, s);
+    iomemtype[4] = cpu_register_io_memory(omap_im3_readfn,
+                    omap_im3_writefn, s, DEVICE_NATIVE_ENDIAN);
     omap_l4_attach(ta, 0, iomemtype[0]);
     omap_l4_attach(ta, 1, iomemtype[1]);
     omap_l4_attach(ta, 2, iomemtype[2]);
@@ -1064,6 +1063,6 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip)
 {
     if (cs < 0 || cs > 1)
-        cpu_abort(cpu_single_env, "%s: wrong CS %i\n", __FUNCTION__, cs);
+        hw_error("%s: wrong CS %i\n", __FUNCTION__, cs);
     s->rfbi.chip[cs] = chip;
 }