#include "hw/sysbus.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
-#include "hw/sparc/sun4m.h"
+#include "hw/sparc/sun4m_iommu.h"
#include "hw/timer/m48t59.h"
#include "hw/sparc/sparc32_dma.h"
#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/scsi/esp.h"
-#include "hw/i386/pc.h"
#include "hw/isa/isa.h"
#include "hw/nvram/sun_nvram.h"
#include "hw/nvram/chrp_nvram.h"
#include "hw/empty_slot.h"
#include "hw/loader.h"
#include "elf.h"
-#include "sysemu/block-backend.h"
#include "trace.h"
#include "qemu/cutils.h"
} vsimm[MAX_VSIMMS];
hwaddr ecc_base;
uint64_t max_mem;
- const char * const default_cpu_model;
uint32_t ecc_version;
uint32_t iommu_version;
uint16_t machine_id;
uint8_t nvram_machine_id;
};
-void DMA_init(ISABus *bus, int high_page_enable)
-{
-}
-
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
Error **errp)
{
KERNEL_LOAD_ADDR,
RAM_size - KERNEL_LOAD_ADDR);
if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
- kernel_filename);
+ error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
INITRD_LOAD_ADDR,
RAM_size - INITRD_LOAD_ADDR);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
- initrd_filename);
+ error_report("could not load initial ram disk '%s'",
+ initrd_filename);
exit(1);
}
}
DeviceState *dev;
SysBusDevice *s;
- dev = qdev_create(NULL, "iommu");
+ dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
qdev_prop_set_uint32(dev, "version", version);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
return s;
}
-static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
- void *iommu, qemu_irq *dev_irq, int is_ledma)
+static void *sparc32_dma_init(hwaddr dma_base,
+ hwaddr esp_base, qemu_irq espdma_irq,
+ hwaddr le_base, qemu_irq ledma_irq)
{
- DeviceState *dev;
- SysBusDevice *s;
+ DeviceState *dma;
+ ESPDMADeviceState *espdma;
+ LEDMADeviceState *ledma;
+ SysBusESPState *esp;
+ SysBusPCNetState *lance;
- dev = qdev_create(NULL, "sparc32_dma");
- qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
- qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- sysbus_connect_irq(s, 0, parent_irq);
- *dev_irq = qdev_get_gpio_in(dev, 0);
- sysbus_mmio_map(s, 0, daddr);
+ dma = qdev_create(NULL, TYPE_SPARC32_DMA);
+ qdev_init_nofail(dma);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
- return s;
-}
+ espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
+ OBJECT(dma), "espdma"));
+ sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
-static void lance_init(NICInfo *nd, hwaddr leaddr,
- void *dma_opaque, qemu_irq irq)
-{
- DeviceState *dev;
- SysBusDevice *s;
- qemu_irq reset;
+ esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
+ sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
+ scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
- qemu_check_nic_model(&nd_table[0], "lance");
+ ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
+ OBJECT(dma), "ledma"));
+ sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
- dev = qdev_create(NULL, "lance");
- qdev_set_nic_properties(dev, nd);
- qdev_prop_set_ptr(dev, "dma", dma_opaque);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(s, 0, leaddr);
- sysbus_connect_irq(s, 0, irq);
- reset = qdev_get_gpio_in(dev, 0);
- qdev_connect_gpio_out(dma_opaque, 0, reset);
+ lance = SYSBUS_PCNET(object_resolve_path_component(
+ OBJECT(ledma), "lance"));
+ sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
+
+ return dma;
}
static DeviceState *slavio_intctl_init(hwaddr addr,
ret = -1;
}
if (ret < 0 || ret > PROM_SIZE_MAX) {
- fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
+ error_report("could not load prom '%s'", bios_name);
exit(1);
}
}
/* allocate RAM */
if ((uint64_t)RAM_size > max_mem) {
- fprintf(stderr,
- "qemu: Too much memory for this machine: %d, maximum %d\n",
- (unsigned int)(RAM_size / (1024 * 1024)),
- (unsigned int)(max_mem / (1024 * 1024)));
+ error_report("Too much memory for this machine: %d, maximum %d",
+ (unsigned int)(RAM_size / (1024 * 1024)),
+ (unsigned int)(max_mem / (1024 * 1024)));
exit(1);
}
dev = qdev_create(NULL, "memory");
.class_init = ram_class_init,
};
-static void cpu_devinit(const char *cpu_model, unsigned int id,
+static void cpu_devinit(const char *cpu_type, unsigned int id,
uint64_t prom_addr, qemu_irq **cpu_irqs)
{
CPUState *cs;
SPARCCPU *cpu;
CPUSPARCState *env;
- cpu = cpu_sparc_init(cpu_model);
- if (cpu == NULL) {
- fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
- exit(1);
- }
+ cpu = SPARC_CPU(cpu_create(cpu_type));
env = &cpu->env;
cpu_sparc_set_id(env, id);
MachineState *machine)
{
DeviceState *slavio_intctl;
- const char *cpu_model = machine->cpu_model;
unsigned int i;
- void *iommu, *espdma, *ledma, *nvram;
- qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
- espdma_irq, ledma_irq;
- qemu_irq esp_reset, dma_enable;
+ void *nvram;
+ qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
qemu_irq fdc_tc;
unsigned long kernel_size;
DriveInfo *fd[MAX_FD];
FWCfgState *fw_cfg;
unsigned int num_vsimms;
+ DeviceState *dev;
+ SysBusDevice *s;
/* init CPUs */
- if (!cpu_model)
- cpu_model = hwdef->default_cpu_model;
-
for(i = 0; i < smp_cpus; i++) {
- cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
+ cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
}
for (i = smp_cpus; i < MAX_CPUS; i++)
afx_init(hwdef->afx_base);
}
- iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
- slavio_irq[30]);
+ iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
if (hwdef->iommu_pad_base) {
/* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
}
- espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
- iommu, &espdma_irq, 0);
-
- ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
- slavio_irq[16], iommu, &ledma_irq, 1);
+ sparc32_dma_init(hwdef->dma_base,
+ hwdef->esp_base, slavio_irq[18],
+ hwdef->le_base, slavio_irq[16]);
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
empty_slot_init(hwdef->sx_base, 0x2000);
}
- lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
-
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
- slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
- !machine->enable_graphics, ESCC_CLOCK, 1);
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
- escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
- serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
+ dev = qdev_create(NULL, TYPE_ESCC);
+ qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
+ qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
+ qdev_prop_set_uint32(dev, "it_shift", 1);
+ qdev_prop_set_chr(dev, "chrB", NULL);
+ qdev_prop_set_chr(dev, "chrA", NULL);
+ qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
+ qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(s, 0, slavio_irq[14]);
+ sysbus_connect_irq(s, 1, slavio_irq[14]);
+ sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
+
+ dev = qdev_create(NULL, TYPE_ESCC);
+ qdev_prop_set_uint32(dev, "disabled", 0);
+ qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
+ qdev_prop_set_uint32(dev, "it_shift", 1);
+ qdev_prop_set_chr(dev, "chrB", serial_hd(1));
+ qdev_prop_set_chr(dev, "chrA", serial_hd(0));
+ qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
+ qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
+ qdev_init_nofail(dev);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(s, 0, slavio_irq[15]);
+ sysbus_connect_irq(s, 1, slavio_irq[15]);
+ sysbus_mmio_map(s, 0, hwdef->serial_base);
if (hwdef->apc_base) {
apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
slavio_irq[30], fdc_tc);
- esp_init(hwdef->esp_base, 2,
- espdma_memory_read, espdma_memory_write,
- espdma, espdma_irq, &esp_reset, &dma_enable);
-
- qdev_connect_gpio_out(espdma, 0, esp_reset);
- qdev_connect_gpio_out(espdma, 1, dma_enable);
-
if (hwdef->cs_base) {
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
slavio_irq[5]);
.machine_id = ss5_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- .default_cpu_model = "Fujitsu MB86904",
},
/* SS-10 */
{
.machine_id = ss10_id,
.iommu_version = 0x03000000,
.max_mem = 0xf00000000ULL,
- .default_cpu_model = "TI SuperSparc II",
},
/* SS-600MP */
{
.machine_id = ss600mp_id,
.iommu_version = 0x01000000,
.max_mem = 0xf00000000ULL,
- .default_cpu_model = "TI SuperSparc II",
},
/* SS-20 */
{
.machine_id = ss20_id,
.iommu_version = 0x13000000,
.max_mem = 0xf00000000ULL,
- .default_cpu_model = "TI SuperSparc II",
},
/* Voyager */
{
.machine_id = vger_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- .default_cpu_model = "Fujitsu MB86904",
},
/* LX */
{
.machine_id = lx_id,
.iommu_version = 0x04000000,
.max_mem = 0x10000000,
- .default_cpu_model = "TI MicroSparc I",
},
/* SS-4 */
{
.machine_id = ss4_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- .default_cpu_model = "Fujitsu MB86904",
},
/* SPARCClassic */
{
.machine_id = scls_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- .default_cpu_model = "TI MicroSparc I",
},
/* SPARCbook */
{
.machine_id = sbook_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- .default_cpu_model = "TI MicroSparc I",
},
};
mc->block_default_type = IF_SCSI;
mc->is_default = 1;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
}
static const TypeInfo ss5_type = {
mc->block_default_type = IF_SCSI;
mc->max_cpus = 4;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
}
static const TypeInfo ss10_type = {
mc->block_default_type = IF_SCSI;
mc->max_cpus = 4;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
}
static const TypeInfo ss600mp_type = {
mc->block_default_type = IF_SCSI;
mc->max_cpus = 4;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
}
static const TypeInfo ss20_type = {
mc->init = vger_init;
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
}
static const TypeInfo voyager_type = {
mc->init = ss_lx_init;
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
}
static const TypeInfo ss_lx_type = {
mc->init = ss4_init;
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
}
static const TypeInfo ss4_type = {
mc->init = scls_init;
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
}
static const TypeInfo scls_type = {
mc->init = sbook_init;
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
}
static const TypeInfo sbook_type = {
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