Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging

[qemu.git] / hw / pci / msix.c

diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 031eaabca9de1609e1d76204869dc03016f7e6ba..4e336416a78a66a2fecfe3f77f217e6276d86a50 100644 (file)
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -14,11 +14,15 @@
  * GNU GPL, version 2 or (at your option) any later version.
  */
 
  * GNU GPL, version 2 or (at your option) any later version.
  */
 

+#include "qemu/osdep.h"

 #include "hw/hw.h"
 #include "hw/pci/msi.h"
 #include "hw/pci/msix.h"
 #include "hw/pci/pci.h"
 #include "hw/hw.h"
 #include "hw/pci/msi.h"
 #include "hw/pci/msix.h"
 #include "hw/pci/pci.h"

+#include "hw/xen/xen.h"

 #include "qemu/range.h"
 #include "qemu/range.h"

+#include "qapi/error.h"
+#include "trace.h"

 
 #define MSIX_CAP_LENGTH 12
 
 
 #define MSIX_CAP_LENGTH 12
 


@@ -70,15 +74,22 @@ void msix_set_pending(PCIDevice *dev, unsigned int vector)
     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 }
 
     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 }
 

-static void msix_clr_pending(PCIDevice *dev, int vector)
+void msix_clr_pending(PCIDevice *dev, int vector)

 {
     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 }
 
 static bool msix_vector_masked(PCIDevice *dev, unsigned int vector, bool fmask)
 {
 {
     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 }
 
 static bool msix_vector_masked(PCIDevice *dev, unsigned int vector, bool fmask)
 {

-    unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
-    return fmask || dev->msix_table[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
+    unsigned offset = vector * PCI_MSIX_ENTRY_SIZE;
+    uint8_t *data = &dev->msix_table[offset + PCI_MSIX_ENTRY_DATA];
+    /* MSIs on Xen can be remapped into pirqs. In those cases, masking
+     * and unmasking go through the PV evtchn path. */
+    if (xen_enabled() && xen_is_pirq_msi(pci_get_long(data))) {
+        return false;
+    }
+    return fmask || dev->msix_table[offset + PCI_MSIX_ENTRY_VECTOR_CTRL] &
+        PCI_MSIX_ENTRY_CTRL_MASKBIT;

 }
 
 bool msix_is_masked(PCIDevice *dev, unsigned int vector)
 }
 
 bool msix_is_masked(PCIDevice *dev, unsigned int vector)


@@ -120,10 +131,14 @@ static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
     }
 }
 
     }
 }
 

+static bool msix_masked(PCIDevice *dev)
+{
+    return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
+}
+

 static void msix_update_function_masked(PCIDevice *dev)
 {
 static void msix_update_function_masked(PCIDevice *dev)
 {

-    dev->msix_function_masked = !msix_enabled(dev) ||
-        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
+    dev->msix_function_masked = !msix_enabled(dev) || msix_masked(dev);

 }
 
 /* Handle MSI-X capability config write. */
 }
 
 /* Handle MSI-X capability config write. */


@@ -138,6 +153,8 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
         return;
     }
 
         return;
     }
 

+    trace_msix_write_config(dev->name, msix_enabled(dev), msix_masked(dev));
+

     was_masked = dev->msix_function_masked;
     msix_update_function_masked(dev);
 
     was_masked = dev->msix_function_masked;
     msix_update_function_masked(dev);
 


@@ -200,8 +217,14 @@ static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
     return pci_get_long(dev->msix_pba + addr);
 }
 
     return pci_get_long(dev->msix_pba + addr);
 }
 

+static void msix_pba_mmio_write(void *opaque, hwaddr addr,
+                                uint64_t val, unsigned size)
+{
+}
+

 static const MemoryRegionOps msix_pba_mmio_ops = {
     .read = msix_pba_mmio_read,
 static const MemoryRegionOps msix_pba_mmio_ops = {
     .read = msix_pba_mmio_read,

+    .write = msix_pba_mmio_write,

     .endianness = DEVICE_LITTLE_ENDIAN,
     .valid = {
         .min_access_size = 4,
     .endianness = DEVICE_LITTLE_ENDIAN,
     .valid = {
         .min_access_size = 4,


@@ -223,22 +246,44 @@ static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
     }
 }
 
     }
 }
 

-/* Initialize the MSI-X structures */
+/*
+ * Make PCI device @dev MSI-X capable
+ * @nentries is the max number of MSI-X vectors that the device support.
+ * @table_bar is the MemoryRegion that MSI-X table structure resides.
+ * @table_bar_nr is number of base address register corresponding to @table_bar.
+ * @table_offset indicates the offset that the MSI-X table structure starts with
+ * in @table_bar.
+ * @pba_bar is the MemoryRegion that the Pending Bit Array structure resides.
+ * @pba_bar_nr is number of base address register corresponding to @pba_bar.
+ * @pba_offset indicates the offset that the Pending Bit Array structure
+ * starts with in @pba_bar.
+ * Non-zero @cap_pos puts capability MSI-X at that offset in PCI config space.
+ * @errp is for returning errors.
+ *
+ * Return 0 on success; set @errp and return -errno on error:
+ * -ENOTSUP means lacking msi support for a msi-capable platform.
+ * -EINVAL means capability overlap, happens when @cap_pos is non-zero,
+ * also means a programming error, except device assignment, which can check
+ * if a real HW is broken.
+ */

 int msix_init(struct PCIDevice *dev, unsigned short nentries,
               MemoryRegion *table_bar, uint8_t table_bar_nr,
               unsigned table_offset, MemoryRegion *pba_bar,
 int msix_init(struct PCIDevice *dev, unsigned short nentries,
               MemoryRegion *table_bar, uint8_t table_bar_nr,
               unsigned table_offset, MemoryRegion *pba_bar,

-              uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos)
+              uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos,
+              Error **errp)

 {
     int cap;
     unsigned table_size, pba_size;
     uint8_t *config;
 
     /* Nothing to do if MSI is not supported by interrupt controller */
 {
     int cap;
     unsigned table_size, pba_size;
     uint8_t *config;
 
     /* Nothing to do if MSI is not supported by interrupt controller */

-    if (!msi_supported) {
+    if (!msi_nonbroken) {
+        error_setg(errp, "MSI-X is not supported by interrupt controller");

         return -ENOTSUP;
     }
 
     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {
         return -ENOTSUP;
     }
 
     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {

+        error_setg(errp, "The number of MSI-X vectors is invalid");

         return -EINVAL;
     }
 
         return -EINVAL;
     }
 


@@ -251,10 +296,13 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
         table_offset + table_size > memory_region_size(table_bar) ||
         pba_offset + pba_size > memory_region_size(pba_bar) ||
         (table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {
         table_offset + table_size > memory_region_size(table_bar) ||
         pba_offset + pba_size > memory_region_size(pba_bar) ||
         (table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {

+        error_setg(errp, "table & pba overlap, or they don't fit in BARs,"
+                   " or don't align");

         return -EINVAL;
     }
 
         return -EINVAL;
     }
 

-    cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH);
+    cap = pci_add_capability(dev, PCI_CAP_ID_MSIX,
+                              cap_pos, MSIX_CAP_LENGTH, errp);

     if (cap < 0) {
         return cap;
     }
     if (cap < 0) {
         return cap;
     }


@@ -291,33 +339,39 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
 }
 
 int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
 }
 
 int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,

-                            uint8_t bar_nr)
+                            uint8_t bar_nr, Error **errp)

 {
     int ret;
     char *name;
 {
     int ret;
     char *name;

+    uint32_t bar_size = 4096;
+    uint32_t bar_pba_offset = bar_size / 2;
+    uint32_t bar_pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;

 
     /*
      * Migration compatibility dictates that this remains a 4k
      * BAR with the vector table in the lower half and PBA in
 
     /*
      * Migration compatibility dictates that this remains a 4k
      * BAR with the vector table in the lower half and PBA in

-     * the upper half.  Do not use these elsewhere!
+     * the upper half for nentries which is lower or equal to 128.
+     * No need to care about using more than 65 entries for legacy
+     * machine types who has at most 64 queues.

      */
      */

-#define MSIX_EXCLUSIVE_BAR_SIZE 4096
-#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0
-#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)
-#define MSIX_EXCLUSIVE_CAP_OFFSET 0
+    if (nentries * PCI_MSIX_ENTRY_SIZE > bar_pba_offset) {
+        bar_pba_offset = nentries * PCI_MSIX_ENTRY_SIZE;
+    }

 
 

-    if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {
-        return -EINVAL;
+    if (bar_pba_offset + bar_pba_size > 4096) {
+        bar_size = bar_pba_offset + bar_pba_size;

     }
 
     }
 

+    bar_size = pow2ceil(bar_size);
+

     name = g_strdup_printf("%s-msix", dev->name);
     name = g_strdup_printf("%s-msix", dev->name);

-    memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, MSIX_EXCLUSIVE_BAR_SIZE);
+    memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, bar_size);

     g_free(name);
 
     ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
     g_free(name);
 
     ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,

-                    MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar,
-                    bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,
-                    MSIX_EXCLUSIVE_CAP_OFFSET);
+                    0, &dev->msix_exclusive_bar,
+                    bar_nr, bar_pba_offset,
+                    0, errp);

     if (ret) {
         return ret;
     }
     if (ret) {
         return ret;
     }


@@ -384,7 +438,7 @@ void msix_save(PCIDevice *dev, QEMUFile *f)
     }
 
     qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
     }
 
     qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);

-    qemu_put_buffer(f, dev->msix_pba, (n + 7) / 8);
+    qemu_put_buffer(f, dev->msix_pba, DIV_ROUND_UP(n, 8));

 }
 
 /* Should be called after restoring the config space. */
 }
 
 /* Should be called after restoring the config space. */


@@ -399,7 +453,7 @@ void msix_load(PCIDevice *dev, QEMUFile *f)
 
     msix_clear_all_vectors(dev);
     qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
 
     msix_clear_all_vectors(dev);
     qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);

-    qemu_get_buffer(f, dev->msix_pba, (n + 7) / 8);
+    qemu_get_buffer(f, dev->msix_pba, DIV_ROUND_UP(n, 8));

     msix_update_function_masked(dev);
 
     for (vector = 0; vector < n; vector++) {
     msix_update_function_masked(dev);
 
     for (vector = 0; vector < n; vector++) {


@@ -426,8 +480,10 @@ void msix_notify(PCIDevice *dev, unsigned vector)
 {
     MSIMessage msg;
 
 {
     MSIMessage msg;
 

-    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
+    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {

         return;
         return;

+    }
+

     if (msix_is_masked(dev, vector)) {
         msix_set_pending(dev, vector);
         return;
     if (msix_is_masked(dev, vector)) {
         msix_set_pending(dev, vector);
         return;


@@ -435,8 +491,7 @@ void msix_notify(PCIDevice *dev, unsigned vector)
 
     msg = msix_get_message(dev, vector);
 
 
     msg = msix_get_message(dev, vector);
 

-    address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
-                         MEMTXATTRS_UNSPECIFIED, NULL);
+    msi_send_message(dev, msg);

 }
 
 void msix_reset(PCIDevice *dev)
 }
 
 void msix_reset(PCIDevice *dev)


@@ -446,7 +501,7 @@ void msix_reset(PCIDevice *dev)
     }
     msix_clear_all_vectors(dev);
     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
     }
     msix_clear_all_vectors(dev);
     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=

-           ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
+            ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];

     memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
     memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
     msix_mask_all(dev, dev->msix_entries_nr);
     memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
     memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
     msix_mask_all(dev, dev->msix_entries_nr);


@@ -463,8 +518,10 @@ void msix_reset(PCIDevice *dev)
 /* Mark vector as used. */
 int msix_vector_use(PCIDevice *dev, unsigned vector)
 {
 /* Mark vector as used. */
 int msix_vector_use(PCIDevice *dev, unsigned vector)
 {

-    if (vector >= dev->msix_entries_nr)
+    if (vector >= dev->msix_entries_nr) {

         return -EINVAL;
         return -EINVAL;

+    }
+

     dev->msix_entry_used[vector]++;
     return 0;
 }
     dev->msix_entry_used[vector]++;
     return 0;
 }


@@ -567,12 +624,16 @@ void msix_unset_vector_notifiers(PCIDevice *dev)
     dev->msix_vector_poll_notifier = NULL;
 }
 
     dev->msix_vector_poll_notifier = NULL;
 }
 

-static void put_msix_state(QEMUFile *f, void *pv, size_t size)
+static int put_msix_state(QEMUFile *f, void *pv, size_t size,
+                          const VMStateField *field, QJSON *vmdesc)

 {
     msix_save(pv, f);
 {
     msix_save(pv, f);

+
+    return 0;

 }
 
 }
 

-static int get_msix_state(QEMUFile *f, void *pv, size_t size)
+static int get_msix_state(QEMUFile *f, void *pv, size_t size,
+                          const VMStateField *field)

 {
     msix_load(pv, f);
     return 0;
 {
     msix_load(pv, f);
     return 0;