#include "qemu-char.h"
#include "isa.h"
#include "pc.h"
+#include "sysemu.h"
//#define DEBUG_PARALLEL
#ifdef DEBUG_PARALLEL
-#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
+#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
#else
-#define pdebug(fmt, arg...) ((void)0)
+#define pdebug(fmt, ...) ((void)0)
#endif
#define PARA_REG_DATA 0
#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
-struct ParallelState {
+typedef struct ParallelState {
uint8_t dataw;
uint8_t datar;
uint8_t status;
int epp_timeout;
uint32_t last_read_offset; /* For debugging */
/* Memory-mapped interface */
- target_phys_addr_t base;
int it_shift;
-};
+} ParallelState;
+
+typedef struct ISAParallelState {
+ ISADevice dev;
+ uint32_t index;
+ uint32_t iobase;
+ uint32_t isairq;
+ ParallelState state;
+} ISAParallelState;
static void parallel_update_irq(ParallelState *s)
{
if (val & PARA_CTR_STROBE) {
s->status &= ~PARA_STS_BUSY;
if ((s->control & PARA_CTR_STROBE) == 0)
- qemu_chr_write(s->chr, &s->dataw, 1);
+ qemu_chr_fe_write(s->chr, &s->dataw, 1);
} else {
if (s->control & PARA_CTR_INTEN) {
s->irq_pending = 1;
{
ParallelState *s = opaque;
uint8_t parm = val;
+ int dir;
/* Sometimes programs do several writes for timing purposes on old
HW. Take care not to waste time on writes that do nothing. */
if (s->dataw == val)
return;
pdebug("wd%02x\n", val);
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
s->dataw = val;
break;
case PARA_REG_STS:
if (s->control == val)
return;
pdebug("wc%02x\n", val);
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
+
+ if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
+ if (val & PARA_CTR_DIR) {
+ dir = 1;
+ } else {
+ dir = 0;
+ }
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
+ parm &= ~PARA_CTR_DIR;
+ }
+
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
s->control = val;
break;
case PARA_REG_EPP_ADDR:
pdebug("wa%02x s\n", val);
else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
s->epp_timeout = 1;
pdebug("wa%02x t\n", val);
}
pdebug("we%02x s\n", val);
else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
s->epp_timeout = 1;
pdebug("we%02x t\n", val);
}
pdebug("we%04x s\n", val);
return;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
s->epp_timeout = 1;
pdebug("we%04x t\n", val);
pdebug("we%08x s\n", val);
return;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
s->epp_timeout = 1;
pdebug("we%08x t\n", val);
addr &= 7;
switch(addr) {
case PARA_REG_DATA:
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
if (s->last_read_offset != addr || s->datar != ret)
pdebug("rd%02x\n", ret);
s->datar = ret;
break;
case PARA_REG_STS:
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
ret &= ~PARA_STS_TMOUT;
if (s->epp_timeout)
ret |= PARA_STS_TMOUT;
/* s->control has some bits fixed to 1. It is zero only when
it has not been yet written to. */
if (s->control == 0) {
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
if (s->last_read_offset != addr)
pdebug("rc%02x\n", ret);
s->control = ret;
pdebug("ra%02x s\n", ret);
else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
s->epp_timeout = 1;
pdebug("ra%02x t\n", ret);
}
pdebug("re%02x s\n", ret);
else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
s->epp_timeout = 1;
pdebug("re%02x t\n", ret);
}
pdebug("re%04x s\n", eppdata);
return eppdata;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le16_to_cpu(eppdata);
if (err) {
pdebug("re%08x s\n", eppdata);
return eppdata;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le32_to_cpu(eppdata);
if (err) {
static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
- addr &= 7;
- pdebug("wecp%d=%02x\n", addr, val);
+ pdebug("wecp%d=%02x\n", addr & 7, val);
}
static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
uint8_t ret = 0xff;
- addr &= 7;
- pdebug("recp%d:%02x\n", addr, ret);
+
+ pdebug("recp%d:%02x\n", addr & 7, ret);
return ret;
}
-static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
+static void parallel_reset(void *opaque)
{
+ ParallelState *s = opaque;
+
s->datar = ~0;
s->dataw = ~0;
s->status = PARA_STS_BUSY;
s->control = PARA_CTR_SELECT;
s->control |= PARA_CTR_INIT;
s->control |= 0xc0;
- s->irq = irq;
s->irq_pending = 0;
- s->chr = chr;
s->hw_driver = 0;
s->epp_timeout = 0;
s->last_read_offset = ~0U;
}
-/* If fd is zero, it means that the parallel device uses the console */
-ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
+static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
+
+static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
+ { 0, 8, 1,
+ .read = parallel_ioport_read_hw,
+ .write = parallel_ioport_write_hw },
+ { 4, 1, 2,
+ .read = parallel_ioport_eppdata_read_hw2,
+ .write = parallel_ioport_eppdata_write_hw2 },
+ { 4, 1, 4,
+ .read = parallel_ioport_eppdata_read_hw4,
+ .write = parallel_ioport_eppdata_write_hw4 },
+ { 0x400, 8, 1,
+ .read = parallel_ioport_ecp_read,
+ .write = parallel_ioport_ecp_write },
+ PORTIO_END_OF_LIST(),
+};
+
+static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
+ { 0, 8, 1,
+ .read = parallel_ioport_read_sw,
+ .write = parallel_ioport_write_sw },
+ PORTIO_END_OF_LIST(),
+};
+
+static int parallel_isa_initfn(ISADevice *dev)
{
- ParallelState *s;
+ static int index;
+ ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
+ ParallelState *s = &isa->state;
+ int base;
uint8_t dummy;
- s = qemu_mallocz(sizeof(ParallelState));
- if (!s)
- return NULL;
- parallel_reset(s, irq, chr);
+ if (!s->chr) {
+ fprintf(stderr, "Can't create parallel device, empty char device\n");
+ exit(1);
+ }
+
+ if (isa->index == -1)
+ isa->index = index;
+ if (isa->index >= MAX_PARALLEL_PORTS)
+ return -1;
+ if (isa->iobase == -1)
+ isa->iobase = isa_parallel_io[isa->index];
+ index++;
+
+ base = isa->iobase;
+ isa_init_irq(dev, &s->irq, isa->isairq);
+ qemu_register_reset(parallel_reset, s);
- if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
s->status = dummy;
}
- if (s->hw_driver) {
- register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
- register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
- register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
- register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
- register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
- register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
- register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
- register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
- }
- else {
- register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
- register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
- }
- return s;
+ isa_register_portio_list(dev, base,
+ (s->hw_driver
+ ? &isa_parallel_portio_hw_list[0]
+ : &isa_parallel_portio_sw_list[0]),
+ s, "parallel");
+ return 0;
}
/* Memory mapped interface */
{
ParallelState *s = opaque;
- return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
+ return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
}
static void parallel_mm_writeb (void *opaque,
{
ParallelState *s = opaque;
- parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
+ parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}
static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
- return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
+ return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
}
static void parallel_mm_writew (void *opaque,
{
ParallelState *s = opaque;
- parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
+ parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}
static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
- return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
+ return parallel_ioport_read_sw(s, addr >> s->it_shift);
}
static void parallel_mm_writel (void *opaque,
{
ParallelState *s = opaque;
- parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
+ parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
+static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
¶llel_mm_readb,
¶llel_mm_readw,
¶llel_mm_readl,
};
-static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
+static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
¶llel_mm_writeb,
¶llel_mm_writew,
¶llel_mm_writel,
};
/* If fd is zero, it means that the parallel device uses the console */
-ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
+bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
+ CharDriverState *chr)
{
ParallelState *s;
int io_sw;
- s = qemu_mallocz(sizeof(ParallelState));
- if (!s)
- return NULL;
- parallel_reset(s, irq, chr);
- s->base = base;
+ s = g_malloc0(sizeof(ParallelState));
+ s->irq = irq;
+ s->chr = chr;
s->it_shift = it_shift;
+ qemu_register_reset(parallel_reset, s);
- io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
+ io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw,
+ s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
- return s;
+ return true;
+}
+
+static ISADeviceInfo parallel_isa_info = {
+ .qdev.name = "isa-parallel",
+ .qdev.size = sizeof(ISAParallelState),
+ .init = parallel_isa_initfn,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
+ DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1),
+ DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
+ DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+static void parallel_register_devices(void)
+{
+ isa_qdev_register(¶llel_isa_info);
}
+
+device_init(parallel_register_devices)
projects / qemu.git / blobdiff