/*
* PowerPC emulation cpu definitions for qemu.
- *
+ *
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
#define __CPU_PPC_H__
#include "config.h"
-#include <stdint.h>
-
-#if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)
-/* When using 64 bits temporary registers,
- * we can use 64 bits GPR with no extra cost
- */
-#define TARGET_PPCSPE
-#endif
+#include <inttypes.h>
#if defined (TARGET_PPC64)
typedef uint64_t ppc_gpr_t;
-#define TARGET_LONG_BITS 64
#define TARGET_GPR_BITS 64
+#define TARGET_LONG_BITS 64
#define REGX "%016" PRIx64
-#elif defined(TARGET_PPCSPE)
+#define TARGET_PAGE_BITS 12
+#elif defined(TARGET_PPCEMB)
+/* BookE have 36 bits physical address space */
+#define TARGET_PHYS_ADDR_BITS 64
/* GPR are 64 bits: used by vector extension */
typedef uint64_t ppc_gpr_t;
+#define TARGET_GPR_BITS 64
#define TARGET_LONG_BITS 32
+#define REGX "%016" PRIx64
+#if defined(CONFIG_USER_ONLY)
+/* It looks like a lot of Linux programs assume page size
+ * is 4kB long. This is evil, but we have to deal with it...
+ */
+#define TARGET_PAGE_BITS 12
+#else
+/* Pages can be 1 kB small */
+#define TARGET_PAGE_BITS 10
+#endif
+#else
+#if (HOST_LONG_BITS >= 64)
+/* When using 64 bits temporary registers,
+ * we can use 64 bits GPR with no extra cost
+ * It's even an optimization as it will prevent
+ * the compiler to do unuseful masking in the micro-ops.
+ */
+typedef uint64_t ppc_gpr_t;
#define TARGET_GPR_BITS 64
-#define REGX "%08" PRIx32
+#define REGX "%08" PRIx64
#else
typedef uint32_t ppc_gpr_t;
-#define TARGET_LONG_BITS 32
#define TARGET_GPR_BITS 32
#define REGX "%08" PRIx32
#endif
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 12
+#endif
#include "cpu-defs.h"
+#define ADDRX TARGET_FMT_lx
+#define PADDRX TARGET_FMT_plx
+
#include <setjmp.h>
#include "softfloat.h"
#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32
-/* XXX: put this in a common place */
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-
/*****************************************************************************/
-/* PVR definitions for most known PowerPC */
-enum {
- /* PowerPC 401 cores */
- CPU_PPC_401A1 = 0x00210000,
- CPU_PPC_401B2 = 0x00220000,
- CPU_PPC_401C2 = 0x00230000,
- CPU_PPC_401D2 = 0x00240000,
- CPU_PPC_401E2 = 0x00250000,
- CPU_PPC_401F2 = 0x00260000,
- CPU_PPC_401G2 = 0x00270000,
-#define CPU_PPC_401 CPU_PPC_401G2
- CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
- CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
- /* PowerPC 403 cores */
- CPU_PPC_403GA = 0x00200011,
- CPU_PPC_403GB = 0x00200100,
- CPU_PPC_403GC = 0x00200200,
- CPU_PPC_403GCX = 0x00201400,
-#define CPU_PPC_403 CPU_PPC_403GCX
- /* PowerPC 405 cores */
- CPU_PPC_405CR = 0x40110145,
-#define CPU_PPC_405GP CPU_PPC_405CR
- CPU_PPC_405EP = 0x51210950,
- CPU_PPC_405GPR = 0x50910951,
- CPU_PPC_405D2 = 0x20010000,
- CPU_PPC_405D4 = 0x41810000,
-#define CPU_PPC_405 CPU_PPC_405D4
- CPU_PPC_NPE405H = 0x414100C0,
- CPU_PPC_NPE405H2 = 0x41410140,
- CPU_PPC_NPE405L = 0x416100C0,
- /* XXX: missing 405LP, LC77700 */
- /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
-#if 0
- CPU_PPC_STB01000 = xxx,
-#endif
-#if 0
- CPU_PPC_STB01010 = xxx,
-#endif
-#if 0
- CPU_PPC_STB0210 = xxx,
-#endif
- CPU_PPC_STB03 = 0x40310000,
-#if 0
- CPU_PPC_STB043 = xxx,
-#endif
-#if 0
- CPU_PPC_STB045 = xxx,
-#endif
- CPU_PPC_STB25 = 0x51510950,
-#if 0
- CPU_PPC_STB130 = xxx,
-#endif
- /* Xilinx cores */
- CPU_PPC_X2VP4 = 0x20010820,
-#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
- CPU_PPC_X2VP20 = 0x20010860,
-#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
- /* PowerPC 440 cores */
- CPU_PPC_440EP = 0x422218D3,
-#define CPU_PPC_440GR CPU_PPC_440EP
- CPU_PPC_440GP = 0x40120481,
- CPU_PPC_440GX = 0x51B21850,
- CPU_PPC_440GXc = 0x51B21892,
- CPU_PPC_440GXf = 0x51B21894,
- CPU_PPC_440SP = 0x53221850,
- CPU_PPC_440SP2 = 0x53221891,
- CPU_PPC_440SPE = 0x53421890,
- /* XXX: missing 440GRX */
- /* PowerPC 460 cores - TODO */
- /* PowerPC MPC 5xx cores */
- CPU_PPC_5xx = 0x00020020,
- /* PowerPC MPC 8xx cores (aka PowerQUICC) */
- CPU_PPC_8xx = 0x00500000,
- /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
- CPU_PPC_82xx_HIP3 = 0x00810101,
- CPU_PPC_82xx_HIP4 = 0x80811014,
- CPU_PPC_827x = 0x80822013,
- /* eCores */
- CPU_PPC_e200 = 0x81120000,
- CPU_PPC_e500v110 = 0x80200010,
- CPU_PPC_e500v120 = 0x80200020,
- CPU_PPC_e500v210 = 0x80210010,
- CPU_PPC_e500v220 = 0x80210020,
-#define CPU_PPC_e500 CPU_PPC_e500v220
- CPU_PPC_e600 = 0x80040010,
- /* PowerPC 6xx cores */
- CPU_PPC_601 = 0x00010001,
- CPU_PPC_602 = 0x00050100,
- CPU_PPC_603 = 0x00030100,
- CPU_PPC_603E = 0x00060101,
- CPU_PPC_603P = 0x00070000,
- CPU_PPC_603E7v = 0x00070100,
- CPU_PPC_603E7v2 = 0x00070201,
- CPU_PPC_603E7 = 0x00070200,
- CPU_PPC_603R = 0x00071201,
- CPU_PPC_G2 = 0x00810011,
- CPU_PPC_G2H4 = 0x80811010,
- CPU_PPC_G2gp = 0x80821010,
- CPU_PPC_G2ls = 0x90810010,
- CPU_PPC_G2LE = 0x80820010,
- CPU_PPC_G2LEgp = 0x80822010,
- CPU_PPC_G2LEls = 0xA0822010,
- CPU_PPC_604 = 0x00040000,
- CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */
- CPU_PPC_604R = 0x000a0101,
- /* PowerPC 74x/75x cores (aka G3) */
- CPU_PPC_74x = 0x00080000,
- CPU_PPC_740E = 0x00080100,
- CPU_PPC_750E = 0x00080200,
- CPU_PPC_755_10 = 0x00083100,
- CPU_PPC_755_11 = 0x00083101,
- CPU_PPC_755_20 = 0x00083200,
- CPU_PPC_755D = 0x00083202,
- CPU_PPC_755E = 0x00083203,
-#define CPU_PPC_755 CPU_PPC_755E
- CPU_PPC_74xP = 0x10080000,
- CPU_PPC_750CXE21 = 0x00082201,
- CPU_PPC_750CXE22 = 0x00082212,
- CPU_PPC_750CXE23 = 0x00082203,
- CPU_PPC_750CXE24 = 0x00082214,
- CPU_PPC_750CXE24b = 0x00083214,
- CPU_PPC_750CXE31 = 0x00083211,
- CPU_PPC_750CXE31b = 0x00083311,
-#define CPU_PPC_750CXE CPU_PPC_750CXE31b
- CPU_PPC_750CXR = 0x00083410,
- CPU_PPC_750FX10 = 0x70000100,
- CPU_PPC_750FX20 = 0x70000200,
- CPU_PPC_750FX21 = 0x70000201,
- CPU_PPC_750FX22 = 0x70000202,
- CPU_PPC_750FX23 = 0x70000203,
-#define CPU_PPC_750FX CPU_PPC_750FX23
- CPU_PPC_750FL = 0x700A0203,
- CPU_PPC_750GX10 = 0x70020100,
- CPU_PPC_750GX11 = 0x70020101,
- CPU_PPC_750GX12 = 0x70020102,
-#define CPU_PPC_750GX CPU_PPC_750GX12
- CPU_PPC_750GL = 0x70020102,
- CPU_PPC_750L30 = 0x00088300,
- CPU_PPC_750L32 = 0x00088302,
- CPU_PPC_750CL = 0x00087200,
- /* PowerPC 74xx cores (aka G4) */
- CPU_PPC_7400 = 0x000C0100,
- CPU_PPC_7410C = 0x800C1102,
- CPU_PPC_7410D = 0x800C1103,
- CPU_PPC_7410E = 0x800C1104,
- CPU_PPC_7441 = 0x80000210,
- CPU_PPC_7445 = 0x80010100,
- CPU_PPC_7447 = 0x80020100,
- CPU_PPC_7447A = 0x80030101,
- CPU_PPC_7448 = 0x80040100,
- CPU_PPC_7450 = 0x80000200,
- CPU_PPC_7450b = 0x80000201,
- CPU_PPC_7451 = 0x80000203,
- CPU_PPC_7451G = 0x80000210,
- CPU_PPC_7455 = 0x80010201,
- CPU_PPC_7455F = 0x80010303,
- CPU_PPC_7455G = 0x80010304,
- CPU_PPC_7457 = 0x80020101,
- CPU_PPC_7457C = 0x80020102,
- CPU_PPC_7457A = 0x80030000,
- /* 64 bits PowerPC */
- CPU_PPC_620 = 0x00140000,
- CPU_PPC_630 = 0x00400000,
- CPU_PPC_631 = 0x00410000,
- CPU_PPC_POWER4 = 0x00350000,
- CPU_PPC_POWER4P = 0x00380000,
- CPU_PPC_POWER5 = 0x003A0000,
- CPU_PPC_POWER5P = 0x003B0000,
- CPU_PPC_970 = 0x00390000,
- CPU_PPC_970FX10 = 0x00391100,
- CPU_PPC_970FX20 = 0x003C0200,
- CPU_PPC_970FX21 = 0x003C0201,
- CPU_PPC_970FX30 = 0x003C0300,
- CPU_PPC_970FX31 = 0x003C0301,
-#define CPU_PPC_970FX CPU_PPC_970FX31
- CPU_PPC_970MP10 = 0x00440100,
- CPU_PPC_970MP11 = 0x00440101,
-#define CPU_PPC_970MP CPU_PPC_970MP11
- CPU_PPC_CELL10 = 0x00700100,
- CPU_PPC_CELL20 = 0x00700400,
- CPU_PPC_CELL30 = 0x00700500,
- CPU_PPC_CELL31 = 0x00700501,
-#define CPU_PPC_CELL32 CPU_PPC_CELL31
-#define CPU_PPC_CELL CPU_PPC_CELL32
- CPU_PPC_RS64 = 0x00330000,
- CPU_PPC_RS64II = 0x00340000,
- CPU_PPC_RS64III = 0x00360000,
- CPU_PPC_RS64IV = 0x00370000,
- /* Original POWER */
- /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
- * POWER2 (RIOS2) & RSC2 (P2SC) here
- */
-#if 0
- CPU_POWER = xxx,
-#endif
-#if 0
- CPU_POWER2 = xxx,
-#endif
-};
-
-/* System version register (used on MPC 8xxx) */
+/* MMU model */
enum {
- PPC_SVR_8540 = 0x80300000,
- PPC_SVR_8541E = 0x807A0010,
- PPC_SVR_8543v10 = 0x80320010,
- PPC_SVR_8543v11 = 0x80320011,
- PPC_SVR_8543v20 = 0x80320020,
- PPC_SVR_8543Ev10 = 0x803A0010,
- PPC_SVR_8543Ev11 = 0x803A0011,
- PPC_SVR_8543Ev20 = 0x803A0020,
- PPC_SVR_8545 = 0x80310220,
- PPC_SVR_8545E = 0x80390220,
- PPC_SVR_8547E = 0x80390120,
- PPC_SCR_8548v10 = 0x80310010,
- PPC_SCR_8548v11 = 0x80310011,
- PPC_SCR_8548v20 = 0x80310020,
- PPC_SVR_8548Ev10 = 0x80390010,
- PPC_SVR_8548Ev11 = 0x80390011,
- PPC_SVR_8548Ev20 = 0x80390020,
- PPC_SVR_8555E = 0x80790010,
- PPC_SVR_8560v10 = 0x80700010,
- PPC_SVR_8560v20 = 0x80700020,
+ POWERPC_MMU_UNKNOWN = 0,
+ /* Standard 32 bits PowerPC MMU */
+ POWERPC_MMU_32B,
+ /* Standard 64 bits PowerPC MMU */
+ POWERPC_MMU_64B,
+ /* PowerPC 601 MMU */
+ POWERPC_MMU_601,
+ /* PowerPC 6xx MMU with software TLB */
+ POWERPC_MMU_SOFT_6xx,
+ /* PowerPC 74xx MMU with software TLB */
+ POWERPC_MMU_SOFT_74xx,
+ /* PowerPC 4xx MMU with software TLB */
+ POWERPC_MMU_SOFT_4xx,
+ /* PowerPC 4xx MMU with software TLB and zones protections */
+ POWERPC_MMU_SOFT_4xx_Z,
+ /* PowerPC 4xx MMU in real mode only */
+ POWERPC_MMU_REAL_4xx,
+ /* BookE MMU model */
+ POWERPC_MMU_BOOKE,
+ /* BookE FSL MMU model */
+ POWERPC_MMU_BOOKE_FSL,
+ /* 64 bits "bridge" PowerPC MMU */
+ POWERPC_MMU_64BRIDGE,
};
/*****************************************************************************/
-/* Instruction types */
+/* Exception model */
enum {
- PPC_NONE = 0x00000000,
- /* integer operations instructions */
- /* flow control instructions */
- /* virtual memory instructions */
- /* ld/st with reservation instructions */
- /* cache control instructions */
- /* spr/msr access instructions */
- PPC_INSNS_BASE = 0x0000000000000001ULL,
-#define PPC_INTEGER PPC_INSNS_BASE
-#define PPC_FLOW PPC_INSNS_BASE
-#define PPC_MEM PPC_INSNS_BASE
-#define PPC_RES PPC_INSNS_BASE
-#define PPC_CACHE PPC_INSNS_BASE
-#define PPC_MISC PPC_INSNS_BASE
- /* floating point operations instructions */
- PPC_FLOAT = 0x0000000000000002ULL,
- /* more floating point operations instructions */
- PPC_FLOAT_EXT = 0x0000000000000004ULL,
- /* external control instructions */
- PPC_EXTERN = 0x0000000000000008ULL,
- /* segment register access instructions */
- PPC_SEGMENT = 0x0000000000000010ULL,
- /* Optional cache control instructions */
- PPC_CACHE_OPT = 0x0000000000000020ULL,
- /* Optional floating point op instructions */
- PPC_FLOAT_OPT = 0x0000000000000040ULL,
- /* Optional memory control instructions */
- PPC_MEM_TLBIA = 0x0000000000000080ULL,
- PPC_MEM_TLBIE = 0x0000000000000100ULL,
- PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
- /* eieio & sync */
- PPC_MEM_SYNC = 0x0000000000000400ULL,
- /* PowerPC 6xx TLB management instructions */
- PPC_6xx_TLB = 0x0000000000000800ULL,
- /* Altivec support */
- PPC_ALTIVEC = 0x0000000000001000ULL,
- /* Time base support */
- PPC_TB = 0x0000000000002000ULL,
- /* Embedded PowerPC dedicated instructions */
- PPC_EMB_COMMON = 0x0000000000004000ULL,
- /* PowerPC 40x exception model */
- PPC_40x_EXCP = 0x0000000000008000ULL,
- /* PowerPC 40x specific instructions */
- PPC_40x_SPEC = 0x0000000000010000ULL,
- /* PowerPC 405 Mac instructions */
- PPC_405_MAC = 0x0000000000020000ULL,
- /* PowerPC 440 specific instructions */
- PPC_440_SPEC = 0x0000000000040000ULL,
- /* Specific extensions */
- /* Power-to-PowerPC bridge (601) */
- PPC_POWER_BR = 0x0000000000080000ULL,
- /* PowerPC 602 specific */
- PPC_602_SPEC = 0x0000000000100000ULL,
- /* Deprecated instructions */
- /* Original POWER instruction set */
- PPC_POWER = 0x0000000000200000ULL,
- /* POWER2 instruction set extension */
- PPC_POWER2 = 0x0000000000400000ULL,
- /* Power RTC support */
- PPC_POWER_RTC = 0x0000000000800000ULL,
- /* 64 bits PowerPC instructions */
- /* 64 bits PowerPC instruction set */
- PPC_64B = 0x0000000001000000ULL,
- /* 64 bits hypervisor extensions */
- PPC_64H = 0x0000000002000000ULL,
- /* 64 bits PowerPC "bridge" features */
- PPC_64_BRIDGE = 0x0000000004000000ULL,
- /* BookE (embedded) PowerPC specification */
- PPC_BOOKE = 0x0000000008000000ULL,
- /* eieio */
- PPC_MEM_EIEIO = 0x0000000010000000ULL,
- /* e500 vector instructions */
- PPC_E500_VECTOR = 0x0000000020000000ULL,
- /* PowerPC 4xx dedicated instructions */
- PPC_4xx_COMMON = 0x0000000040000000ULL,
- /* PowerPC 2.03 specification extensions */
- PPC_203 = 0x0000000080000000ULL,
- /* PowerPC 2.03 SPE extension */
- PPC_SPE = 0x0000000100000000ULL,
- /* PowerPC 2.03 SPE floating-point extension */
- PPC_SPEFPU = 0x0000000200000000ULL,
+ POWERPC_EXCP_UNKNOWN = 0,
+ /* Standard PowerPC exception model */
+ POWERPC_EXCP_STD,
+ /* PowerPC 40x exception model */
+ POWERPC_EXCP_40x,
+ /* PowerPC 601 exception model */
+ POWERPC_EXCP_601,
+ /* PowerPC 602 exception model */
+ POWERPC_EXCP_602,
+ /* PowerPC 603 exception model */
+ POWERPC_EXCP_603,
+ /* PowerPC 603e exception model */
+ POWERPC_EXCP_603E,
+ /* PowerPC G2 exception model */
+ POWERPC_EXCP_G2,
+ /* PowerPC 604 exception model */
+ POWERPC_EXCP_604,
+ /* PowerPC 7x0 exception model */
+ POWERPC_EXCP_7x0,
+ /* PowerPC 7x5 exception model */
+ POWERPC_EXCP_7x5,
+ /* PowerPC 74xx exception model */
+ POWERPC_EXCP_74xx,
+ /* PowerPC 970 exception model */
+ POWERPC_EXCP_970,
+ /* BookE exception model */
+ POWERPC_EXCP_BOOKE,
};
-/* CPU run-time flags (MMU and exception model) */
+/*****************************************************************************/
+/* Input pins model */
enum {
- /* MMU model */
- PPC_FLAGS_MMU_MASK = 0x0000000F,
- /* Standard 32 bits PowerPC MMU */
- PPC_FLAGS_MMU_32B = 0x00000000,
- /* Standard 64 bits PowerPC MMU */
- PPC_FLAGS_MMU_64B = 0x00000001,
- /* PowerPC 601 MMU */
- PPC_FLAGS_MMU_601 = 0x00000002,
- /* PowerPC 6xx MMU with software TLB */
- PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
- /* PowerPC 4xx MMU with software TLB */
- PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
- /* PowerPC 403 MMU */
- PPC_FLAGS_MMU_403 = 0x00000005,
- /* Freescale e500 MMU model */
- PPC_FLAGS_MMU_e500 = 0x00000006,
- /* BookE MMU model */
- PPC_FLAGS_MMU_BOOKE = 0x00000007,
- /* Exception model */
- PPC_FLAGS_EXCP_MASK = 0x000000F0,
- /* Standard PowerPC exception model */
- PPC_FLAGS_EXCP_STD = 0x00000000,
- /* PowerPC 40x exception model */
- PPC_FLAGS_EXCP_40x = 0x00000010,
- /* PowerPC 601 exception model */
- PPC_FLAGS_EXCP_601 = 0x00000020,
- /* PowerPC 602 exception model */
- PPC_FLAGS_EXCP_602 = 0x00000030,
- /* PowerPC 603 exception model */
- PPC_FLAGS_EXCP_603 = 0x00000040,
- /* PowerPC 604 exception model */
- PPC_FLAGS_EXCP_604 = 0x00000050,
- /* PowerPC 7x0 exception model */
- PPC_FLAGS_EXCP_7x0 = 0x00000060,
- /* PowerPC 7x5 exception model */
- PPC_FLAGS_EXCP_7x5 = 0x00000070,
- /* PowerPC 74xx exception model */
- PPC_FLAGS_EXCP_74xx = 0x00000080,
- /* PowerPC 970 exception model */
- PPC_FLAGS_EXCP_970 = 0x00000090,
- /* BookE exception model */
- PPC_FLAGS_EXCP_BOOKE = 0x000000A0,
+ PPC_FLAGS_INPUT_UNKNOWN = 0,
+ /* PowerPC 6xx bus */
+ PPC_FLAGS_INPUT_6xx,
+ /* BookE bus */
+ PPC_FLAGS_INPUT_BookE,
+ /* PowerPC 405 bus */
+ PPC_FLAGS_INPUT_405,
+ /* PowerPC 970 bus */
+ PPC_FLAGS_INPUT_970,
+ /* PowerPC 401 bus */
+ PPC_FLAGS_INPUT_401,
};
-#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
-#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
+#define PPC_INPUT(env) (env->bus_model)
-/*****************************************************************************/
-/* Supported instruction set definitions */
-/* This generates an empty opcode table... */
-#define PPC_INSNS_TODO (PPC_NONE)
-#define PPC_FLAGS_TODO (0x00000000)
-
-/* PowerPC 40x instruction set */
-#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
-/* PowerPC 401 */
-#define PPC_INSNS_401 (PPC_INSNS_TODO)
-#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
-/* PowerPC 403 */
-#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
- PPC_40x_SPEC)
-#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
-/* PowerPC 405 */
-#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
- PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
- PPC_405_MAC)
-#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
-/* PowerPC 440 */
-#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
- PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
-#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
-/* Generic BookE PowerPC */
-#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
- PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
-#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
-/* e500 core */
-#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
- PPC_CACHE_OPT | PPC_E500_VECTOR)
-#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
-/* Non-embedded PowerPC */
-#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
- PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
-/* PowerPC 601 */
-#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
-#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
-/* PowerPC 602 */
-#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
- PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
-#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
-/* PowerPC 603 */
-#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
- PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
-#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
-/* PowerPC G2 */
-#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
- PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
-#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
-/* PowerPC 604 */
-#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
- PPC_MEM_TLBSYNC | PPC_TB)
-#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
-/* PowerPC 740/750 (aka G3) */
-#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
- PPC_MEM_TLBSYNC | PPC_TB)
-#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
-/* PowerPC 745/755 */
-#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
- PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
-#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
-/* PowerPC 74xx (aka G4) */
-#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
- PPC_MEM_TLBSYNC | PPC_TB)
-#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
-
-/* Default PowerPC will be 604/970 */
-#define PPC_INSNS_PPC32 PPC_INSNS_604
-#define PPC_FLAGS_PPC32 PPC_FLAGS_604
-#if 0
-#define PPC_INSNS_PPC64 PPC_INSNS_970
-#define PPC_FLAGS_PPC64 PPC_FLAGS_970
-#endif
-#define PPC_INSNS_DEFAULT PPC_INSNS_604
-#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
typedef struct ppc_def_t ppc_def_t;
+typedef struct opc_handler_t opc_handler_t;
/*****************************************************************************/
/* Types used to describe some PowerPC registers */
typedef struct CPUPPCState CPUPPCState;
-typedef struct opc_handler_t opc_handler_t;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_spr_t ppc_spr_t;
typedef struct ppc_dcr_t ppc_dcr_t;
typedef struct ppc_avr_t ppc_avr_t;
-typedef struct ppc_tlb_t ppc_tlb_t;
+typedef union ppc_tlb_t ppc_tlb_t;
/* SPR access micro-ops generations callbacks */
struct ppc_spr_t {
};
/* Software TLB cache */
-struct ppc_tlb_t {
+typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
+struct ppc6xx_tlb_t {
target_ulong pte0;
target_ulong pte1;
target_ulong EPN;
+};
+
+typedef struct ppcemb_tlb_t ppcemb_tlb_t;
+struct ppcemb_tlb_t {
+ target_phys_addr_t RPN;
+ target_ulong EPN;
target_ulong PID;
- int size;
+ target_ulong size;
+ uint32_t prot;
+ uint32_t attr; /* Storage attributes */
+};
+
+union ppc_tlb_t {
+ ppc6xx_tlb_t tlb6;
+ ppcemb_tlb_t tlbe;
};
/*****************************************************************************/
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
#define MSR_HV 60 /* hypervisor state hflags */
-#define MSR_UCLE 26 /* User-mode cache lock enable on e500 */
+#define MSR_CM 31 /* Computation mode for BookE hflags */
+#define MSR_ICM 30 /* Interrupt computation mode for BookE */
+#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
#define MSR_VR 25 /* altivec available hflags */
-#define MSR_SPE 25 /* SPE enable on e500 hflags */
+#define MSR_SPE 25 /* SPE enable for BookE hflags */
#define MSR_AP 23 /* Access privilege state on 602 hflags */
#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
#define MSR_KEY 19 /* key bit on 603e */
#define msr_sf env->msr[MSR_SF]
#define msr_isf env->msr[MSR_ISF]
#define msr_hv env->msr[MSR_HV]
+#define msr_cm env->msr[MSR_CM]
+#define msr_icm env->msr[MSR_ICM]
#define msr_ucle env->msr[MSR_UCLE]
#define msr_vr env->msr[MSR_VR]
#define msr_spe env->msr[MSR_SPE]
#if TARGET_GPR_BITS > HOST_LONG_BITS
/* temporary fixed-point registers
* used to emulate 64 bits target on 32 bits hosts
- */
- target_ulong t0, t1, t2;
+ */
+ ppc_gpr_t t0, t1, t2;
#endif
ppc_avr_t t0_avr, t1_avr, t2_avr;
/* Time base and decrementer */
ppc_tb_t *tb_env;
/* Device control registers */
- int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
- int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
ppc_dcr_t *dcr_env;
/* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
int nb_ways; /* Number of ways in the TLB set */
int last_way; /* Last used way used to allocate TLB in a LRU way */
int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
+ int nb_pids; /* Number of available PID registers */
ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
- /* Callbacks for specific checks on some implementations */
- int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
- target_ulong vaddr, int rw, int acc_type,
- int is_user);
/* 403 dedicated access protection registers */
target_ulong pb[4];
/* Those resources are used during exception processing */
/* CPU model definition */
- uint64_t msr_mask;
+ target_ulong msr_mask;
+ uint8_t mmu_model;
+ uint8_t excp_model;
+ uint8_t bus_model;
+ uint8_t pad;
uint32_t flags;
int exception_index;
int error_code;
int interrupt_request;
+ uint32_t pending_interrupts;
+#if !defined(CONFIG_USER_ONLY)
+ /* This is the IRQ controller, which is implementation dependant
+ * and only relevant when emulating a complete machine.
+ */
+ uint32_t irq_input_state;
+ void **irq_inputs;
+#endif
/* Those resources are used only during code translation */
/* Next instruction pointer */
/* Those resources are used only in Qemu core */
jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
- uint32_t hflags;
+ target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
/* Power management */
int power_mode;
};
/*****************************************************************************/
-CPUPPCState *cpu_ppc_init(void);
-int cpu_ppc_exec(CPUPPCState *s);
-void cpu_ppc_close(CPUPPCState *s);
+CPUPPCState *cpu_ppc_init (void);
+int cpu_ppc_exec (CPUPPCState *s);
+void cpu_ppc_close (CPUPPCState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
-int cpu_ppc_signal_handler(int host_signum, void *pinfo,
- void *puc);
+int cpu_ppc_signal_handler (int host_signum, void *pinfo,
+ void *puc);
void do_interrupt (CPUPPCState *env);
-void cpu_loop_exit(void);
+void ppc_hw_interrupt (CPUPPCState *env);
+void cpu_loop_exit (void);
void dump_stack (CPUPPCState *env);
void ppc_store_xer (CPUPPCState *env, uint32_t value);
target_ulong do_load_msr (CPUPPCState *env);
void do_store_msr (CPUPPCState *env, target_ulong value);
-void ppc_store_msr32 (CPUPPCState *env, uint32_t value);
+void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
void do_compute_hflags (CPUPPCState *env);
+void cpu_ppc_reset (void *opaque);
+CPUPPCState *cpu_ppc_init (void);
+void cpu_ppc_close(CPUPPCState *env);
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
target_ulong load_40x_pit (CPUPPCState *env);
void store_40x_pit (CPUPPCState *env, target_ulong val);
+void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
+void store_40x_sler (CPUPPCState *env, uint32_t val);
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
+void ppc_tlb_invalidate_all (CPUPPCState *env);
+int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
#endif
#endif
-#define TARGET_PAGE_BITS 12
+/* Device control registers */
+int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
+int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
+
+#define CPUState CPUPPCState
+#define cpu_init cpu_ppc_init
+#define cpu_exec cpu_ppc_exec
+#define cpu_gen_code cpu_ppc_gen_code
+#define cpu_signal_handler cpu_ppc_signal_handler
+
#include "cpu-all.h"
/*****************************************************************************/
/* Registers definitions */
-#define ugpr(n) (env->gpr[n])
-
#define XER_SO 31
#define XER_OV 30
#define XER_CA 29
#define XER_CMP 8
-#define XER_BC 0
+#define XER_BC 0
#define xer_so env->xer[4]
#define xer_ov env->xer[6]
#define xer_ca env->xer[2]
#define xer_cmp env->xer[1]
-#define xer_bc env->xer[0]
+#define xer_bc env->xer[0]
/* SPR definitions */
#define SPR_MQ (0x000)
#define SPR_LR (0x008)
#define SPR_CTR (0x009)
#define SPR_DSISR (0x012)
-#define SPR_DAR (0x013)
+#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
#define SPR_601_RTCU (0x014)
#define SPR_601_RTCL (0x015)
#define SPR_DECR (0x016)
#define SPR_SDR1 (0x019)
#define SPR_SRR0 (0x01A)
#define SPR_SRR1 (0x01B)
+#define SPR_AMR (0x01D)
#define SPR_BOOKE_PID (0x030)
#define SPR_BOOKE_DECAR (0x036)
-#define SPR_CSRR0 (0x03A)
-#define SPR_CSRR1 (0x03B)
+#define SPR_BOOKE_CSRR0 (0x03A)
+#define SPR_BOOKE_CSRR1 (0x03B)
#define SPR_BOOKE_DEAR (0x03D)
#define SPR_BOOKE_ESR (0x03E)
-#define SPR_BOOKE_EVPR (0x03F)
+#define SPR_BOOKE_IVPR (0x03F)
#define SPR_8xx_EIE (0x050)
#define SPR_8xx_EID (0x051)
#define SPR_8xx_NRE (0x052)
+#define SPR_CTRL (0x088)
#define SPR_58x_CMPA (0x090)
#define SPR_58x_CMPB (0x091)
#define SPR_58x_CMPC (0x092)
#define SPR_58x_DER (0x094)
#define SPR_58x_COUNTA (0x096)
#define SPR_58x_COUNTB (0x097)
+#define SPR_UCTRL (0x098)
#define SPR_58x_CMPE (0x098)
#define SPR_58x_CMPF (0x099)
#define SPR_58x_CMPG (0x09A)
#define SPR_58x_BAR (0x09F)
#define SPR_VRSAVE (0x100)
#define SPR_USPRG0 (0x100)
+#define SPR_USPRG1 (0x101)
+#define SPR_USPRG2 (0x102)
+#define SPR_USPRG3 (0x103)
#define SPR_USPRG4 (0x104)
#define SPR_USPRG5 (0x105)
#define SPR_USPRG6 (0x106)
#define SPR_EAR (0x11A)
#define SPR_TBL (0x11C)
#define SPR_TBU (0x11D)
+#define SPR_TBU40 (0x11E)
#define SPR_SVR (0x11E)
#define SPR_BOOKE_PIR (0x11E)
#define SPR_PVR (0x11F)
#define SPR_HSPRG0 (0x130)
#define SPR_BOOKE_DBSR (0x130)
#define SPR_HSPRG1 (0x131)
+#define SPR_HDSISR (0x132)
+#define SPR_HDAR (0x133)
#define SPR_BOOKE_DBCR0 (0x134)
#define SPR_IBCR (0x135)
+#define SPR_PURR (0x135)
#define SPR_BOOKE_DBCR1 (0x135)
#define SPR_DBCR (0x136)
#define SPR_HDEC (0x136)
#define SPR_BOOKE_IVOR13 (0x19D)
#define SPR_BOOKE_IVOR14 (0x19E)
#define SPR_BOOKE_IVOR15 (0x19F)
-#define SPR_E500_SPEFSCR (0x200)
+#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_E500_BBEAR (0x201)
#define SPR_E500_BBTAR (0x202)
#define SPR_BOOKE_ATBL (0x20E)
#define SPR_BOOKE_ATBU (0x20F)
#define SPR_IBAT0U (0x210)
-#define SPR_E500_IVOR32 (0x210)
+#define SPR_BOOKE_IVOR32 (0x210)
#define SPR_IBAT0L (0x211)
-#define SPR_E500_IVOR33 (0x211)
+#define SPR_BOOKE_IVOR33 (0x211)
#define SPR_IBAT1U (0x212)
-#define SPR_E500_IVOR34 (0x212)
+#define SPR_BOOKE_IVOR34 (0x212)
#define SPR_IBAT1L (0x213)
-#define SPR_E500_IVOR35 (0x213)
+#define SPR_BOOKE_IVOR35 (0x213)
#define SPR_IBAT2U (0x214)
+#define SPR_BOOKE_IVOR36 (0x214)
#define SPR_IBAT2L (0x215)
#define SPR_E500_L1CFG0 (0x215)
+#define SPR_BOOKE_IVOR37 (0x215)
#define SPR_IBAT3U (0x216)
#define SPR_E500_L1CFG1 (0x216)
#define SPR_IBAT3L (0x217)
#define SPR_DBAT4U (0x238)
#define SPR_DBAT4L (0x239)
#define SPR_DBAT5U (0x23A)
-#define SPR_E500_MCSRR0 (0x23A)
+#define SPR_BOOKE_MCSRR0 (0x23A)
#define SPR_DBAT5L (0x23B)
-#define SPR_E500_MCSRR1 (0x23B)
+#define SPR_BOOKE_MCSRR1 (0x23B)
#define SPR_DBAT6U (0x23C)
-#define SPR_E500_MCSR (0x23C)
+#define SPR_BOOKE_MCSR (0x23C)
#define SPR_DBAT6L (0x23D)
#define SPR_E500_MCAR (0x23D)
#define SPR_DBAT7U (0x23E)
+#define SPR_BOOKE_DSRR0 (0x23E)
#define SPR_DBAT7L (0x23F)
-#define SPR_E500_MAS0 (0x270)
-#define SPR_E500_MAS1 (0x271)
-#define SPR_E500_MAS2 (0x272)
-#define SPR_E500_MAS3 (0x273)
-#define SPR_E500_MAS4 (0x274)
-#define SPR_E500_MAS6 (0x276)
-#define SPR_E500_PID1 (0x279)
-#define SPR_E500_PID2 (0x27A)
-#define SPR_E500_TLB0CFG (0x2B0)
-#define SPR_E500_TLB1CFG (0x2B1)
+#define SPR_BOOKE_DSRR1 (0x23F)
+#define SPR_BOOKE_SPRG8 (0x25C)
+#define SPR_BOOKE_SPRG9 (0x25D)
+#define SPR_BOOKE_MAS0 (0x270)
+#define SPR_BOOKE_MAS1 (0x271)
+#define SPR_BOOKE_MAS2 (0x272)
+#define SPR_BOOKE_MAS3 (0x273)
+#define SPR_BOOKE_MAS4 (0x274)
+#define SPR_BOOKE_MAS6 (0x276)
+#define SPR_BOOKE_PID1 (0x279)
+#define SPR_BOOKE_PID2 (0x27A)
+#define SPR_BOOKE_TLB0CFG (0x2B0)
+#define SPR_BOOKE_TLB1CFG (0x2B1)
+#define SPR_BOOKE_TLB2CFG (0x2B2)
+#define SPR_BOOKE_TLB3CFG (0x2B3)
+#define SPR_BOOKE_EPR (0x2BE)
+#define SPR_PERF0 (0x300)
+#define SPR_PERF1 (0x301)
+#define SPR_PERF2 (0x302)
+#define SPR_PERF3 (0x303)
+#define SPR_PERF4 (0x304)
+#define SPR_PERF5 (0x305)
+#define SPR_PERF6 (0x306)
+#define SPR_PERF7 (0x307)
+#define SPR_PERF8 (0x308)
+#define SPR_PERF9 (0x309)
+#define SPR_PERFA (0x30A)
+#define SPR_PERFB (0x30B)
+#define SPR_PERFC (0x30C)
+#define SPR_PERFD (0x30D)
+#define SPR_PERFE (0x30E)
+#define SPR_PERFF (0x30F)
+#define SPR_UPERF0 (0x310)
+#define SPR_UPERF1 (0x311)
+#define SPR_UPERF2 (0x312)
+#define SPR_UPERF3 (0x313)
+#define SPR_UPERF4 (0x314)
+#define SPR_UPERF5 (0x315)
+#define SPR_UPERF6 (0x316)
+#define SPR_UPERF7 (0x317)
+#define SPR_UPERF8 (0x318)
+#define SPR_UPERF9 (0x319)
+#define SPR_UPERFA (0x31A)
+#define SPR_UPERFB (0x31B)
+#define SPR_UPERFC (0x31C)
+#define SPR_UPERFD (0x31D)
+#define SPR_UPERFE (0x31E)
+#define SPR_UPERFF (0x31F)
#define SPR_440_INV0 (0x370)
#define SPR_440_INV1 (0x371)
#define SPR_440_INV2 (0x372)
#define SPR_440_INV3 (0x373)
-#define SPR_440_IVT0 (0x374)
-#define SPR_440_IVT1 (0x375)
-#define SPR_440_IVT2 (0x376)
-#define SPR_440_IVT3 (0x377)
+#define SPR_440_ITV0 (0x374)
+#define SPR_440_ITV1 (0x375)
+#define SPR_440_ITV2 (0x376)
+#define SPR_440_ITV3 (0x377)
+#define SPR_440_CCR1 (0x378)
+#define SPR_DCRIPR (0x37B)
+#define SPR_PPR (0x380)
#define SPR_440_DNV0 (0x390)
#define SPR_440_DNV1 (0x391)
#define SPR_440_DNV2 (0x392)
#define SPR_440_DNV3 (0x393)
-#define SPR_440_DVT0 (0x394)
-#define SPR_440_DVT1 (0x395)
-#define SPR_440_DVT2 (0x396)
-#define SPR_440_DVT3 (0x397)
+#define SPR_440_DTV0 (0x394)
+#define SPR_440_DTV1 (0x395)
+#define SPR_440_DTV2 (0x396)
+#define SPR_440_DTV3 (0x397)
#define SPR_440_DVLIM (0x398)
#define SPR_440_IVLIM (0x399)
#define SPR_440_RSTCFG (0x39B)
-#define SPR_440_DCBTRL (0x39C)
-#define SPR_440_DCBTRH (0x39D)
-#define SPR_440_ICBTRL (0x39E)
-#define SPR_440_ICBTRH (0x39F)
+#define SPR_BOOKE_DCDBTRL (0x39C)
+#define SPR_BOOKE_DCDBTRH (0x39D)
+#define SPR_BOOKE_ICDBTRL (0x39E)
+#define SPR_BOOKE_ICDBTRH (0x39F)
+#define SPR_UMMCR2 (0x3A0)
+#define SPR_UPMC5 (0x3A1)
+#define SPR_UPMC6 (0x3A2)
+#define SPR_UBAMR (0x3A7)
#define SPR_UMMCR0 (0x3A8)
#define SPR_UPMC1 (0x3A9)
#define SPR_UPMC2 (0x3AA)
-#define SPR_USIA (0x3AB)
+#define SPR_USIAR (0x3AB)
#define SPR_UMMCR1 (0x3AC)
#define SPR_UPMC3 (0x3AD)
#define SPR_UPMC4 (0x3AE)
#define SPR_USDA (0x3AF)
#define SPR_40x_ZPR (0x3B0)
-#define SPR_E500_MAS7 (0x3B0)
+#define SPR_BOOKE_MAS7 (0x3B0)
+#define SPR_620_PMR0 (0x3B0)
+#define SPR_MMCR2 (0x3B0)
+#define SPR_PMC5 (0x3B1)
#define SPR_40x_PID (0x3B1)
+#define SPR_620_PMR1 (0x3B1)
+#define SPR_PMC6 (0x3B2)
#define SPR_440_MMUCR (0x3B2)
+#define SPR_620_PMR2 (0x3B2)
#define SPR_4xx_CCR0 (0x3B3)
+#define SPR_BOOKE_EPLC (0x3B3)
+#define SPR_620_PMR3 (0x3B3)
#define SPR_405_IAC3 (0x3B4)
+#define SPR_BOOKE_EPSC (0x3B4)
+#define SPR_620_PMR4 (0x3B4)
#define SPR_405_IAC4 (0x3B5)
+#define SPR_620_PMR5 (0x3B5)
#define SPR_405_DVC1 (0x3B6)
+#define SPR_620_PMR6 (0x3B6)
#define SPR_405_DVC2 (0x3B7)
+#define SPR_620_PMR7 (0x3B7)
+#define SPR_BAMR (0x3B7)
#define SPR_MMCR0 (0x3B8)
+#define SPR_620_PMR8 (0x3B8)
#define SPR_PMC1 (0x3B9)
#define SPR_40x_SGR (0x3B9)
+#define SPR_620_PMR9 (0x3B9)
#define SPR_PMC2 (0x3BA)
#define SPR_40x_DCWR (0x3BA)
-#define SPR_SIA (0x3BB)
+#define SPR_620_PMRA (0x3BA)
+#define SPR_SIAR (0x3BB)
#define SPR_405_SLER (0x3BB)
+#define SPR_620_PMRB (0x3BB)
#define SPR_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
+#define SPR_620_PMRC (0x3BC)
+#define SPR_401_SKR (0x3BC)
#define SPR_PMC3 (0x3BD)
#define SPR_405_DBCR1 (0x3BD)
+#define SPR_620_PMRD (0x3BD)
#define SPR_PMC4 (0x3BE)
+#define SPR_620_PMRE (0x3BE)
#define SPR_SDA (0x3BF)
+#define SPR_620_PMRF (0x3BF)
#define SPR_403_VTBL (0x3CC)
#define SPR_403_VTBU (0x3CD)
#define SPR_DMISS (0x3D0)
#define SPR_DCMP (0x3D1)
#define SPR_HASH1 (0x3D2)
#define SPR_HASH2 (0x3D3)
-#define SPR_4xx_ICDBDR (0x3D3)
+#define SPR_BOOKE_ICDBDR (0x3D3)
+#define SPR_TLBMISS (0x3D4)
#define SPR_IMISS (0x3D4)
#define SPR_40x_ESR (0x3D4)
+#define SPR_PTEHI (0x3D5)
#define SPR_ICMP (0x3D5)
#define SPR_40x_DEAR (0x3D5)
+#define SPR_PTELO (0x3D6)
#define SPR_RPA (0x3D6)
#define SPR_40x_EVPR (0x3D6)
+#define SPR_L3PM (0x3D7)
#define SPR_403_CDBCR (0x3D7)
+#define SPR_L3OHCR (0x3D8)
#define SPR_TCR (0x3D8)
#define SPR_40x_TSR (0x3D8)
#define SPR_IBR (0x3DA)
#define SPR_40x_TCR (0x3DA)
-#define SPR_ESASR (0x3DB)
+#define SPR_ESASRR (0x3DB)
#define SPR_40x_PIT (0x3DB)
#define SPR_403_TBL (0x3DC)
#define SPR_403_TBU (0x3DD)
#define SPR_40x_SRR2 (0x3DE)
#define SPR_SER (0x3DF)
#define SPR_40x_SRR3 (0x3DF)
+#define SPR_L3ITCR0 (0x3E8)
+#define SPR_L3ITCR1 (0x3E9)
+#define SPR_L3ITCR2 (0x3EA)
+#define SPR_L3ITCR3 (0x3EB)
#define SPR_HID0 (0x3F0)
#define SPR_40x_DBSR (0x3F0)
#define SPR_HID1 (0x3F1)
#define SPR_40x_DBCR0 (0x3F2)
#define SPR_601_HID2 (0x3F2)
#define SPR_E500_L1CSR0 (0x3F2)
+#define SPR_ICTRL (0x3F3)
#define SPR_HID2 (0x3F3)
#define SPR_E500_L1CSR1 (0x3F3)
#define SPR_440_DBDR (0x3F3)
+#define SPR_LDSTDB (0x3F4)
#define SPR_40x_IAC1 (0x3F4)
-#define SPR_E500_MMUCSR0 (0x3F4)
+#define SPR_BOOKE_MMUCSR0 (0x3F4)
#define SPR_DABR (0x3F5)
#define DABR_MASK (~(target_ulong)0x7)
#define SPR_E500_BUCSR (0x3F5)
#define SPR_40x_IAC2 (0x3F5)
#define SPR_601_HID5 (0x3F5)
#define SPR_40x_DAC1 (0x3F6)
+#define SPR_MSSCR0 (0x3F6)
+#define SPR_MSSSR0 (0x3F7)
+#define SPR_DABRX (0x3F7)
#define SPR_40x_DAC2 (0x3F7)
-#define SPR_E500_MMUCFG (0x3F7)
-#define SPR_L2PM (0x3F8)
+#define SPR_BOOKE_MMUCFG (0x3F7)
+#define SPR_LDSTCR (0x3F8)
+#define SPR_L2PMCR (0x3F8)
#define SPR_750_HID2 (0x3F8)
+#define SPR_620_HID8 (0x3F8)
#define SPR_L2CR (0x3F9)
+#define SPR_620_HID9 (0x3F9)
+#define SPR_L3CR (0x3FA)
#define SPR_IABR2 (0x3FA)
#define SPR_40x_DCCR (0x3FA)
#define SPR_ICTC (0x3FB)
#define SPR_SP (0x3FD)
#define SPR_THRM2 (0x3FD)
#define SPR_403_PBU1 (0x3FD)
+#define SPR_604_HID13 (0x3FD)
#define SPR_LT (0x3FE)
#define SPR_THRM3 (0x3FE)
#define SPR_FPECR (0x3FE)
#define SPR_PIR (0x3FF)
#define SPR_403_PBU2 (0x3FF)
#define SPR_601_HID15 (0x3FF)
+#define SPR_604_HID15 (0x3FF)
#define SPR_E500_SVR (0x3FF)
/*****************************************************************************/
#define EXCP_40x_DEBUG 0x2000 /* Debug exception */
/* 405 specific exceptions */
#define EXCP_405_APU 0x0F20 /* APU unavailable exception */
+/* 440 specific exceptions */
+#define EXCP_440_CRIT 0x0100 /* Critical interrupt */
+#define EXCP_440_SPEU 0x1600 /* SPE unavailable exception */
+#define EXCP_440_SPED 0x1700 /* SPE floating-point data exception */
+#define EXCP_440_SPER 0x1800 /* SPE floating-point round exception */
/* TLB assist exceptions (602/603) */
#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
/* Altivec related exceptions */
#define EXCP_VPU 0x0F20 /* VPU unavailable exception */
/* 601 specific exceptions */
-#define EXCP_601_IO 0x0600 /* IO error exception */
+#define EXCP_601_IO 0x0A00 /* IO error exception */
#define EXCP_601_RUNM 0x2000 /* Run mode exception */
/* 602 specific exceptions */
#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
/* may change privilege level */
#define EXCP_BRANCH 0x11001 /* branch instruction */
#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
-#define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */
/* Error codes */
enum {
EXCP_FP_ZX = 0x03, /* FP divide by zero */
EXCP_FP_XX = 0x04, /* FP inexact */
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
- EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
+ EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
/* Privileged instruction */
EXCP_PRIV = 0x30,
- EXCP_PRIV_OPC = 0x01,
- EXCP_PRIV_REG = 0x02,
+ EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
+ EXCP_PRIV_REG = 0x02, /* Privileged register exception */
/* Trap */
EXCP_TRAP = 0x40,
};
+/* Hardware interruption sources:
+ * all those exception can be raised simulteaneously
+ */
+/* Input pins definitions */
+enum {
+ /* 6xx bus input pins */
+ PPC6xx_INPUT_HRESET = 0,
+ PPC6xx_INPUT_SRESET = 1,
+ PPC6xx_INPUT_CKSTP_IN = 2,
+ PPC6xx_INPUT_MCP = 3,
+ PPC6xx_INPUT_SMI = 4,
+ PPC6xx_INPUT_INT = 5,
+};
+
+enum {
+ /* Embedded PowerPC input pins */
+ PPCBookE_INPUT_HRESET = 0,
+ PPCBookE_INPUT_SRESET = 1,
+ PPCBookE_INPUT_CKSTP_IN = 2,
+ PPCBookE_INPUT_MCP = 3,
+ PPCBookE_INPUT_SMI = 4,
+ PPCBookE_INPUT_INT = 5,
+ PPCBookE_INPUT_CINT = 6,
+};
+
+enum {
+ /* PowerPC 401/403 input pins */
+ PPC401_INPUT_RESET = 0,
+ PPC401_INPUT_CINT = 1,
+ PPC401_INPUT_INT = 2,
+ PPC401_INPUT_BERR = 3,
+ PPC401_INPUT_HALT = 4,
+};
+
+enum {
+ /* PowerPC 405 input pins */
+ PPC405_INPUT_RESET_CORE = 0,
+ PPC405_INPUT_RESET_CHIP = 1,
+ PPC405_INPUT_RESET_SYS = 2,
+ PPC405_INPUT_CINT = 3,
+ PPC405_INPUT_INT = 4,
+ PPC405_INPUT_HALT = 5,
+ PPC405_INPUT_DEBUG = 6,
+};
+
+enum {
+ /* PowerPC 620 (and probably others) input pins */
+ PPC620_INPUT_HRESET = 0,
+ PPC620_INPUT_SRESET = 1,
+ PPC620_INPUT_CKSTP = 2,
+ PPC620_INPUT_TBEN = 3,
+ PPC620_INPUT_WAKEUP = 4,
+ PPC620_INPUT_MCP = 5,
+ PPC620_INPUT_SMI = 6,
+ PPC620_INPUT_INT = 7,
+};
+
+enum {
+ /* PowerPC 970 input pins */
+ PPC970_INPUT_HRESET = 0,
+ PPC970_INPUT_SRESET = 1,
+ PPC970_INPUT_CKSTP = 2,
+ PPC970_INPUT_TBEN = 3,
+ PPC970_INPUT_MCP = 4,
+ PPC970_INPUT_INT = 5,
+ PPC970_INPUT_THINT = 6,
+};
+
+/* Hardware exceptions definitions */
+enum {
+ /* External hardware exception sources */
+ PPC_INTERRUPT_RESET = 0, /* Reset exception */
+ PPC_INTERRUPT_MCK = 1, /* Machine check exception */
+ PPC_INTERRUPT_EXT = 2, /* External interrupt */
+ PPC_INTERRUPT_SMI = 3, /* System management interrupt */
+ PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
+ PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
+ PPC_INTERRUPT_THERM = 6, /* Thermal exception */
+ /* Internal hardware exception sources */
+ PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
+ PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
+ PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
+ PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
+ PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
+};
+
/*****************************************************************************/
+static inline target_ulong get_sp_from_cpustate(CPUPPCState *state)
+{
+ return state->gpr[1];
+}
+
#endif /* !defined (__CPU_PPC_H__) */
projects / qemu.git / blobdiff