ppc4xx: correct SDRAM controller warning message condition

[qemu.git] / hw / ppc_mac.h

diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h
index 74d19a199182260f585b79e2d7a5ddf4e905a353..89f96bbc347b32491d4d64ad8a26d3bf03638724 100644 (file)
--- a/hw/ppc_mac.h
+++ b/hw/ppc_mac.h
@@ -28,6 +28,7 @@
 /* SMP is not enabled, for now */
 #define MAX_CPUS 1
 
+#define BIOS_SIZE     (1024 * 1024)
 #define BIOS_FILENAME "ppc_rom.bin"
 #define VGABIOS_FILENAME "video.x"
 #define NVRAM_SIZE        0x2000
@@ -35,8 +36,8 @@
 #define PROM_ADDR         0xfff00000
 
 #define KERNEL_LOAD_ADDR 0x01000000
-#define CMDLINE_ADDR     0x017ff000
-#define INITRD_LOAD_ADDR 0x01800000
+#define CMDLINE_ADDR     0x027ff000
+#define INITRD_LOAD_ADDR 0x02800000
 
 #define ESCC_CLOCK 3686400
 
@@ -48,10 +49,6 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
                  int dbdma_mem_index, int cuda_mem_index, void *nvram,
                  int nb_ide, int *ide_mem_index, int escc_mem_index);
 
-/* NewWorld PowerMac IDE */
-int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
-                   void *dbdma, int channel, qemu_irq dma_irq);
-
 /* Heathrow PIC */
 qemu_irq *heathrow_pic_init(int *pmem_index,
                             int nb_cpus, qemu_irq **irqs);
@@ -61,6 +58,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
 
 /* UniNorth PCI */
 PCIBus *pci_pmac_init(qemu_irq *pic);
+PCIBus *pci_pmac_u3_init(qemu_irq *pic);
 
 /* Mac NVRAM */
 typedef struct MacIONVRAMState MacIONVRAMState;