target-arm: Raw CPSR writes should skip checks and bank switching

[qemu.git] / target-arm / op_helper.c

diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 543d33aad2db733a9c04050dfbcecc45f994a21c..4881e341778e397c66c735b4b563d2395713ab24 100644 (file)
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -779,7 +779,10 @@ void HELPER(exception_return)(CPUARMState *env)
 
     if (!return_to_aa64) {
         env->aarch64 = 0;
-        env->uncached_cpsr = spsr & CPSR_M;
+        /* We do a raw CPSR write because aarch64_sync_64_to_32()
+         * will sort the register banks out for us, and we've already
+         * caught all the bad-mode cases in el_from_spsr().
+         */
         cpsr_write(env, spsr, ~0, CPSRWriteRaw);
         if (!arm_singlestep_active(env)) {
             env->uncached_cpsr &= ~PSTATE_SS;