#ifndef TCG_TARGET_IA64
#define TCG_TARGET_IA64 1
+#define TCG_TARGET_INSN_UNIT_SIZE 16
+typedef struct {
+ uint64_t lo __attribute__((aligned(16)));
+ uint64_t hi;
+} tcg_insn_unit;
+
/* We only map the first 64 registers */
#define TCG_TARGET_NB_REGS 64
typedef enum {
TCG_REG_R61,
TCG_REG_R62,
TCG_REG_R63,
+
+ TCG_AREG0 = TCG_REG_R32,
} TCGReg;
#define TCG_CT_CONST_ZERO 0x100
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 0
+#define TCG_TARGET_HAS_rem_i32 0
#define TCG_TARGET_HAS_div_i64 0
+#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muluh_i32 0
+#define TCG_TARGET_HAS_muluh_i64 0
+#define TCG_TARGET_HAS_mulsh_i32 0
+#define TCG_TARGET_HAS_mulsh_i64 0
+#define TCG_TARGET_HAS_trunc_shr_i32 0
+
+#define TCG_TARGET_HAS_new_ldst 1
#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)
#define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */
#define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */
-#define TCG_AREG0 TCG_REG_R7
-
-static inline void flush_icache_range(tcg_target_ulong start,
- tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
start = start & ~(32UL - 1UL);
stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);