*/
#include "sysbus.h"
-#include "qemu-char.h"
-#include "qemu-log.h"
-#include "net.h"
+#include "char/char.h"
+#include "qemu/log.h"
+#include "net/net.h"
#include "net/checksum.h"
#ifdef DEBUG_XGMAC
frame_size += len;
if (bd.ctl_stat & 0x20000000) {
/* Last buffer in frame. */
- qemu_send_packet(&s->nic->nc, frame, len);
+ qemu_send_packet(qemu_get_queue(s->nic), frame, len);
ptr = frame;
frame_size = 0;
s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
qemu_set_irq(s->sbd_irq, !!stat);
}
-static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
{
struct XgmacState *s = opaque;
uint64_t r = 0;
return r;
}
-static void enet_write(void *opaque, target_phys_addr_t addr,
+static void enet_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XgmacState *s = opaque;
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static int eth_can_rx(VLANClientState *nc)
+static int eth_can_rx(NetClientState *nc)
{
- struct XgmacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
+ struct XgmacState *s = qemu_get_nic_opaque(nc);
/* RX enabled? */
return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
}
-static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
+static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
{
- struct XgmacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
+ struct XgmacState *s = qemu_get_nic_opaque(nc);
static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
0xff, 0xff, 0xff};
int unicast, broadcast, multicast;
return ret;
}
-static void eth_cleanup(VLANClientState *nc)
+static void eth_cleanup(NetClientState *nc)
{
- struct XgmacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
+ struct XgmacState *s = qemu_get_nic_opaque(nc);
s->nic = NULL;
}
static NetClientInfo net_xgmac_enet_info = {
- .type = NET_CLIENT_TYPE_NIC,
+ .type = NET_CLIENT_OPTIONS_KIND_NIC,
.size = sizeof(NICState),
.can_receive = eth_can_rx,
.receive = eth_rx,
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
- dev->qdev.info->name, dev->qdev.id, s);
- qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
+ object_get_typename(OBJECT(dev)), dev->qdev.id, s);
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
s->conf.macaddr.a[4];
return 0;
}
-static SysBusDeviceInfo xgmac_enet_info = {
- .init = xgmac_enet_init,
- .qdev.name = "xgmac",
- .qdev.size = sizeof(struct XgmacState),
- .qdev.vmsd = &vmstate_xgmac,
- .qdev.props = (Property[]) {
- DEFINE_NIC_PROPERTIES(struct XgmacState, conf),
- DEFINE_PROP_END_OF_LIST(),
- }
+static Property xgmac_properties[] = {
+ DEFINE_NIC_PROPERTIES(struct XgmacState, conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xgmac_enet_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ sbc->init = xgmac_enet_init;
+ dc->vmsd = &vmstate_xgmac;
+ dc->props = xgmac_properties;
+}
+
+static const TypeInfo xgmac_enet_info = {
+ .name = "xgmac",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct XgmacState),
+ .class_init = xgmac_enet_class_init,
};
-static void xgmac_enet_register(void)
+
+static void xgmac_enet_register_types(void)
{
- sysbus_register_withprop(&xgmac_enet_info);
+ type_register_static(&xgmac_enet_info);
}
-device_init(xgmac_enet_register)
+type_init(xgmac_enet_register_types)