#include "qapi/error.h"
#include "qapi/qmp/qnum.h"
#include "acpi-build.h"
+#include "acpi-common.h"
#include "qemu/bitmap.h"
#include "qemu/error-report.h"
#include "hw/pci/pci.h"
#include "sysemu/tpm.h"
#include "hw/acpi/tpm.h"
#include "hw/acpi/vmgenid.h"
-#include "hw/boards.h"
#include "sysemu/tpm_backend.h"
#include "hw/rtc/mc146818rtc_regs.h"
#include "migration/vmstate.h"
#include "hw/mem/nvdimm.h"
#include "sysemu/numa.h"
#include "sysemu/reset.h"
+#include "hw/hyperv/vmbus-bridge.h"
/* Supported chipsets: */
#include "hw/southbridge/piix.h"
#define ACPI_BUILD_DPRINTF(fmt, ...)
#endif
-/* Default IOAPIC ID */
-#define ACPI_BUILD_IOAPIC_ID 0x0
-
typedef struct AcpiPmInfo {
bool s3_disabled;
bool s4_disabled;
bool pcihp_bridge_en;
+ bool smi_on_cpuhp;
+ bool smi_on_cpu_unplug;
+ bool pcihp_root_en;
uint8_t s4_val;
AcpiFadtData fadt;
uint16_t cpu_hp_io_base;
static void init_common_fadt_data(MachineState *ms, Object *o,
AcpiFadtData *data)
{
+ X86MachineState *x86ms = X86_MACHINE(ms);
+ /*
+ * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
+ * behavior for compatibility irrelevant to smm_enabled, which doesn't
+ * comforms to ACPI spec.
+ */
+ bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
+ true : x86_machine_is_smm_enabled(x86ms);
uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
AmlAddressSpace as = AML_AS_SYSTEM_IO;
AcpiFadtData fadt = {
.rtc_century = RTC_CENTURY,
.plvl2_lat = 0xfff /* C2 state not supported */,
.plvl3_lat = 0xfff /* C3 state not supported */,
- .smi_cmd = ACPI_PORT_SMI_CMD,
+ .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
.sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
.acpi_enable_cmd =
- object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
+ smm_enabled ?
+ object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
+ 0,
.acpi_disable_cmd =
- object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
+ smm_enabled ?
+ object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
+ 0,
.pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
.pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
.address = io + 0x04 },
pm->cpu_hp_io_base = 0;
pm->pcihp_io_base = 0;
pm->pcihp_io_len = 0;
+ pm->smi_on_cpuhp = false;
+ pm->smi_on_cpu_unplug = false;
assert(obj);
init_common_fadt_data(machine, obj, &pm->fadt);
object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
}
if (lpc) {
+ uint64_t smi_features = object_property_get_uint(lpc,
+ ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
.bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
pm->fadt.reset_reg = r;
pm->fadt.reset_val = 0xf;
pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
+ pm->smi_on_cpuhp =
+ !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
+ pm->smi_on_cpu_unplug =
+ !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
}
/* The above need not be conditional on machine type because the reset port
pm->pcihp_bridge_en =
object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
NULL);
+ pm->pcihp_root_en =
+ object_property_get_bool(obj, "acpi-root-pci-hotplug",
+ NULL);
}
static void acpi_get_misc_info(AcpiMiscInfo *info)
facs->length = cpu_to_le32(sizeof(*facs));
}
-void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
- const CPUArchIdList *apic_ids, GArray *entry)
-{
- uint32_t apic_id = apic_ids->cpus[uid].arch_id;
-
- /* ACPI spec says that LAPIC entry for non present
- * CPU may be omitted from MADT or it must be marked
- * as disabled. However omitting non present CPU from
- * MADT breaks hotplug on linux. So possible CPUs
- * should be put in MADT but kept disabled.
- */
- if (apic_id < 255) {
- AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
-
- apic->type = ACPI_APIC_PROCESSOR;
- apic->length = sizeof(*apic);
- apic->processor_id = uid;
- apic->local_apic_id = apic_id;
- if (apic_ids->cpus[uid].cpu != NULL) {
- apic->flags = cpu_to_le32(1);
- } else {
- apic->flags = cpu_to_le32(0);
- }
- } else {
- AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
-
- apic->type = ACPI_APIC_LOCAL_X2APIC;
- apic->length = sizeof(*apic);
- apic->uid = cpu_to_le32(uid);
- apic->x2apic_id = cpu_to_le32(apic_id);
- if (apic_ids->cpus[uid].cpu != NULL) {
- apic->flags = cpu_to_le32(1);
- } else {
- apic->flags = cpu_to_le32(0);
- }
- }
-}
-
-static void
-build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
-{
- MachineClass *mc = MACHINE_GET_CLASS(pcms);
- X86MachineState *x86ms = X86_MACHINE(pcms);
- const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
- int madt_start = table_data->len;
- AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
- AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
- bool x2apic_mode = false;
-
- AcpiMultipleApicTable *madt;
- AcpiMadtIoApic *io_apic;
- AcpiMadtIntsrcovr *intsrcovr;
- int i;
-
- madt = acpi_data_push(table_data, sizeof *madt);
- madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
- madt->flags = cpu_to_le32(1);
-
- for (i = 0; i < apic_ids->len; i++) {
- adevc->madt_cpu(adev, i, apic_ids, table_data);
- if (apic_ids->cpus[i].arch_id > 254) {
- x2apic_mode = true;
- }
- }
-
- io_apic = acpi_data_push(table_data, sizeof *io_apic);
- io_apic->type = ACPI_APIC_IO;
- io_apic->length = sizeof(*io_apic);
- io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
- io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
- io_apic->interrupt = cpu_to_le32(0);
-
- if (x86ms->apic_xrupt_override) {
- intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
- intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
- intsrcovr->length = sizeof(*intsrcovr);
- intsrcovr->source = 0;
- intsrcovr->gsi = cpu_to_le32(2);
- intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
- }
- for (i = 1; i < 16; i++) {
-#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
- if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
- /* No need for a INT source override structure. */
- continue;
- }
- intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
- intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
- intsrcovr->length = sizeof(*intsrcovr);
- intsrcovr->source = i;
- intsrcovr->gsi = cpu_to_le32(i);
- intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
- }
-
- if (x2apic_mode) {
- AcpiMadtLocalX2ApicNmi *local_nmi;
-
- local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
- local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
- local_nmi->length = sizeof(*local_nmi);
- local_nmi->uid = 0xFFFFFFFF; /* all processors */
- local_nmi->flags = cpu_to_le16(0);
- local_nmi->lint = 1; /* ACPI_LINT1 */
- } else {
- AcpiMadtLocalNmi *local_nmi;
-
- local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
- local_nmi->type = ACPI_APIC_LOCAL_NMI;
- local_nmi->length = sizeof(*local_nmi);
- local_nmi->processor_id = 0xff; /* all processors */
- local_nmi->flags = cpu_to_le16(0);
- local_nmi->lint = 1; /* ACPI_LINT1 */
- }
-
- build_header(linker, table_data,
- (void *)(table_data->data + madt_start), "APIC",
- table_data->len - madt_start, 1, NULL, NULL);
-}
-
static void build_append_pcihp_notify_entry(Aml *method, int slot)
{
Aml *if_ctx;
int slot = PCI_SLOT(i);
bool hotplug_enabled_dev;
bool bridge_in_acpi;
+ bool cold_plugged_bridge;
if (!pdev) {
if (bsel) { /* add hotplug slots for non present devices */
aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
);
aml_append(dev, method);
+ method = aml_method("_DSM", 4, AML_SERIALIZED);
+ aml_append(method,
+ aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1),
+ aml_arg(2), aml_arg(3),
+ aml_name("BSEL"), aml_name("_SUN")))
+ );
+ aml_append(dev, method);
aml_append(parent_scope, dev);
build_append_pcihp_notify_entry(notify_method, slot);
pc = PCI_DEVICE_GET_CLASS(pdev);
dc = DEVICE_GET_CLASS(pdev);
- /* When hotplug for bridges is enabled, bridges are
- * described in ACPI separately (see build_pci_bus_end).
- * In this case they aren't themselves hot-pluggable.
+ /*
+ * Cold plugged bridges aren't themselves hot-pluggable.
* Hotplugged bridges *are* hot-pluggable.
*/
- bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
- !DEVICE(pdev)->hotplugged;
+ cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
+ bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
- hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
+ hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
continue;
dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
+ if (bsel) {
+ aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
+ method = aml_method("_DSM", 4, AML_SERIALIZED);
+ aml_append(method, aml_return(
+ aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
+ aml_arg(3), aml_name("BSEL"), aml_name("_SUN"))
+ ));
+ aml_append(dev, method);
+ }
+
if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
/* add VGA specific AML methods */
int s3d;
aml_append(method, aml_return(aml_int(s3d)));
aml_append(dev, method);
} else if (hotplug_enabled_dev) {
- /* add _SUN/_EJ0 to make slot hotpluggable */
- aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
-
+ /* add _EJ0 to make slot hotpluggable */
method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
aml_append(method,
aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
}
/* Append PCNT method to notify about events on local and child buses.
- * Add unconditionally for root since DSDT expects it.
+ * Add this method for root bus only when hotplug is enabled since DSDT
+ * expects it.
*/
- method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
-
- /* If bus supports hotplug select it and notify about local events */
- if (bsel) {
- uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
+ if (bsel || pcihp_bridge_en) {
+ method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
+
+ /* If bus supports hotplug select it and notify about local events */
+ if (bsel) {
+ uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
+
+ aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
+ aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
+ aml_int(1))); /* Device Check */
+ aml_append(method, aml_call2("DVNT", aml_name("PCID"),
+ aml_int(3))); /* Eject Request */
+ }
- aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
- aml_append(method,
- aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
- );
- aml_append(method,
- aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
- );
- }
+ /* Notify about child bus events in any case */
+ if (pcihp_bridge_en) {
+ QLIST_FOREACH(sec, &bus->child, sibling) {
+ int32_t devfn = sec->parent_dev->devfn;
- /* Notify about child bus events in any case */
- if (pcihp_bridge_en) {
- QLIST_FOREACH(sec, &bus->child, sibling) {
- int32_t devfn = sec->parent_dev->devfn;
+ if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
+ continue;
+ }
- if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
- continue;
+ aml_append(method, aml_name("^S%.02X.PCNT", devfn));
}
-
- aml_append(method, aml_name("^S%.02X.PCNT", devfn));
}
+
+ aml_append(parent_scope, method);
}
- aml_append(parent_scope, method);
qobject_unref(bsel);
}
+Aml *aml_pci_device_dsm(void)
+{
+ Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx;
+ Aml *acpi_index = aml_local(0);
+ Aml *zero = aml_int(0);
+ Aml *bnum = aml_arg(4);
+ Aml *func = aml_arg(2);
+ Aml *rev = aml_arg(1);
+ Aml *sun = aml_arg(5);
+
+ method = aml_method("PDSM", 6, AML_SERIALIZED);
+
+ /*
+ * PCI Firmware Specification 3.1
+ * 4.6. _DSM Definitions for PCI
+ */
+ UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
+ ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ {
+ aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));
+ ifctx1 = aml_if(aml_equal(func, zero));
+ {
+ uint8_t byte_list[1];
+
+ ifctx2 = aml_if(aml_equal(rev, aml_int(2)));
+ {
+ /*
+ * advertise function 7 if device has acpi-index
+ * acpi_index values:
+ * 0: not present (default value)
+ * FFFFFFFF: not supported (old QEMU without PIDX reg)
+ * other: device's acpi-index
+ */
+ ifctx3 = aml_if(aml_lnot(
+ aml_or(aml_equal(acpi_index, zero),
+ aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
+ ));
+ {
+ byte_list[0] =
+ 1 /* have supported functions */ |
+ 1 << 7 /* support for function 7 */
+ ;
+ aml_append(ifctx3, aml_return(aml_buffer(1, byte_list)));
+ }
+ aml_append(ifctx2, ifctx3);
+ }
+ aml_append(ifctx1, ifctx2);
+
+ byte_list[0] = 0; /* nothing supported */
+ aml_append(ifctx1, aml_return(aml_buffer(1, byte_list)));
+ }
+ aml_append(ifctx, ifctx1);
+ elsectx = aml_else();
+ /*
+ * PCI Firmware Specification 3.1
+ * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
+ * Operating Systems
+ */
+ ifctx1 = aml_if(aml_equal(func, aml_int(7)));
+ {
+ Aml *pkg = aml_package(2);
+ Aml *ret = aml_local(1);
+
+ aml_append(pkg, zero);
+ /*
+ * optional, if not impl. should return null string
+ */
+ aml_append(pkg, aml_string("%s", ""));
+ aml_append(ifctx1, aml_store(pkg, ret));
+ /*
+ * update acpi-index to actual value
+ */
+ aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
+ aml_append(ifctx1, aml_return(ret));
+ }
+ aml_append(elsectx, ifctx1);
+ aml_append(ifctx, elsectx);
+ }
+ aml_append(method, ifctx);
+ return method;
+}
+
/**
* build_prt_entry:
* @link_name: link name for PCI route entry
return method;
}
-typedef struct CrsRangeEntry {
- uint64_t base;
- uint64_t limit;
-} CrsRangeEntry;
-
-static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
-{
- CrsRangeEntry *entry;
-
- entry = g_malloc(sizeof(*entry));
- entry->base = base;
- entry->limit = limit;
-
- g_ptr_array_add(ranges, entry);
-}
-
-static void crs_range_free(gpointer data)
-{
- CrsRangeEntry *entry = (CrsRangeEntry *)data;
- g_free(entry);
-}
-
-typedef struct CrsRangeSet {
- GPtrArray *io_ranges;
- GPtrArray *mem_ranges;
- GPtrArray *mem_64bit_ranges;
- } CrsRangeSet;
-
-static void crs_range_set_init(CrsRangeSet *range_set)
-{
- range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- range_set->mem_64bit_ranges =
- g_ptr_array_new_with_free_func(crs_range_free);
-}
-
-static void crs_range_set_free(CrsRangeSet *range_set)
-{
- g_ptr_array_free(range_set->io_ranges, true);
- g_ptr_array_free(range_set->mem_ranges, true);
- g_ptr_array_free(range_set->mem_64bit_ranges, true);
-}
-
-static gint crs_range_compare(gconstpointer a, gconstpointer b)
-{
- CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
- CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
-
- if (entry_a->base < entry_b->base) {
- return -1;
- } else if (entry_a->base > entry_b->base) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/*
- * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
- * interval, computes the 'free' ranges from the same interval.
- * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
- * will return { [base - a1], [a2 - b1], [b2 - limit] }.
- */
-static void crs_replace_with_free_ranges(GPtrArray *ranges,
- uint64_t start, uint64_t end)
-{
- GPtrArray *free_ranges = g_ptr_array_new();
- uint64_t free_base = start;
- int i;
-
- g_ptr_array_sort(ranges, crs_range_compare);
- for (i = 0; i < ranges->len; i++) {
- CrsRangeEntry *used = g_ptr_array_index(ranges, i);
-
- if (free_base < used->base) {
- crs_range_insert(free_ranges, free_base, used->base - 1);
- }
-
- free_base = used->limit + 1;
- }
-
- if (free_base < end) {
- crs_range_insert(free_ranges, free_base, end);
- }
-
- g_ptr_array_set_size(ranges, 0);
- for (i = 0; i < free_ranges->len; i++) {
- g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
- }
-
- g_ptr_array_free(free_ranges, true);
-}
-
-/*
- * crs_range_merge - merges adjacent ranges in the given array.
- * Array elements are deleted and replaced with the merged ranges.
- */
-static void crs_range_merge(GPtrArray *range)
-{
- GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
- CrsRangeEntry *entry;
- uint64_t range_base, range_limit;
- int i;
-
- if (!range->len) {
- return;
- }
-
- g_ptr_array_sort(range, crs_range_compare);
-
- entry = g_ptr_array_index(range, 0);
- range_base = entry->base;
- range_limit = entry->limit;
- for (i = 1; i < range->len; i++) {
- entry = g_ptr_array_index(range, i);
- if (entry->base - 1 == range_limit) {
- range_limit = entry->limit;
- } else {
- crs_range_insert(tmp, range_base, range_limit);
- range_base = entry->base;
- range_limit = entry->limit;
- }
- }
- crs_range_insert(tmp, range_base, range_limit);
-
- g_ptr_array_set_size(range, 0);
- for (i = 0; i < tmp->len; i++) {
- entry = g_ptr_array_index(tmp, i);
- crs_range_insert(range, entry->base, entry->limit);
- }
- g_ptr_array_free(tmp, true);
-}
-
-static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
-{
- Aml *crs = aml_resource_template();
- CrsRangeSet temp_range_set;
- CrsRangeEntry *entry;
- uint8_t max_bus = pci_bus_num(host->bus);
- uint8_t type;
- int devfn;
- int i;
-
- crs_range_set_init(&temp_range_set);
- for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
- uint64_t range_base, range_limit;
- PCIDevice *dev = host->bus->devices[devfn];
-
- if (!dev) {
- continue;
- }
-
- for (i = 0; i < PCI_NUM_REGIONS; i++) {
- PCIIORegion *r = &dev->io_regions[i];
-
- range_base = r->addr;
- range_limit = r->addr + r->size - 1;
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (!range_base || range_base > range_limit) {
- continue;
- }
-
- if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
- crs_range_insert(temp_range_set.io_ranges,
- range_base, range_limit);
- } else { /* "memory" */
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
- }
- }
-
- type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
- if (type == PCI_HEADER_TYPE_BRIDGE) {
- uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
- if (subordinate > max_bus) {
- max_bus = subordinate;
- }
-
- range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
- range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- crs_range_insert(temp_range_set.io_ranges,
- range_base, range_limit);
- }
-
- range_base =
- pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
- range_limit =
- pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
-
- range_base =
- pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
- range_limit =
- pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
- }
- }
-
- crs_range_merge(temp_range_set.io_ranges);
- for (i = 0; i < temp_range_set.io_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.io_ranges, i);
- aml_append(crs,
- aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
- AML_POS_DECODE, AML_ENTIRE_RANGE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
- }
-
- crs_range_merge(temp_range_set.mem_ranges);
- for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
- aml_append(crs,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
- AML_MAX_FIXED, AML_NON_CACHEABLE,
- AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
- }
-
- crs_range_merge(temp_range_set.mem_64bit_ranges);
- for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
- aml_append(crs,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
- AML_MAX_FIXED, AML_NON_CACHEABLE,
- AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->mem_64bit_ranges,
- entry->base, entry->limit);
- }
-
- crs_range_set_free(&temp_range_set);
-
- aml_append(crs,
- aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- 0,
- pci_bus_num(host->bus),
- max_bus,
- 0,
- max_bus - pci_bus_num(host->bus) + 1));
-
- return crs;
-}
-
static void build_hpet_aml(Aml *table)
{
Aml *crs;
aml_append(table, scope);
}
-static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
-{
- Aml *dev, *fdi;
- uint8_t maxc, maxh, maxs;
-
- isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
-
- dev = aml_device("FLP%c", 'A' + idx);
-
- aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
-
- fdi = aml_package(16);
- aml_append(fdi, aml_int(idx)); /* Drive Number */
- aml_append(fdi,
- aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
- /*
- * the values below are the limits of the drive, and are thus independent
- * of the inserted media
- */
- aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
- aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
- aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
- /*
- * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
- * the drive type, so shall we
- */
- aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
- aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
- aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
- aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
- aml_append(fdi, aml_int(0x12)); /* disk_eot */
- aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
- aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
- aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
- aml_append(fdi, aml_int(0xF6)); /* disk_fill */
- aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
- aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
-
- aml_append(dev, aml_name_decl("_FDI", fdi));
- return dev;
-}
-
-static Aml *build_fdc_device_aml(ISADevice *fdc)
-{
- int i;
- Aml *dev;
- Aml *crs;
-
-#define ACPI_FDE_MAX_FD 4
- uint32_t fde_buf[5] = {
- 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
- cpu_to_le32(2) /* tape presence (2 == never present) */
- };
-
- dev = aml_device("FDC0");
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
-
- crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
- aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
- aml_append(crs, aml_irq_no_flags(6));
- aml_append(crs,
- aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
- FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
-
- if (type < FLOPPY_DRIVE_TYPE_NONE) {
- fde_buf[i] = cpu_to_le32(1); /* drive present */
- aml_append(dev, build_fdinfo_aml(i, type));
- }
- }
- aml_append(dev, aml_name_decl("_FDE",
- aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
-
- return dev;
-}
-
-static Aml *build_kbd_device_aml(void)
-{
- Aml *dev;
- Aml *crs;
-
- dev = aml_device("KBD");
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
-
- aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
-
- crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
- aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
- aml_append(crs, aml_irq_no_flags(1));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- return dev;
-}
-
-static Aml *build_mouse_device_aml(void)
+static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
{
Aml *dev;
+ Aml *method;
Aml *crs;
- dev = aml_device("MOU");
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
-
- aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
-
- crs = aml_resource_template();
- aml_append(crs, aml_irq_no_flags(12));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- return dev;
-}
+ dev = aml_device("VMBS");
+ aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
+ aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
+ aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
-static Aml *build_lpt_device_aml(void)
-{
- Aml *dev;
- Aml *crs;
- Aml *method;
- Aml *if_ctx;
- Aml *else_ctx;
- Aml *zero = aml_int(0);
- Aml *is_present = aml_local(0);
+ method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
+ aml_name("STA")));
+ aml_append(dev, method);
- dev = aml_device("LPT");
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
+ method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
+ aml_name("STA")));
+ aml_append(dev, method);
method = aml_method("_STA", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_store(aml_name("LPEN"), is_present));
- if_ctx = aml_if(aml_equal(is_present, zero));
- {
- aml_append(if_ctx, aml_return(aml_int(0x00)));
- }
- aml_append(method, if_ctx);
- else_ctx = aml_else();
- {
- aml_append(else_ctx, aml_return(aml_int(0x0f)));
- }
- aml_append(method, else_ctx);
+ aml_append(method, aml_return(aml_name("STA")));
aml_append(dev, method);
- crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
- aml_append(crs, aml_irq_no_flags(7));
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- return dev;
-}
-
-static void build_com_device_aml(Aml *scope, uint8_t uid)
-{
- Aml *dev;
- Aml *crs;
- uint8_t irq = 4;
- uint16_t io_port = 0x03F8;
-
- assert(uid == 1 || uid == 2);
- if (uid == 2) {
- irq = 3;
- io_port = 0x02F8;
- }
- if (!memory_region_present(get_system_io(), io_port)) {
- return;
- }
-
- dev = aml_device("COM%d", uid);
- aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
- aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
-
- aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
+ aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
- aml_append(crs, aml_irq_no_flags(irq));
+ aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
aml_append(dev, aml_name_decl("_CRS", crs));
- aml_append(scope, dev);
+ return dev;
}
static void build_isa_devices_aml(Aml *table)
{
- ISADevice *fdc = pc_find_fdc0();
bool ambiguous;
-
- Aml *scope = aml_scope("_SB.PCI0.ISA");
Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
+ Aml *scope;
- aml_append(scope, build_kbd_device_aml());
- aml_append(scope, build_mouse_device_aml());
- if (fdc) {
- aml_append(scope, build_fdc_device_aml(fdc));
- }
- aml_append(scope, build_lpt_device_aml());
- build_com_device_aml(scope, 1);
- build_com_device_aml(scope, 2);
+ assert(obj && !ambiguous);
- if (ambiguous) {
- error_report("Multiple ISA busses, unable to define IPMI ACPI data");
- } else if (!obj) {
- error_report("No ISA bus, unable to define IPMI ACPI data");
- } else {
- build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
- isa_build_aml(ISA_BUS(obj), scope);
- }
+ scope = aml_scope("_SB.PCI0.ISA");
+ build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
+ isa_build_aml(ISA_BUS(obj), scope);
aml_append(table, scope);
}
aml_append(table, sb_scope);
}
+static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
+{
+ Aml *dev;
+ Aml *resource_template;
+
+ /* DRAM controller */
+ dev = aml_device("DRAC");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
+
+ resource_template = aml_resource_template();
+ if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
+ aml_append(resource_template,
+ aml_qword_memory(AML_POS_DECODE,
+ AML_MIN_FIXED,
+ AML_MAX_FIXED,
+ AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0x0000000000000000,
+ mcfg->base,
+ mcfg->base + mcfg->size - 1,
+ 0x0000000000000000,
+ mcfg->size));
+ } else {
+ aml_append(resource_template,
+ aml_dword_memory(AML_POS_DECODE,
+ AML_MIN_FIXED,
+ AML_MAX_FIXED,
+ AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0x0000000000000000,
+ mcfg->base,
+ mcfg->base + mcfg->size - 1,
+ 0x0000000000000000,
+ mcfg->size));
+ }
+ aml_append(dev, aml_name_decl("_CRS", resource_template));
+
+ return dev;
+}
+
static void build_q35_isa_bridge(Aml *table)
{
Aml *dev;
Aml *scope;
- Aml *field;
scope = aml_scope("_SB.PCI0");
dev = aml_device("ISA");
aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
aml_int(0x60), 0x0C));
- aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
- aml_int(0x80), 0x02));
- field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
- aml_append(field, aml_named_field("COMA", 3));
- aml_append(field, aml_reserved_field(1));
- aml_append(field, aml_named_field("COMB", 3));
- aml_append(field, aml_reserved_field(1));
- aml_append(field, aml_named_field("LPTD", 2));
- aml_append(dev, field);
-
- aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
- aml_int(0x82), 0x02));
- /* enable bits */
- field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
- aml_append(field, aml_named_field("CAEN", 1));
- aml_append(field, aml_named_field("CBEN", 1));
- aml_append(field, aml_named_field("LPEN", 1));
- aml_append(dev, field);
-
- aml_append(scope, dev);
- aml_append(table, scope);
-}
-
-static void build_piix4_pm(Aml *table)
-{
- Aml *dev;
- Aml *scope;
-
- scope = aml_scope("_SB.PCI0");
- dev = aml_device("PX13");
- aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
-
- aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
- aml_int(0x00), 0xff));
aml_append(scope, dev);
aml_append(table, scope);
}
{
Aml *dev;
Aml *scope;
- Aml *field;
scope = aml_scope("_SB.PCI0");
dev = aml_device("ISA");
/* PIIX PCI to ISA irq remapping */
aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
aml_int(0x60), 0x04));
- /* enable bits */
- field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
- /* Offset(0x5f),, 7, */
- aml_append(field, aml_reserved_field(0x2f8));
- aml_append(field, aml_reserved_field(7));
- aml_append(field, aml_named_field("LPEN", 1));
- /* Offset(0x67),, 3, */
- aml_append(field, aml_reserved_field(0x38));
- aml_append(field, aml_reserved_field(3));
- aml_append(field, aml_named_field("CAEN", 1));
- aml_append(field, aml_reserved_field(3));
- aml_append(field, aml_named_field("CBEN", 1));
- aml_append(dev, field);
aml_append(scope, dev);
aml_append(table, scope);
aml_append(scope, field);
aml_append(scope,
- aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
+ aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x08));
field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
aml_append(field, aml_named_field("BNUM", 32));
+ aml_append(field, aml_named_field("PIDX", 32));
aml_append(scope, field);
aml_append(scope, aml_mutex("BLCK", 0));
aml_append(method, aml_return(aml_int(0)));
aml_append(scope, method);
+ method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
+ aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
+ aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
+ aml_append(method,
+ aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
+ aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
+ aml_append(method, aml_release(aml_name("BLCK")));
+ aml_append(method, aml_return(aml_local(0)));
+ aml_append(scope, method);
+
+ aml_append(scope, aml_pci_device_dsm());
+
aml_append(table, scope);
}
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
X86MachineState *x86ms = X86_MACHINE(machine);
AcpiMcfgInfo mcfg;
+ bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
uint32_t nr_mem = machine->ram_slots;
int root_bus_limit = 0xFF;
PCIBus *bus = NULL;
TPMIf *tpm = tpm_find();
int i;
+ VMBusBridge *vmbus_bridge = vmbus_bridge_find();
dsdt = init_aml_allocator();
dev = aml_device("PCI0");
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
- aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
aml_append(sb_scope, dev);
aml_append(dsdt, sb_scope);
- build_hpet_aml(dsdt);
- build_piix4_pm(dsdt);
+ if (misc->has_hpet) {
+ build_hpet_aml(dsdt);
+ }
build_piix4_isa_bridge(dsdt);
build_isa_devices_aml(dsdt);
- build_piix4_pci_hotplug(dsdt);
+ if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
+ build_piix4_pci_hotplug(dsdt);
+ }
build_piix4_pci0_int(dsdt);
} else {
sb_scope = aml_scope("_SB");
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
- aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
aml_append(dev, build_q35_osc_method());
aml_append(sb_scope, dev);
+ if (mcfg_valid) {
+ aml_append(sb_scope, build_q35_dram_controller(&mcfg));
+ }
+
+ if (pm->smi_on_cpuhp) {
+ /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
+ dev = aml_device("PCI0.SMI0");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
+ aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_io(
+ AML_DECODE16,
+ ACPI_PORT_SMI_CMD,
+ ACPI_PORT_SMI_CMD,
+ 1,
+ 2)
+ );
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
+ aml_int(ACPI_PORT_SMI_CMD), 2));
+ field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
+ AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("SMIC", 8));
+ aml_append(field, aml_reserved_field(8));
+ aml_append(dev, field);
+ aml_append(sb_scope, dev);
+ }
+
aml_append(dsdt, sb_scope);
- build_hpet_aml(dsdt);
+ if (misc->has_hpet) {
+ build_hpet_aml(dsdt);
+ }
build_q35_isa_bridge(dsdt);
build_isa_devices_aml(dsdt);
build_q35_pci0_int(dsdt);
}
}
+ if (vmbus_bridge) {
+ sb_scope = aml_scope("_SB");
+ aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
+ aml_append(dsdt, sb_scope);
+ }
+
if (pcmc->legacy_cpu_hotplug) {
build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
} else {
CPUHotplugFeatures opts = {
- .acpi_1_compatible = true, .has_legacy_cphp = true
+ .acpi_1_compatible = true, .has_legacy_cphp = true,
+ .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
+ .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
};
build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
"\\_SB.PCI0", "\\_GPE._E02");
{
aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
- if (misc->is_piix4) {
+ if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
method = aml_method("_E01", 0, AML_NOTSERIALIZED);
aml_append(method,
aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
}
aml_append(dev, build_prt(false));
- crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
+ crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
+ 0, 0, 0, 0);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
aml_append(dsdt, scope);
* the PCI0._CRS. Add mmconfig to the set so it will be excluded
* too.
*/
- if (acpi_get_mcfg(&mcfg)) {
+ if (mcfg_valid) {
crs_range_insert(crs_range_set.mem_ranges,
mcfg.base, mcfg.base + mcfg.size - 1);
}
crs_range_set_free(&crs_range_set);
/* reserve PCIHP resources */
- if (pm->pcihp_io_len) {
+ if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
dev = aml_device("PHPR");
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
aml_append(dev,
/* create fw_cfg node, unconditionally */
{
- /* when using port i/o, the 8-bit data register *always* overlaps
- * with half of the 16-bit control register. Hence, the total size
- * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
- * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
- uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg),
- "dma_enabled", NULL) ?
- ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
- FW_CFG_CTL_SIZE;
-
scope = aml_scope("\\_SB.PCI0");
- dev = aml_device("FWCF");
-
- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-
- /* device present, functioning, decoding, not shown in UI */
- aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
-
- crs = aml_resource_template();
- aml_append(crs,
- aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
- );
- aml_append(dev, aml_name_decl("_CRS", crs));
-
- aml_append(scope, dev);
+ fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
aml_append(dsdt, scope);
}
g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
build_header(linker, table_data,
(void *)(table_data->data + table_data->len - dsdt->buf->len),
- "DSDT", dsdt->buf->len, 1, NULL, NULL);
+ "DSDT", dsdt->buf->len, 1, x86ms->oem_id, x86ms->oem_table_id);
free_aml_allocator();
}
static void
-build_hpet(GArray *table_data, BIOSLinker *linker)
+build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
+ const char *oem_table_id)
{
Acpi20Hpet *hpet;
hpet->timer_block_id = cpu_to_le32(0x8086a201);
hpet->addr.address = cpu_to_le64(HPET_BASE);
build_header(linker, table_data,
- (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
+ (void *)hpet, "HPET", sizeof(*hpet), 1, oem_id, oem_table_id);
}
static void
-build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
+build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
+ const char *oem_id, const char *oem_table_id)
{
Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
ACPI_BUILD_TPMLOG_FILE, 0);
build_header(linker, table_data,
- (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
-}
-
-static void
-build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
-{
- Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
- unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
- unsigned log_addr_offset =
- (char *)&tpm2_ptr->log_area_start_address - table_data->data;
-
- tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
- if (TPM_IS_TIS_ISA(tpm_find())) {
- tpm2_ptr->control_area_address = cpu_to_le64(0);
- tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
- } else if (TPM_IS_CRB(tpm_find())) {
- tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
- tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
- } else {
- g_warn_if_reached();
- }
-
- tpm2_ptr->log_area_minimum_length =
- cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
-
- /* log area start address to be filled by Guest linker */
- bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
- log_addr_offset, log_addr_size,
- ACPI_BUILD_TPMLOG_FILE, 0);
- build_header(linker, table_data,
- (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
+ (void *)tcpa, "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id);
}
#define HOLE_640K_START (640 * KiB)
build_header(linker, table_data,
(void *)(table_data->data + srat_start),
"SRAT",
- table_data->len - srat_start, 1, NULL, NULL);
+ table_data->len - srat_start, 1, x86ms->oem_id,
+ x86ms->oem_table_id);
}
/*
* (version Oct. 2014 or later)
*/
static void
-build_dmar_q35(GArray *table_data, BIOSLinker *linker)
+build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
+ const char *oem_table_id)
{
int dmar_start = table_data->len;
}
build_header(linker, table_data, (void *)(table_data->data + dmar_start),
- "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
+ "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id);
}
/*
* Helpful to speedup Windows guests and ignored by others.
*/
static void
-build_waet(GArray *table_data, BIOSLinker *linker)
+build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
+ const char *oem_table_id)
{
int waet_start = table_data->len;
build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
build_header(linker, table_data, (void *)(table_data->data + waet_start),
- "WAET", table_data->len - waet_start, 1, NULL, NULL);
+ "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id);
}
/*
}
static void
-build_amd_iommu(GArray *table_data, BIOSLinker *linker)
+build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
+ const char *oem_table_id)
{
int ivhd_table_len = 24;
int iommu_start = table_data->len;
}
build_header(linker, table_data, (void *)(table_data->data + iommu_start),
- "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
+ "IVRS", table_data->len - iommu_start, 1, oem_id,
+ oem_table_id);
}
typedef
GArray *tables_blob = tables->table_data;
AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
Object *vmgenid_dev;
+ char *oem_id;
+ char *oem_table_id;
acpi_get_pm_info(machine, &pm);
acpi_get_misc_info(&misc);
acpi_get_pci_holes(&pci_hole, &pci_hole64);
acpi_get_slic_oem(&slic_oem);
+ if (slic_oem.id) {
+ oem_id = slic_oem.id;
+ } else {
+ oem_id = x86ms->oem_id;
+ }
+
+ if (slic_oem.table_id) {
+ oem_table_id = slic_oem.table_id;
+ } else {
+ oem_table_id = x86ms->oem_table_id;
+ }
+
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
ACPI_BUILD_DPRINTF("init ACPI tables\n");
pm.fadt.facs_tbl_offset = &facs;
pm.fadt.dsdt_tbl_offset = &dsdt;
pm.fadt.xdsdt_tbl_offset = &dsdt;
- build_fadt(tables_blob, tables->linker, &pm.fadt,
- slic_oem.id, slic_oem.table_id);
+ build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
aml_len += tables_blob->len - fadt;
acpi_add_table(table_offsets, tables_blob);
- build_madt(tables_blob, tables->linker, pcms);
+ acpi_build_madt(tables_blob, tables->linker, x86ms,
+ ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
+ x86ms->oem_table_id);
vmgenid_dev = find_vmgenid_dev();
if (vmgenid_dev) {
acpi_add_table(table_offsets, tables_blob);
vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
- tables->vmgenid, tables->linker);
+ tables->vmgenid, tables->linker, x86ms->oem_id);
}
if (misc.has_hpet) {
acpi_add_table(table_offsets, tables_blob);
- build_hpet(tables_blob, tables->linker);
+ build_hpet(tables_blob, tables->linker, x86ms->oem_id,
+ x86ms->oem_table_id);
}
if (misc.tpm_version != TPM_VERSION_UNSPEC) {
- acpi_add_table(table_offsets, tables_blob);
- build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
-
- if (misc.tpm_version == TPM_VERSION_2_0) {
+ if (misc.tpm_version == TPM_VERSION_1_2) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
+ x86ms->oem_id, x86ms->oem_table_id);
+ } else { /* TPM_VERSION_2_0 */
acpi_add_table(table_offsets, tables_blob);
- build_tpm2(tables_blob, tables->linker, tables->tcpalog);
+ build_tpm2(tables_blob, tables->linker, tables->tcpalog,
+ x86ms->oem_id, x86ms->oem_table_id);
}
}
if (pcms->numa_nodes) {
build_srat(tables_blob, tables->linker, machine);
if (machine->numa_state->have_numa_distance) {
acpi_add_table(table_offsets, tables_blob);
- build_slit(tables_blob, tables->linker, machine);
+ build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
+ x86ms->oem_table_id);
}
if (machine->numa_state->hmat_enabled) {
acpi_add_table(table_offsets, tables_blob);
- build_hmat(tables_blob, tables->linker, machine->numa_state);
+ build_hmat(tables_blob, tables->linker, machine->numa_state,
+ x86ms->oem_id, x86ms->oem_table_id);
}
}
if (acpi_get_mcfg(&mcfg)) {
acpi_add_table(table_offsets, tables_blob);
- build_mcfg(tables_blob, tables->linker, &mcfg);
+ build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
+ x86ms->oem_table_id);
}
if (x86_iommu_get_default()) {
IommuType IOMMUType = x86_iommu_get_type();
if (IOMMUType == TYPE_AMD) {
acpi_add_table(table_offsets, tables_blob);
- build_amd_iommu(tables_blob, tables->linker);
+ build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
+ x86ms->oem_table_id);
} else if (IOMMUType == TYPE_INTEL) {
acpi_add_table(table_offsets, tables_blob);
- build_dmar_q35(tables_blob, tables->linker);
+ build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
+ x86ms->oem_table_id);
}
}
if (machine->nvdimms_state->is_enabled) {
nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
- machine->nvdimms_state, machine->ram_slots);
+ machine->nvdimms_state, machine->ram_slots,
+ x86ms->oem_id, x86ms->oem_table_id);
}
acpi_add_table(table_offsets, tables_blob);
- build_waet(tables_blob, tables->linker);
+ build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
/* Add tables supplied by user (if any) */
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
/* RSDT is pointed to by RSDP */
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets,
- slic_oem.id, slic_oem.table_id);
+ oem_id, oem_table_id);
/* RSDP is in FSEG memory, so allocate it separately */
{
AcpiRsdpData rsdp_data = {
.revision = 0,
- .oem_id = ACPI_BUILD_APPNAME6,
+ .oem_id = x86ms->oem_id,
.xsdt_tbl_offset = NULL,
.rsdt_tbl_offset = &rsdt,
};
/* Now expose it all to Guest */
build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
build_state, tables.table_data,
- ACPI_BUILD_TABLE_FILE,
- ACPI_BUILD_TABLE_MAX_SIZE);
+ ACPI_BUILD_TABLE_FILE);
assert(build_state->table_mr != NULL);
build_state->linker_mr =
acpi_add_rom_blob(acpi_build_update, build_state,
- tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
+ tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
tables.tcpalog->data, acpi_data_len(tables.tcpalog));
build_state->rsdp = NULL;
build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
build_state, tables.rsdp,
- ACPI_BUILD_RSDP_FILE, 0);
+ ACPI_BUILD_RSDP_FILE);
}
qemu_register_reset(acpi_build_reset, build_state);
projects / qemu.git / blobdiff