Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-/*
- TODO-list:
-
- Rest of V9 instructions, VIS instructions
- NPC/PC static optimisations (use JUMP_TB when possible)
- Optimize synthetic instructions
-*/
-
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
according to jump_pc[T2] */
/* global register indexes */
-static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
+static TCGv cpu_env, cpu_T[2], cpu_regwptr;
+static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
#ifdef TARGET_SPARC64
int mem_idx;
int fpu_enabled;
struct TranslationBlock *tb;
+ uint32_t features;
} DisasContext;
-extern FILE *logfile;
-extern int loglevel;
-
// This function uses non-native bit order
#define GET_FIELD(X, FROM, TO) \
((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
static void gen_op_load_fpr_DT0(unsigned int src)
{
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ offsetof(CPU_DoubleU, l.upper));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ offsetof(CPU_DoubleU, l.lower));
}
static void gen_op_load_fpr_DT1(unsigned int src)
{
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
+ offsetof(CPU_DoubleU, l.upper));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
+ offsetof(CPU_DoubleU, l.lower));
}
static void gen_op_store_DT0_fpr(unsigned int dst)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ offsetof(CPU_DoubleU, l.upper));
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ offsetof(CPU_DoubleU, l.lower));
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
}
-#ifdef CONFIG_USER_ONLY
static void gen_op_load_fpr_QT0(unsigned int src)
{
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.upmost));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.upper));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.lower));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.lowest));
}
static void gen_op_load_fpr_QT1(unsigned int src)
{
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ offsetof(CPU_QuadU, l.upmost));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ offsetof(CPU_QuadU, l.upper));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ offsetof(CPU_QuadU, l.lower));
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ offsetof(CPU_QuadU, l.lowest));
}
static void gen_op_store_QT0_fpr(unsigned int dst)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.upmost));
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.upper));
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.lower));
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ offsetof(CPU_QuadU, l.lowest));
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
}
-#endif
/* moves */
#ifdef CONFIG_USER_ONLY
#ifdef TARGET_SPARC64
#define hypervisor(dc) 0
#endif
-#define gen_op_ldst(name) gen_op_##name##_raw()
#else
#define supervisor(dc) (dc->mem_idx >= 1)
#ifdef TARGET_SPARC64
#define hypervisor(dc) (dc->mem_idx == 2)
-#define OP_LD_TABLE(width) \
- static GenOpFunc * const gen_op_##width[] = { \
- &gen_op_##width##_user, \
- &gen_op_##width##_kernel, \
- &gen_op_##width##_hypv, \
- };
#else
-#define OP_LD_TABLE(width) \
- static GenOpFunc * const gen_op_##width[] = { \
- &gen_op_##width##_user, \
- &gen_op_##width##_kernel, \
- };
#endif
-#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
-#endif
-
-#ifndef CONFIG_USER_ONLY
-#ifdef __i386__
-OP_LD_TABLE(std);
-#endif /* __i386__ */
-OP_LD_TABLE(stdf);
-OP_LD_TABLE(lddf);
#endif
#ifdef TARGET_ABI32
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
- int l1;
-
- l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
- gen_set_label(l1);
+ tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+ tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
}
#ifdef TARGET_SPARC64
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
- int l1;
-
- l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
- gen_set_label(l1);
+ tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+ tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
}
#endif
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_add_tl(dst, src1, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
- gen_cc_C_add_icc(dst, cpu_cc_src);
- gen_cc_V_add_icc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
- gen_cc_NZ_xcc(dst);
- gen_cc_C_add_xcc(dst, cpu_cc_src);
- gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_add_tl(dst, src1, cpu_tmp0);
gen_cc_clear_icc();
gen_cc_clear_xcc();
gen_cc_C_add_xcc(dst, cpu_cc_src);
#endif
- tcg_gen_add_tl(dst, dst, src2);
- gen_cc_NZ_icc(dst);
- gen_cc_C_add_icc(dst, cpu_cc_src);
- gen_cc_V_add_icc(dst, cpu_cc_src, src2);
+ tcg_gen_add_tl(dst, dst, cpu_cc_src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
- gen_cc_NZ_xcc(dst);
- gen_cc_C_add_xcc(dst, cpu_cc_src);
- gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_add_tl(dst, src1, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
- gen_cc_C_add_icc(dst, cpu_cc_src);
- gen_cc_V_add_icc(dst, cpu_cc_src, src2);
- gen_cc_V_tag(cpu_cc_src, src2);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
+ gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
- gen_cc_NZ_xcc(dst);
- gen_cc_C_add_xcc(dst, cpu_cc_src);
- gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
{
- gen_tag_tv(src1, src2);
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
+ gen_tag_tv(cpu_cc_src, cpu_cc_src2);
tcg_gen_add_tl(dst, src1, src2);
- gen_add_tv(dst, cpu_cc_src, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ gen_add_tv(dst, cpu_cc_src, cpu_cc_src2);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
- gen_cc_C_add_icc(dst, cpu_cc_src);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
- gen_cc_NZ_xcc(dst);
- gen_cc_C_add_xcc(dst, cpu_cc_src);
- gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
- int l1;
-
- l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
- gen_set_label(l1);
+ tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+ tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
}
#ifdef TARGET_SPARC64
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
- int l1;
-
- l1 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_xor_tl(r_temp, src1, src2);
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
- tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
- gen_set_label(l1);
+ tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+ tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
}
#endif
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_sub_tl(dst, src1, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
- gen_cc_C_sub_icc(cpu_cc_src, src2);
- gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
+ gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
- gen_cc_NZ_xcc(dst);
- gen_cc_C_sub_xcc(cpu_cc_src, src2);
- gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
+ gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_sub_tl(dst, src1, cpu_tmp0);
gen_cc_clear_icc();
gen_cc_clear_xcc();
gen_cc_C_sub_xcc(dst, cpu_cc_src);
#endif
- tcg_gen_sub_tl(dst, dst, src2);
- gen_cc_NZ_icc(dst);
- gen_cc_C_sub_icc(dst, cpu_cc_src);
- gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
+ tcg_gen_sub_tl(dst, dst, cpu_cc_src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
- gen_cc_NZ_xcc(dst);
- gen_cc_C_sub_xcc(dst, cpu_cc_src);
- gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
+ gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_sub_tl(dst, src1, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
- gen_cc_C_sub_icc(cpu_cc_src, src2);
- gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
- gen_cc_V_tag(cpu_cc_src, src2);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
+ gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
+ gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
- gen_cc_NZ_xcc(dst);
- gen_cc_C_sub_xcc(cpu_cc_src, src2);
- gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
+ gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
{
- gen_tag_tv(src1, src2);
tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
+ gen_tag_tv(cpu_cc_src, cpu_cc_src2);
tcg_gen_sub_tl(dst, src1, src2);
- gen_sub_tv(dst, cpu_cc_src, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
- gen_cc_C_sub_icc(cpu_cc_src, src2);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
- gen_cc_NZ_xcc(dst);
- gen_cc_C_sub_xcc(cpu_cc_src, src2);
- gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
+ gen_cc_NZ_xcc(cpu_cc_dst);
+ gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
+ gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
#endif
}
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp, r_temp2;
- int l1, l2;
+ int l1;
l1 = gen_new_label();
- l2 = gen_new_label();
r_temp = tcg_temp_new(TCG_TYPE_TL);
r_temp2 = tcg_temp_new(TCG_TYPE_I32);
if (!(env->y & 1))
T1 = 0;
*/
+ tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
tcg_gen_trunc_tl_i32(r_temp2, r_temp);
tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
- tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
- tcg_gen_br(l2);
- gen_set_label(l1);
+ tcg_gen_brcond_i32(TCG_COND_NE, r_temp2, tcg_const_i32(0), l1);
tcg_gen_movi_tl(cpu_cc_src2, 0);
- gen_set_label(l2);
+ gen_set_label(l1);
// b2 = T0 & 1;
// env->y = (b2 << 31) | (env->y >> 1);
- tcg_gen_trunc_tl_i32(r_temp2, src1);
+ tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
tcg_gen_shli_i32(r_temp2, r_temp2, 31);
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
// T0 = (b1 << 31) | (T0 >> 1);
// src1 = T0;
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
- tcg_gen_shri_tl(cpu_cc_src, src1, 1);
+ tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
/* do addition and update flags */
tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
- gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_C_add_icc(dst, cpu_cc_src);
+ gen_cc_NZ_icc(cpu_cc_dst);
+ gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
+ gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
}
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
l1 = gen_new_label();
l2 = gen_new_label();
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
gen_trap_ifdivzero_tl(src2);
- tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1);
- tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1);
+ tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src, tcg_const_tl(INT64_MIN), l1);
+ tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src2, tcg_const_tl(-1), l1);
tcg_gen_movi_i64(dst, INT64_MIN);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_div_i64(dst, src1, src2);
+ tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
gen_set_label(l2);
}
#endif
{
int l1;
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
+ gen_cc_NZ_icc(cpu_cc_dst);
l1 = gen_new_label();
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
static inline void gen_op_logic_cc(TCGv dst)
{
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+
gen_cc_clear_icc();
- gen_cc_NZ_icc(dst);
+ gen_cc_NZ_icc(cpu_cc_dst);
#ifdef TARGET_SPARC64
gen_cc_clear_xcc();
- gen_cc_NZ_xcc(dst);
+ gen_cc_NZ_xcc(cpu_cc_dst);
#endif
}
helper_fcmpd_fcc3,
};
-#if defined(CONFIG_USER_ONLY)
static GenOpFunc * const gen_fcmpq[4] = {
helper_fcmpq,
helper_fcmpq_fcc1,
helper_fcmpq_fcc2,
helper_fcmpq_fcc3,
};
-#endif
static GenOpFunc * const gen_fcmpes[4] = {
helper_fcmpes,
helper_fcmped_fcc3,
};
-#if defined(CONFIG_USER_ONLY)
static GenOpFunc * const gen_fcmpeq[4] = {
helper_fcmpeq,
helper_fcmpeq_fcc1,
helper_fcmpeq_fcc2,
helper_fcmpeq_fcc3,
};
-#endif
static inline void gen_op_fcmps(int fccno)
{
tcg_gen_helper_0_0(gen_fcmpd[fccno]);
}
-#if defined(CONFIG_USER_ONLY)
static inline void gen_op_fcmpq(int fccno)
{
tcg_gen_helper_0_0(gen_fcmpq[fccno]);
}
-#endif
static inline void gen_op_fcmpes(int fccno)
{
tcg_gen_helper_0_0(gen_fcmped[fccno]);
}
-#if defined(CONFIG_USER_ONLY)
static inline void gen_op_fcmpeq(int fccno)
{
tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
}
-#endif
#else
tcg_gen_helper_0_0(helper_fcmpd);
}
-#if defined(CONFIG_USER_ONLY)
static inline void gen_op_fcmpq(int fccno)
{
tcg_gen_helper_0_0(helper_fcmpq);
}
-#endif
static inline void gen_op_fcmpes(int fccno)
{
tcg_gen_helper_0_0(helper_fcmped);
}
-#if defined(CONFIG_USER_ONLY)
static inline void gen_op_fcmpeq(int fccno)
{
tcg_gen_helper_0_0(helper_fcmpeq);
}
#endif
-#endif
-
static inline void gen_op_fpexception_im(int fsr_flags)
{
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
return r_asi;
}
-static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
+static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
+ int sign)
{
TCGv r_asi;
tcg_const_i32(8));
}
-static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
+static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
+ int rd)
{
TCGv r_val1, r_asi;
tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
}
-static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
+static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
+ int rd)
{
TCGv r_asi;
#elif !defined(CONFIG_USER_ONLY)
-static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
+static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
+ int sign)
{
int asi;
return r_rs2;
}
+#define CHECK_IU_FEATURE(dc, FEATURE) \
+ if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
+ goto illegal_insn;
+#define CHECK_FPU_FEATURE(dc, FEATURE) \
+ if (!((dc)->features & CPU_FEATURE_ ## FEATURE)) \
+ goto nfpu_insn;
+
/* before an instruction, dc->pc must be static */
static void disas_sparc_insn(DisasContext * dc)
{
case 0x4: /* SETHI */
if (rd) { // nop
uint32_t value = GET_FIELD(insn, 10, 31);
- tcg_gen_movi_tl(cpu_dst, value << 10);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_movl_TN_reg(rd, tcg_const_tl(value << 10));
}
break;
case 0x0: /* UNIMPL */
if (rs2 != 0) {
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ } else
+ tcg_gen_mov_tl(cpu_dst, cpu_src1);
}
cond = GET_FIELD(insn, 3, 6);
if (cond == 0x8) {
SPARCv8 manual, rdy on the
microSPARC II */
#endif
- tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
+ tcg_gen_ld_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, y));
gen_movl_TN_reg(rd, cpu_dst);
break;
#ifdef TARGET_SPARC64
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x3: /* V9 rdasi */
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, asi));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
gen_movl_TN_reg(rd, cpu_dst);
break;
}
break;
case 0x5: /* V9 rdpc */
- tcg_gen_movi_tl(cpu_dst, dc->pc);
- gen_movl_TN_reg(rd, cpu_dst);
+ gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
break;
case 0x6: /* V9 rdfprs */
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, fprs));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc, cpu_cond))
goto jmp_insn;
- tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
+ tcg_gen_ld_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, gsr));
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x17: /* Tick compare */
- tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
+ tcg_gen_ld_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, tick_cmpr));
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x18: /* System tick */
}
break;
case 0x19: /* System tick compare */
- tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
+ tcg_gen_ld_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, stick_cmpr));
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x10: /* Performance Control */
// gen_op_rdhtstate();
break;
case 3: // hintp
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, hintp));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 5: // htba
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, htba));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 6: // hver
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, hver));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 31: // hstick_cmpr
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, hstick_cmpr));
break;
default:
goto illegal_insn;
}
break;
case 5: // tba
- tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
+ tcg_gen_ld_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, tbr));
break;
case 6: // pstate
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, pstate));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 7: // tl
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, tl));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 8: // pil
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, psrpil));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 9: // cwp
tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
break;
case 10: // cansave
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, cansave));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 11: // canrestore
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, canrestore));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 12: // cleanwin
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, cleanwin));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 13: // otherwin
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, otherwin));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 14: // wstate
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, wstate));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 16: // UA2005 gl
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, gl));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 26: // UA2005 strand status
if (!hypervisor(dc))
goto priv_insn;
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, ssr));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break;
case 31: // ver
- tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
+ tcg_gen_ld_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, version));
break;
case 15: // fq
default:
goto illegal_insn;
}
#else
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, wim));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
#endif
gen_movl_TN_reg(rd, cpu_dst);
gen_op_store_FT0_fpr(rd);
break;
case 0x29: /* fsqrts */
+ CHECK_FPU_FEATURE(dc, FSQRT);
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fsqrts);
gen_op_store_FT0_fpr(rd);
break;
case 0x2a: /* fsqrtd */
+ CHECK_FPU_FEATURE(dc, FSQRT);
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fsqrtd);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x2b: /* fsqrtq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fsqrtq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x41:
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x43: /* faddq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x45:
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x47: /* fsubq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
- case 0x49:
+ case 0x49: /* fmuls */
+ CHECK_FPU_FEATURE(dc, FMUL);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
- case 0x4a:
+ case 0x4a: /* fmuld */
+ CHECK_FPU_FEATURE(dc, FMUL);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x4b: /* fmulq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ CHECK_FPU_FEATURE(dc, FMUL);
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x4d:
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x4f: /* fdivq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x69:
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x6e: /* fdmulq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0xc4:
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
gen_op_store_FT0_fpr(rd);
break;
case 0xc7: /* fqtos */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fqtos);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
-#else
- goto nfpu_insn;
-#endif
case 0xc8:
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fitod);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0xcb: /* fqtod */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fqtod);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0xcc: /* fitoq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fitoq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0xcd: /* fstoq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fstoq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0xce: /* fdtoq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fdtoq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0xd1:
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
gen_op_store_FT0_fpr(rd);
break;
case 0xd3: /* fqtoi */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fqtoi);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_FT0_fpr(rd);
break;
-#else
- goto nfpu_insn;
-#endif
#ifdef TARGET_SPARC64
case 0x2: /* V9 fmovd */
gen_op_load_fpr_DT0(DFPREG(rs2));
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x3: /* V9 fmovq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rs2));
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x6: /* V9 fnegd */
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fnegd);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x7: /* V9 fnegq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
tcg_gen_helper_0_0(helper_fnegq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0xa: /* V9 fabsd */
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fabsd);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0xb: /* V9 fabsq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
tcg_gen_helper_0_0(helper_fabsq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x81: /* V9 fstox */
gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x83: /* V9 fqtox */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fqtox);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x84: /* V9 fxtos */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x8c: /* V9 fxtoq */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
tcg_gen_helper_0_0(helper_fxtoq);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
#endif
default:
goto illegal_insn;
gen_set_label(l1);
break;
} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
-#if defined(CONFIG_USER_ONLY)
int l1;
+ CHECK_FPU_FEATURE(dc, FLOAT128);
l1 = gen_new_label();
cond = GET_FIELD_SP(insn, 14, 17);
cpu_src1 = get_src1(insn, cpu_src1);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_set_label(l1);
break;
-#else
- goto nfpu_insn;
-#endif
}
#endif
switch (xop) {
gen_fcond(r_cond, fcc, cond); \
tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
tcg_const_tl(0), l1); \
- glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
- glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
+ glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
+ (glue(size_FDQ, FPREG(rs2))); \
+ glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
+ (glue(size_FDQ, FPREG(rd))); \
gen_set_label(l1); \
}
case 0x001: /* V9 fmovscc %fcc0 */
FMOVCC(D, 0);
break;
case 0x003: /* V9 fmovqcc %fcc0 */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
FMOVCC(Q, 0);
break;
-#else
- goto nfpu_insn;
-#endif
case 0x041: /* V9 fmovscc %fcc1 */
FMOVCC(F, 1);
break;
FMOVCC(D, 1);
break;
case 0x043: /* V9 fmovqcc %fcc1 */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
FMOVCC(Q, 1);
break;
-#else
- goto nfpu_insn;
-#endif
case 0x081: /* V9 fmovscc %fcc2 */
FMOVCC(F, 2);
break;
FMOVCC(D, 2);
break;
case 0x083: /* V9 fmovqcc %fcc2 */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
FMOVCC(Q, 2);
break;
-#else
- goto nfpu_insn;
-#endif
case 0x0c1: /* V9 fmovscc %fcc3 */
FMOVCC(F, 3);
break;
FMOVCC(D, 3);
break;
case 0x0c3: /* V9 fmovqcc %fcc3 */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
FMOVCC(Q, 3);
break;
-#else
- goto nfpu_insn;
-#endif
#undef FMOVCC
#define FMOVCC(size_FDQ, icc) \
{ \
gen_cond(r_cond, icc, cond); \
tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \
tcg_const_tl(0), l1); \
- glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
- glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
+ glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
+ (glue(size_FDQ, FPREG(rs2))); \
+ glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
+ (glue(size_FDQ, FPREG(rd))); \
gen_set_label(l1); \
}
case 0x102: /* V9 fmovdcc %icc */
FMOVCC(D, 0);
case 0x103: /* V9 fmovqcc %icc */
-#if defined(CONFIG_USER_ONLY)
- FMOVCC(D, 0);
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ FMOVCC(Q, 0);
break;
-#else
- goto nfpu_insn;
-#endif
case 0x181: /* V9 fmovscc %xcc */
FMOVCC(F, 1);
break;
FMOVCC(D, 1);
break;
case 0x183: /* V9 fmovqcc %xcc */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
FMOVCC(Q, 1);
break;
-#else
- goto nfpu_insn;
-#endif
#undef FMOVCC
#endif
case 0x51: /* fcmps, V9 %fcc */
gen_op_fcmpd(rd & 3);
break;
case 0x53: /* fcmpq, V9 %fcc */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_op_fcmpq(rd & 3);
break;
-#else /* !defined(CONFIG_USER_ONLY) */
- goto nfpu_insn;
-#endif
case 0x55: /* fcmpes, V9 %fcc */
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
gen_op_fcmped(rd & 3);
break;
case 0x57: /* fcmpeq, V9 %fcc */
-#if defined(CONFIG_USER_ONLY)
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_op_fcmpeq(rd & 3);
break;
-#else/* !defined(CONFIG_USER_ONLY) */
- goto nfpu_insn;
-#endif
default:
goto illegal_insn;
}
// or %g0, x, y -> mov T0, x; mov y, T0
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
- tcg_gen_movi_tl(cpu_dst, (int)rs2);
+ gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_TN(rs2, cpu_dst);
+ gen_movl_TN_reg(rd, cpu_dst);
}
} else {
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
+ gen_movl_TN_reg(rd, cpu_dst);
} else { /* register */
// or x, %g0, y -> mov T1, x; mov y, T1
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 != 0) {
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ gen_movl_TN_reg(rd, cpu_dst);
+ } else
+ gen_movl_TN_reg(rd, cpu_src1);
}
}
- gen_movl_TN_reg(rd, cpu_dst);
#ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx */
cpu_src1 = get_src1(insn, cpu_src1);
break;
#endif
case 0xa:
+ CHECK_IU_FEATURE(dc, MUL);
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
case 0xb:
+ CHECK_IU_FEATURE(dc, MUL);
gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
#endif
case 0xe:
- tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
+ CHECK_IU_FEATURE(dc, DIV);
+ tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
+ cpu_src2);
if (xop & 0x10)
gen_op_div_cc(cpu_dst);
break;
case 0xf:
- tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
+ CHECK_IU_FEATURE(dc, DIV);
+ tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
+ cpu_src2);
if (xop & 0x10)
gen_op_div_cc(cpu_dst);
break;
break;
#ifndef TARGET_SPARC64
case 0x25: /* sll */
- tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
- tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 20, 31);
+ tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+ } else { /* register */
+ tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
+ tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x26: /* srl */
- tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
- tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 20, 31);
+ tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+ } else { /* register */
+ tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
+ tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x27: /* sra */
- tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
- tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 20, 31);
+ tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+ } else { /* register */
+ tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
+ tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
gen_movl_TN_reg(rd, cpu_dst);
break;
#endif
switch(rd) {
case 0: /* wry */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
+ tcg_gen_st_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, y));
break;
#ifndef TARGET_SPARC64
case 0x01 ... 0x0f: /* undefined in the
case 0x3: /* V9 wrasi */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, asi));
break;
case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, fprs));
save_state(dc, cpu_cond);
gen_op_next_insn();
tcg_gen_exit_tb(0);
if (gen_trap_ifnofpu(dc, cpu_cond))
goto jmp_insn;
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
+ tcg_gen_st_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, gsr));
break;
case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
tcg_gen_xor_tl(cpu_dst, cpu_src1,
cpu_src2);
- tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
- tick_cmpr));
+ tcg_gen_st_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState,
+ tick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, tick));
tcg_gen_xor_tl(cpu_dst, cpu_src1,
cpu_src2);
- tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
- stick_cmpr));
+ tcg_gen_st_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState,
+ stick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, stick));
break;
case 0x10: /* Performance Control */
- case 0x11: /* Performance Instrumentation Counter */
+ case 0x11: /* Performance Instrumentation
+ Counter */
case 0x12: /* Dispatch Control */
case 0x14: /* Softint set */
case 0x15: /* Softint clear */
tcg_gen_ld_ptr(r_tsptr, cpu_env,
offsetof(CPUState, tsptr));
tcg_gen_st_tl(cpu_dst, r_tsptr,
- offsetof(trap_state, tstate));
+ offsetof(trap_state,
+ tstate));
}
break;
case 3: // tt
}
break;
case 5: // tba
- tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
+ tcg_gen_st_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, tbr));
break;
case 6: // pstate
save_state(dc, cpu_cond);
break;
case 7: // tl
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, tl));
break;
case 8: // pil
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState,
+ psrpil));
break;
case 9: // cwp
tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
break;
case 10: // cansave
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState,
+ cansave));
break;
case 11: // canrestore
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState,
+ canrestore));
break;
case 12: // cleanwin
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState,
+ cleanwin));
break;
case 13: // otherwin
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState,
+ otherwin));
break;
case 14: // wstate
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState,
+ wstate));
break;
case 16: // UA2005 gl
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, gl));
break;
case 26: // UA2005 strand status
if (!hypervisor(dc))
goto priv_insn;
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, ssr));
break;
default:
goto illegal_insn;
}
#else
- tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
+ tcg_gen_andi_tl(cpu_dst, cpu_dst,
+ ((1 << NWINDOWS) - 1));
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, wim));
#endif
}
break;
if (!supervisor(dc))
goto priv_insn;
tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
- tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
+ tcg_gen_st_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, tbr));
#else
if (!hypervisor(dc))
goto priv_insn;
break;
case 3: // hintp
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, hintp));
break;
case 5: // htba
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
+ tcg_gen_st_i32(cpu_tmp32, cpu_env,
+ offsetof(CPUSPARCState, htba));
break;
case 31: // hstick_cmpr
{
TCGv r_tickptr;
- tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
- hstick_cmpr));
+ tcg_gen_st_tl(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState,
+ hstick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, hstick));
tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 10);
- tcg_gen_movi_tl(cpu_dst, (int)rs2);
+ gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_TN(rs2, cpu_dst);
+ gen_movl_reg_TN(rs2, cpu_tmp0);
+ gen_movl_TN_reg(rd, cpu_tmp0);
}
- gen_movl_TN_reg(rd, cpu_dst);
gen_set_label(l1);
break;
}
tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 9);
- tcg_gen_movi_tl(cpu_dst, (int)rs2);
+ gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
- gen_movl_reg_TN(rs2, cpu_dst);
+ gen_movl_reg_TN(rs2, cpu_tmp0);
+ gen_movl_TN_reg(rd, cpu_tmp0);
}
- gen_movl_TN_reg(rd, cpu_dst);
gen_set_label(l1);
break;
}
// XXX
goto illegal_insn;
case 0x010: /* VIS I array8 */
+ CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x012: /* VIS I array16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x014: /* VIS I array32 */
+ CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x018: /* VIS I alignaddr */
+ CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
// XXX
goto illegal_insn;
case 0x020: /* VIS I fcmple16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmple16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x022: /* VIS I fcmpne16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmpne16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x024: /* VIS I fcmple32 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmple32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x026: /* VIS I fcmpne32 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmpne32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x028: /* VIS I fcmpgt16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmpgt16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x02a: /* VIS I fcmpeq16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmpeq16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x02c: /* VIS I fcmpgt32 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmpgt32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x02e: /* VIS I fcmpeq32 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fcmpeq32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x031: /* VIS I fmul8x16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fmul8x16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x033: /* VIS I fmul8x16au */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fmul8x16au);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x035: /* VIS I fmul8x16al */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fmul8x16al);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x036: /* VIS I fmul8sux16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fmul8sux16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x037: /* VIS I fmul8ulx16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fmul8ulx16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x038: /* VIS I fmuld8sux16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fmuld8sux16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x039: /* VIS I fmuld8ulx16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fmuld8ulx16);
// XXX
goto illegal_insn;
case 0x048: /* VIS I faligndata */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_faligndata);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x04b: /* VIS I fpmerge */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fpmerge);
// XXX
goto illegal_insn;
case 0x04d: /* VIS I fexpand */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fexpand);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x050: /* VIS I fpadd16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fpadd16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x051: /* VIS I fpadd16s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fpadd16s);
gen_op_store_FT0_fpr(rd);
break;
case 0x052: /* VIS I fpadd32 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fpadd32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x053: /* VIS I fpadd32s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fpadd32s);
gen_op_store_FT0_fpr(rd);
break;
case 0x054: /* VIS I fpsub16 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fpsub16);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x055: /* VIS I fpsub16s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fpsub16s);
gen_op_store_FT0_fpr(rd);
break;
case 0x056: /* VIS I fpsub32 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fpadd32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x057: /* VIS I fpsub32s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fpsub32s);
gen_op_store_FT0_fpr(rd);
break;
case 0x060: /* VIS I fzero */
+ CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_helper_0_0(helper_movl_DT0_0);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x061: /* VIS I fzeros */
+ CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_helper_0_0(helper_movl_FT0_0);
gen_op_store_FT0_fpr(rd);
break;
case 0x062: /* VIS I fnor */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fnor);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x063: /* VIS I fnors */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fnors);
gen_op_store_FT0_fpr(rd);
break;
case 0x064: /* VIS I fandnot2 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT1(DFPREG(rs1));
gen_op_load_fpr_DT0(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fandnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x065: /* VIS I fandnot2s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT1(rs1);
gen_op_load_fpr_FT0(rs2);
tcg_gen_helper_0_0(helper_fandnots);
gen_op_store_FT0_fpr(rd);
break;
case 0x066: /* VIS I fnot2 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x067: /* VIS I fnot2s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fnot);
gen_op_store_FT0_fpr(rd);
break;
case 0x068: /* VIS I fandnot1 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fandnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x069: /* VIS I fandnot1s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fandnots);
gen_op_store_FT0_fpr(rd);
break;
case 0x06a: /* VIS I fnot1 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT1(DFPREG(rs1));
tcg_gen_helper_0_0(helper_fnot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x06b: /* VIS I fnot1s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT1(rs1);
tcg_gen_helper_0_0(helper_fnot);
gen_op_store_FT0_fpr(rd);
break;
case 0x06c: /* VIS I fxor */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fxor);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x06d: /* VIS I fxors */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fxors);
gen_op_store_FT0_fpr(rd);
break;
case 0x06e: /* VIS I fnand */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fnand);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x06f: /* VIS I fnands */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fnands);
gen_op_store_FT0_fpr(rd);
break;
case 0x070: /* VIS I fand */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fand);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x071: /* VIS I fands */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fands);
gen_op_store_FT0_fpr(rd);
break;
case 0x072: /* VIS I fxnor */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fxnor);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x073: /* VIS I fxnors */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fxnors);
gen_op_store_FT0_fpr(rd);
break;
case 0x074: /* VIS I fsrc1 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x075: /* VIS I fsrc1s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_store_FT0_fpr(rd);
break;
case 0x076: /* VIS I fornot2 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT1(DFPREG(rs1));
gen_op_load_fpr_DT0(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fornot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x077: /* VIS I fornot2s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT1(rs1);
gen_op_load_fpr_FT0(rs2);
tcg_gen_helper_0_0(helper_fornots);
gen_op_store_FT0_fpr(rd);
break;
case 0x078: /* VIS I fsrc2 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs2));
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x079: /* VIS I fsrc2s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs2);
gen_op_store_FT0_fpr(rd);
break;
case 0x07a: /* VIS I fornot1 */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_fornot);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x07b: /* VIS I fornot1s */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fornots);
gen_op_store_FT0_fpr(rd);
break;
case 0x07c: /* VIS I for */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_helper_0_0(helper_for);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x07d: /* VIS I fors */
+ CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_FT0(rs1);
gen_op_load_fpr_FT1(rs2);
tcg_gen_helper_0_0(helper_fors);
gen_op_store_FT0_fpr(rd);
break;
case 0x07e: /* VIS I fone */
+ CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_helper_0_0(helper_movl_DT0_1);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x07f: /* VIS I fones */
+ CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_helper_0_0(helper_movl_FT0_1);
gen_op_store_FT0_fpr(rd);
break;
if (rs2) {
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ } else
+ tcg_gen_mov_tl(cpu_dst, cpu_src1);
}
tcg_gen_helper_0_0(helper_restore);
gen_mov_pc_npc(dc, cpu_cond);
- tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
+ tcg_gen_helper_0_2(helper_check_align, cpu_dst,
+ tcg_const_i32(3));
tcg_gen_mov_tl(cpu_npc, cpu_dst);
dc->npc = DYNAMIC_PC;
goto jmp_insn;
if (rs2) {
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
- }
+ } else
+ tcg_gen_mov_tl(cpu_dst, cpu_src1);
}
switch (xop) {
case 0x38: /* jmpl */
{
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_tmp0, dc->pc);
- gen_movl_TN_reg(rd, cpu_tmp0);
- }
+ gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
gen_mov_pc_npc(dc, cpu_cond);
- tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
+ tcg_gen_helper_0_2(helper_check_align, cpu_dst,
+ tcg_const_i32(3));
tcg_gen_mov_tl(cpu_npc, cpu_dst);
dc->npc = DYNAMIC_PC;
}
if (!supervisor(dc))
goto priv_insn;
gen_mov_pc_npc(dc, cpu_cond);
- tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
+ tcg_gen_helper_0_2(helper_check_align, cpu_dst,
+ tcg_const_i32(3));
tcg_gen_mov_tl(cpu_npc, cpu_dst);
dc->npc = DYNAMIC_PC;
tcg_gen_helper_0_0(helper_rett);
goto jmp_insn;
#endif
case 0x3b: /* flush */
+ if (!((dc)->features & CPU_FEATURE_FLUSH))
+ goto unimp_flush;
tcg_gen_helper_0_1(helper_flush, cpu_dst);
break;
case 0x3c: /* save */
{
unsigned int xop = GET_FIELD(insn, 7, 12);
- save_state(dc, cpu_cond);
cpu_src1 = get_src1(insn, cpu_src1);
if (xop == 0x3c || xop == 0x3e)
{
if (rs2 != 0) {
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
- }
+ } else
+ tcg_gen_mov_tl(cpu_addr, cpu_src1);
}
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
(xop > 0x17 && xop <= 0x1d ) ||
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
switch (xop) {
case 0x0: /* load unsigned word */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
break;
tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x2: /* load unsigned halfword */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
break;
if (rd & 1)
goto illegal_insn;
else {
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ save_state(dc, cpu_cond);
+ tcg_gen_helper_0_2(helper_check_align, cpu_addr,
+ tcg_const_i32(7)); // XXX remove
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0xa: /* load signed halfword */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0xd: /* ldstub -- XXX: should be atomically */
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
- tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr,
+ dc->mem_idx);
break;
- case 0x0f: /* swap register with memory. Also atomically */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ case 0x0f: /* swap register with memory. Also
+ atomically */
+ CHECK_IU_FEATURE(dc, SWAP);
gen_movl_reg_TN(rd, cpu_val);
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
if (!supervisor(dc))
goto priv_insn;
#endif
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
break;
case 0x11: /* load unsigned byte alternate */
if (!supervisor(dc))
goto priv_insn;
#endif
+ save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
break;
case 0x12: /* load unsigned halfword alternate */
if (!supervisor(dc))
goto priv_insn;
#endif
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
+ save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
break;
case 0x13: /* load double word alternate */
#endif
if (rd & 1)
goto illegal_insn;
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ save_state(dc, cpu_cond);
gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
gen_movl_TN_reg(rd + 1, cpu_tmp0);
break;
if (!supervisor(dc))
goto priv_insn;
#endif
+ save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
break;
case 0x1a: /* load signed halfword alternate */
if (!supervisor(dc))
goto priv_insn;
#endif
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
+ save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
break;
case 0x1d: /* ldstuba -- XXX: should be atomically */
if (!supervisor(dc))
goto priv_insn;
#endif
+ save_state(dc, cpu_cond);
gen_ldstub_asi(cpu_val, cpu_addr, insn);
break;
- case 0x1f: /* swap reg with alt. memory. Also atomically */
+ case 0x1f: /* swap reg with alt. memory. Also
+ atomically */
+ CHECK_IU_FEATURE(dc, SWAP);
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
if (!supervisor(dc))
goto priv_insn;
#endif
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ save_state(dc, cpu_cond);
gen_movl_reg_TN(rd, cpu_val);
gen_swap_asi(cpu_val, cpu_addr, insn);
break;
#endif
#ifdef TARGET_SPARC64
case 0x08: /* V9 ldsw */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x0b: /* V9 ldx */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x18: /* V9 ldswa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
break;
case 0x1b: /* V9 ldxa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
break;
case 0x2d: /* V9 prefetch, no effect */
goto skip_move;
case 0x30: /* V9 ldfa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ save_state(dc, cpu_cond);
gen_ldf_asi(cpu_addr, insn, 4, rd);
goto skip_move;
case 0x33: /* V9 lddfa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ save_state(dc, cpu_cond);
gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
goto skip_move;
case 0x3d: /* V9 prefetcha, no effect */
goto skip_move;
case 0x32: /* V9 ldqfa */
-#if defined(CONFIG_USER_ONLY)
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ save_state(dc, cpu_cond);
gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
goto skip_move;
-#else
- goto nfpu_insn;
-#endif
#endif
default:
goto illegal_insn;
} else if (xop >= 0x20 && xop < 0x24) {
if (gen_trap_ifnofpu(dc, cpu_cond))
goto jmp_insn;
+ save_state(dc, cpu_cond);
switch (xop) {
case 0x20: /* load fpreg */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUState, fpr[rd]));
break;
case 0x21: /* load fsr */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ ABI32_MASK(cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUState, ft0));
tcg_gen_helper_0_0(helper_ldfsr);
break;
case 0x22: /* load quad fpreg */
-#if defined(CONFIG_USER_ONLY)
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
- gen_op_ldst(ldqf);
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ tcg_gen_helper_0_2(helper_ldqf, cpu_addr,
+ tcg_const_i32(dc->mem_idx));
gen_op_store_QT0_fpr(QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x23: /* load double fpreg */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
- gen_op_ldst(lddf);
+ tcg_gen_helper_0_2(helper_lddf, cpu_addr,
+ tcg_const_i32(dc->mem_idx));
gen_op_store_DT0_fpr(DFPREG(rd));
break;
default:
gen_movl_reg_TN(rd, cpu_val);
switch (xop) {
case 0x4: /* store word */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
break;
tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x6: /* store halfword */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x7: /* store double word */
if (rd & 1)
goto illegal_insn;
-#ifndef __i386__
else {
TCGv r_low;
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ save_state(dc, cpu_cond);
+ ABI32_MASK(cpu_addr);
+ tcg_gen_helper_0_2(helper_check_align, cpu_addr,
+ tcg_const_i32(7)); // XXX remove
r_low = tcg_temp_new(TCG_TYPE_I32);
gen_movl_reg_TN(rd + 1, r_low);
tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
r_low);
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
}
-#else /* __i386__ */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
- flush_cond(dc, cpu_cond);
- gen_movl_reg_TN(rd + 1, cpu_cond);
- gen_op_ldst(std);
-#endif /* __i386__ */
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x14: /* store word alternate */
if (!supervisor(dc))
goto priv_insn;
#endif
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 4);
break;
case 0x15: /* store byte alternate */
if (!supervisor(dc))
goto priv_insn;
#endif
+ save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 1);
break;
case 0x16: /* store halfword alternate */
if (!supervisor(dc))
goto priv_insn;
#endif
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
+ save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 2);
break;
case 0x17: /* store double word alternate */
if (rd & 1)
goto illegal_insn;
else {
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ save_state(dc, cpu_cond);
gen_stda_asi(cpu_val, cpu_addr, insn, rd);
}
break;
#endif
#ifdef TARGET_SPARC64
case 0x0e: /* V9 stx */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
ABI32_MASK(cpu_addr);
tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x1e: /* V9 stxa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 8);
break;
#endif
} else if (xop > 0x23 && xop < 0x28) {
if (gen_trap_ifnofpu(dc, cpu_cond))
goto jmp_insn;
+ save_state(dc, cpu_cond);
switch (xop) {
case 0x24: /* store fpreg */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
+ ABI32_MASK(cpu_addr);
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
offsetof(CPUState, fpr[rd]));
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
break;
case 0x25: /* stfsr, V9 stxfsr */
-#ifdef CONFIG_USER_ONLY
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
-#endif
+ ABI32_MASK(cpu_addr);
tcg_gen_helper_0_0(helper_stfsr);
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
offsetof(CPUState, ft0));
break;
case 0x26:
#ifdef TARGET_SPARC64
-#if defined(CONFIG_USER_ONLY)
/* V9 stqf, store quad fpreg */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rd));
- gen_op_ldst(stqf);
+ tcg_gen_helper_0_2(helper_stqf, cpu_addr, dc->mem_idx);
break;
-#else
- goto nfpu_insn;
-#endif
#else /* !TARGET_SPARC64 */
/* stdfq, store floating point queue */
#if defined(CONFIG_USER_ONLY)
goto nfq_insn;
#endif
#endif
- case 0x27:
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ case 0x27: /* store double fpreg */
gen_op_load_fpr_DT0(DFPREG(rd));
- gen_op_ldst(stdf);
+ tcg_gen_helper_0_2(helper_stdf, cpu_addr,
+ tcg_const_i32(dc->mem_idx));
break;
default:
goto illegal_insn;
}
} else if (xop > 0x33 && xop < 0x3f) {
+ save_state(dc, cpu_cond);
switch (xop) {
#ifdef TARGET_SPARC64
case 0x34: /* V9 stfa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
gen_op_load_fpr_FT0(rd);
gen_stf_asi(cpu_addr, insn, 4, rd);
break;
case 0x36: /* V9 stqfa */
-#if defined(CONFIG_USER_ONLY)
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ tcg_gen_helper_0_2(helper_check_align, cpu_addr,
+ tcg_const_i32(7));
gen_op_load_fpr_QT0(QFPREG(rd));
gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
break;
-#else
- goto nfpu_insn;
-#endif
case 0x37: /* V9 stdfa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
gen_op_load_fpr_DT0(DFPREG(rd));
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break;
case 0x3c: /* V9 casa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
gen_movl_TN_reg(rd, cpu_val);
break;
case 0x3e: /* V9 casxa */
- tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
gen_movl_TN_reg(rd, cpu_val);
break;
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
dc->is_br = 1;
return;
+ unimp_flush:
+ save_state(dc, cpu_cond);
+ tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_UNIMP_FLUSH));
+ dc->is_br = 1;
+ return;
#if !defined(CONFIG_USER_ONLY)
priv_insn:
save_state(dc, cpu_cond);
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
dc->is_br = 1;
return;
+#endif
nfpu_insn:
save_state(dc, cpu_cond);
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
dc->is_br = 1;
return;
-#ifndef TARGET_SPARC64
+#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
nfq_insn:
save_state(dc, cpu_cond);
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
dc->is_br = 1;
return;
#endif
-#endif
#ifndef TARGET_SPARC64
ncp_insn:
save_state(dc, cpu_cond);
last_pc = dc->pc;
dc->npc = (target_ulong) tb->cs_base;
dc->mem_idx = cpu_mmu_index(env);
- dc->fpu_enabled = cpu_fpu_enabled(env);
+ dc->features = env->features;
+ if ((dc->features & CPU_FEATURE_FLOAT)) {
+ dc->fpu_enabled = cpu_fpu_enabled(env);
+#if defined(CONFIG_USER_ONLY)
+ dc->features |= CPU_FEATURE_FLOAT128;
+#endif
+ } else
+ dc->fpu_enabled = 0;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
- cpu_cond = cpu_T[2];
-
do {
if (env->nb_breakpoints > 0) {
for(j = 0; j < env->nb_breakpoints; j++) {
cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
offsetof(CPUState, regwptr),
"regwptr");
- //#if TARGET_LONG_BITS > HOST_LONG_BITS
#ifdef TARGET_SPARC64
- cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
- TCG_AREG0, offsetof(CPUState, t0), "T0");
- cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
- TCG_AREG0, offsetof(CPUState, t1), "T1");
- cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
- TCG_AREG0, offsetof(CPUState, t2), "T2");
cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
TCG_AREG0, offsetof(CPUState, xcc),
"xcc");
-#else
- cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
- cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
- cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
#endif
+ /* XXX: T0 and T1 should be temporaries */
+ cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, t0), "T0");
+ cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, t1), "T1");
+ cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, cond),
+ "cond");
cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, cc_src),
"cc_src");
cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, gregs[i]),
gregnames[i]);
+ /* register helpers */
+
+#undef DEF_HELPER
+#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
+#include "helper.h"
+ }
+}
+
+void gen_pc_load(CPUState *env, TranslationBlock *tb,
+ unsigned long searched_pc, int pc_pos, void *puc)
+{
+ target_ulong npc;
+ env->pc = gen_opc_pc[pc_pos];
+ npc = gen_opc_npc[pc_pos];
+ if (npc == 1) {
+ /* dynamic NPC: already stored */
+ } else if (npc == 2) {
+ target_ulong t2 = (target_ulong)(unsigned long)puc;
+ /* jump PC: use T2 and the jump targets of the translation */
+ if (t2)
+ env->npc = gen_opc_jump_pc[0];
+ else
+ env->npc = gen_opc_jump_pc[1];
+ } else {
+ env->npc = npc;
}
}
projects / qemu.git / blobdiff