case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
s->ulpd_pm_regs[addr >> 2] = 0;
- qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
+ qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
return ret;
case 0x18: /* Reserved */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
- qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
+ qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
}
}
s->ulpd_pm_regs[addr >> 2] = value;
}
/* Dummy Traffic Controller's Memory Interface */
-static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t ret;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
}
static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
}
}
-static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_tcmi_read,
-};
-
-static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_tcmi_write,
+static const MemoryRegionOps omap_tcmi_ops = {
+ .read = omap_tcmi_read,
+ .write = omap_tcmi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(target_phys_addr_t base,
+static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
- omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
+ "omap-tcmi", 0x100);
+ memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
omap_tcmi_reset(mpu);
}
/* Digital phase-locked loops control */
-static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
if (addr == 0x00) /* CTL_REG */
return s->mode;
}
static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
uint16_t diff;
static const int bypass_div[4] = { 1, 2, 4, 4 };
int div, mult;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
if (addr == 0x00) { /* CTL_REG */
/* See omap_ulpd_pm_write() too */
diff = s->mode & value;
}
}
-static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
- omap_badwidth_read16,
- omap_dpll_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
- omap_badwidth_write16,
- omap_dpll_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_dpll_ops = {
+ .read = omap_dpll_read,
+ .write = omap_dpll_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_dpll_reset(struct dpll_ctl_s *s)
omap_clk_setrate(s->dpll, 1, 1);
}
-static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
- omap_clk clk)
+static void omap_dpll_init(MemoryRegion *memory, struct dpll_ctl_s *s,
+ target_phys_addr_t base, omap_clk clk)
{
- int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
- omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
s->dpll = clk;
omap_dpll_reset(s);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_add_subregion(memory, base, &s->iomem);
}
/* MPU Clock/Reset/Power Mode Control */
-static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* ARM_CKCTL */
return s->clkm.arm_ckctl;
}
static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
};
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* ARM_CKCTL */
diff = s->clkm.arm_ckctl ^ value;
}
}
-static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
- omap_badwidth_read16,
- omap_clkm_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
- omap_badwidth_write16,
- omap_clkm_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_clkm_ops = {
+ .read = omap_clkm_read,
+ .write = omap_clkm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
return s->clkm.dsp_idlect1;
}
static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
diff = s->clkm.dsp_idlect1 ^ value;
}
}
-static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
- omap_badwidth_read16,
- omap_clkdsp_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
- omap_badwidth_write16,
- omap_clkdsp_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_clkdsp_ops = {
+ .read = omap_clkdsp_read,
+ .write = omap_clkdsp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_clkm_reset(struct omap_mpu_state_s *s)
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(target_phys_addr_t mpu_base,
+static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
{
- int iomemtype[2] = {
- cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s,
- DEVICE_NATIVE_ENDIAN),
- cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s,
- DEVICE_NATIVE_ENDIAN),
- };
+ memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
+ "omap-clkm", 0x100);
+ memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s,
+ "omap-clkdsp", 0x1000);
s->clkm.arm_idlect1 = 0x03ff;
s->clkm.arm_idlect2 = 0x0100;
omap_clkm_reset(s);
s->clkm.cold_start = 0x3a;
- cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
- cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
+ memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
+ memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
}
/* MPU I/O */
qemu_irq *in;
qemu_irq handler[16];
qemu_irq wakeup;
+ MemoryRegion iomem;
uint16_t inputs;
uint16_t outputs;
s->row_latch = ~rows;
}
-static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* INPUT_LATCH */
return s->inputs;
}
static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (offset) {
case 0x04: /* OUTPUT_REG */
diff = (s->outputs ^ value) & ~s->dir;
}
}
-static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
- omap_badwidth_read16,
- omap_mpuio_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
- omap_badwidth_write16,
- omap_mpuio_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_mpuio_ops = {
+ .read = omap_mpuio_read,
+ .write = omap_mpuio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mpuio_reset(struct omap_mpuio_s *s)
omap_mpuio_kbd_update(s);
}
-struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
+struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
+ target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
- int iomemtype;
struct omap_mpuio_s *s = (struct omap_mpuio_s *)
g_malloc0(sizeof(struct omap_mpuio_s));
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
omap_mpuio_reset(s);
- iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
- omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mpuio_ops, s,
+ "omap-mpuio", 0x800);
+ memory_region_add_subregion(memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
/* MicroWire Interface */
struct omap_uwire_s {
+ MemoryRegion iomem;
qemu_irq txirq;
qemu_irq rxirq;
qemu_irq txdrq;
}
}
-static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* RDR */
s->control &= ~(1 << 15); /* RDRB */
}
static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* TDR */
s->txbuf = value; /* TD */
}
}
-static CPUReadMemoryFunc * const omap_uwire_readfn[] = {
- omap_badwidth_read16,
- omap_uwire_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_uwire_writefn[] = {
- omap_badwidth_write16,
- omap_uwire_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_uwire_ops = {
+ .read = omap_uwire_read,
+ .write = omap_uwire_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_uwire_reset(struct omap_uwire_s *s)
s->setup[4] = 0;
}
-struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
- qemu_irq *irq, qemu_irq dma, omap_clk clk)
+static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
+ qemu_irq txirq, qemu_irq rxirq,
+ qemu_irq dma,
+ omap_clk clk)
{
- int iomemtype;
struct omap_uwire_s *s = (struct omap_uwire_s *)
g_malloc0(sizeof(struct omap_uwire_s));
- s->txirq = irq[0];
- s->rxirq = irq[1];
+ s->txirq = txirq;
+ s->rxirq = rxirq;
s->txdrq = dma;
omap_uwire_reset(s);
- iomemtype = cpu_register_io_memory(omap_uwire_readfn,
- omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_uwire_ops, s, "omap-uwire", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
}
}
-static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* PWL_LEVEL */
return s->pwl.level;
}
static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* PWL_LEVEL */
s->pwl.level = value;
}
}
-static CPUReadMemoryFunc * const omap_pwl_readfn[] = {
- omap_pwl_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_pwl_writefn[] = {
- omap_pwl_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_pwl_ops = {
+ .read = omap_pwl_read,
+ .write = omap_pwl_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pwl_reset(struct omap_mpu_state_s *s)
omap_pwl_update(s);
}
-static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
+static void omap_pwl_init(MemoryRegion *system_memory,
+ target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_clk clk)
{
- int iomemtype;
-
omap_pwl_reset(s);
- iomemtype = cpu_register_io_memory(omap_pwl_readfn,
- omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->pwl_iomem, &omap_pwl_ops, s,
+ "omap-pwl", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->pwl_iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
}
/* Pulse-Width Tone module */
-static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* FRC */
return s->pwt.frc;
}
static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* FRC */
s->pwt.frc = value & 0x3f;
}
}
-static CPUReadMemoryFunc * const omap_pwt_readfn[] = {
- omap_pwt_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_pwt_writefn[] = {
- omap_pwt_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_pwt_ops = {
+ .read =omap_pwt_read,
+ .write = omap_pwt_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pwt_reset(struct omap_mpu_state_s *s)
s->pwt.gcr = 0;
}
-static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
+static void omap_pwt_init(MemoryRegion *system_memory,
+ target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_clk clk)
{
- int iomemtype;
-
s->pwt.clk = clk;
omap_pwt_reset(s);
- iomemtype = cpu_register_io_memory(omap_pwt_readfn,
- omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->pwt_iomem, &omap_pwt_ops, s,
+ "omap-pwt", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->pwt_iomem);
}
/* Real-time Clock module */
struct omap_rtc_s {
+ MemoryRegion iomem;
qemu_irq irq;
qemu_irq alarm;
QEMUTimer *clk;
printf("%s: conversion failed\n", __FUNCTION__);
}
-static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint8_t i;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* SECONDS_REG */
return to_bcd(s->current_tm.tm_sec);
}
static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
struct tm new_tm;
time_t ti[2];
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* SECONDS_REG */
#ifdef ALMDEBUG
}
}
-static CPUReadMemoryFunc * const omap_rtc_readfn[] = {
- omap_rtc_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_rtc_writefn[] = {
- omap_rtc_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_rtc_ops = {
+ .read = omap_rtc_read,
+ .write = omap_rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_rtc_tick(void *opaque)
omap_rtc_tick(s);
}
-static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
- qemu_irq *irq, omap_clk clk)
+static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
+ qemu_irq timerirq, qemu_irq alarmirq,
+ omap_clk clk)
{
- int iomemtype;
struct omap_rtc_s *s = (struct omap_rtc_s *)
g_malloc0(sizeof(struct omap_rtc_s));
- s->irq = irq[0];
- s->alarm = irq[1];
+ s->irq = timerirq;
+ s->alarm = alarmirq;
s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
omap_rtc_reset(s);
- iomemtype = cpu_register_io_memory(omap_rtc_readfn,
- omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_rtc_ops, s,
+ "omap-rtc", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
/* Multi-channel Buffered Serial Port interfaces */
struct omap_mcbsp_s {
+ MemoryRegion iomem;
qemu_irq txirq;
qemu_irq rxirq;
qemu_irq txdrq;
omap_mcbsp_rx_stop(s);
}
-static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* DRR2 */
if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
omap_badwidth_write16(opaque, addr, value);
}
-static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = {
- omap_badwidth_read16,
- omap_mcbsp_read,
- omap_badwidth_read16,
-};
+static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
+{
+ switch (size) {
+ case 2: return omap_mcbsp_writeh(opaque, addr, value);
+ case 4: return omap_mcbsp_writew(opaque, addr, value);
+ default: return omap_badwidth_write16(opaque, addr, value);
+ }
+}
-static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = {
- omap_badwidth_write16,
- omap_mcbsp_writeh,
- omap_mcbsp_writew,
+static const MemoryRegionOps omap_mcbsp_ops = {
+ .read = omap_mcbsp_read,
+ .write = omap_mcbsp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
qemu_del_timer(s->sink_timer);
}
-struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
- qemu_irq *irq, qemu_irq *dma, omap_clk clk)
+static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
+ qemu_irq txirq, qemu_irq rxirq,
+ qemu_irq *dma, omap_clk clk)
{
- int iomemtype;
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
g_malloc0(sizeof(struct omap_mcbsp_s));
- s->txirq = irq[0];
- s->rxirq = irq[1];
+ s->txirq = txirq;
+ s->rxirq = rxirq;
s->txdrq = dma[0];
s->rxdrq = dma[1];
s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s);
- iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
- omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
/* LED Pulse Generators */
struct omap_lpg_s {
+ MemoryRegion iomem;
QEMUTimer *tm;
uint8_t control;
omap_lpg_update(s);
}
-static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* LCR */
return s->control;
}
static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* LCR */
if (~value & (1 << 6)) /* LPGRES */
}
}
-static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
- omap_lpg_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
- omap_lpg_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_lpg_ops = {
+ .read = omap_lpg_read,
+ .write = omap_lpg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_lpg_clk_update(void *opaque, int line, int on)
omap_lpg_update(s);
}
-static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
+static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
+ target_phys_addr_t base, omap_clk clk)
{
- int iomemtype;
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
omap_lpg_reset(s);
- iomemtype = cpu_register_io_memory(omap_lpg_readfn,
- omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
}
/* MPUI Peripheral Bridge configuration */
-static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
if (addr == OMAP_MPUI_BASE) /* CMR */
return 0xfe4d;
return 0;
}
-static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
- omap_badwidth_read16,
- omap_mpui_io_read,
- omap_badwidth_read16,
-};
+static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
+{
+ /* FIXME: infinite loop */
+ omap_badwidth_write16(opaque, addr, value);
+}
-static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
- omap_badwidth_write16,
- omap_badwidth_write16,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_mpui_io_ops = {
+ .read = omap_mpui_io_read,
+ .write = omap_mpui_io_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
+static void omap_setup_mpui_io(MemoryRegion *system_memory,
+ struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
- omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
+ memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu,
+ "omap-mpui-io", 0x7fff);
+ memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
+ &mpu->mpui_io_iomem);
}
/* General chip reset */
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
- omap_inth_reset(mpu->ih[0]);
- omap_inth_reset(mpu->ih[1]);
omap_dma_reset(mpu->dma);
omap_mpu_timer_reset(mpu->timer[0]);
omap_mpu_timer_reset(mpu->timer[1]);
{ 0 }
};
-static void omap_setup_dsp_mapping(const struct omap_map_s *map)
+static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
+ const struct omap_map_s *map)
{
- int io;
+ MemoryRegion *io;
for (; map->phys_dsp; map ++) {
- io = cpu_get_physical_page_desc(map->phys_mpu);
-
- cpu_register_physical_memory(map->phys_dsp, map->size, io);
+ io = g_new(MemoryRegion, 1);
+ memory_region_init_alias(io, map->name,
+ system_memory, map->phys_mpu, map->size);
+ memory_region_add_subregion(system_memory, map->phys_dsp, io);
}
}
int i;
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
g_malloc0(sizeof(struct omap_mpu_state_s));
- ram_addr_t imif_base, emiff_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
+ SysBusDevice *busdev;
if (!core)
core = "ti925t";
omap_clk_init(s);
/* Memory-mapped stuff */
- cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
- (emiff_base = qemu_ram_alloc(NULL, "omap1.dram",
- s->sdram_size)) | IO_MEM_RAM);
- cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
- (imif_base = qemu_ram_alloc(NULL, "omap1.sram",
- s->sram_size)) | IO_MEM_RAM);
+ memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size);
+ memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
+ memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size);
+ memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
- omap_clkm_init(0xfffece00, 0xe1008000, s);
+ omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
cpu_irq = arm_pic_init_cpu(s->env);
- s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
- cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
- omap_findclk(s, "arminth_ck"));
- s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
- omap_inth_get_pin(s->ih[0], OMAP_INT_15XX_IH2_IRQ),
- NULL, omap_findclk(s, "arminth_ck"));
-
- for (i = 0; i < 6; i ++)
- dma_irqs[i] =
- s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
- s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
+ s->ih[0] = qdev_create(NULL, "omap-intc");
+ qdev_prop_set_uint32(s->ih[0], "size", 0x100);
+ qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
+ qdev_init_nofail(s->ih[0]);
+ busdev = sysbus_from_qdev(s->ih[0]);
+ sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
+ sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
+ sysbus_mmio_map(busdev, 0, 0xfffecb00);
+ s->ih[1] = qdev_create(NULL, "omap-intc");
+ qdev_prop_set_uint32(s->ih[1], "size", 0x800);
+ qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck"));
+ qdev_init_nofail(s->ih[1]);
+ busdev = sysbus_from_qdev(s->ih[1]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
+ /* The second interrupt controller's FIQ output is not wired up */
+ sysbus_mmio_map(busdev, 0, 0xfffe0000);
+
+ for (i = 0; i < 6; i++) {
+ dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
+ omap1_dma_irq_map[i].intr);
+ }
+ s->dma = omap_dma_init(0xfffed800, dma_irqs,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
s->port[emiff ].addr_valid = omap_validate_emiff_addr;
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
/* Register SDRAM and SRAM DMA ports for fast transfers. */
- soc_dma_port_add_mem_ram(s->dma,
- emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
- soc_dma_port_add_mem_ram(s->dma,
- imif_base, OMAP_IMIF_BASE, s->sram_size);
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram),
+ OMAP_EMIFF_BASE, s->sdram_size);
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
+ OMAP_IMIF_BASE, s->sram_size);
s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
- s->irq[0][OMAP_INT_TIMER1],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
omap_findclk(s, "mputim_ck"));
s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
- s->irq[0][OMAP_INT_TIMER2],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
omap_findclk(s, "mputim_ck"));
s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
- s->irq[0][OMAP_INT_TIMER3],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
omap_findclk(s, "mputim_ck"));
s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
- s->irq[0][OMAP_INT_WD_TIMER],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
omap_findclk(s, "armwdt_ck"));
s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
- s->irq[1][OMAP_INT_OS_TIMER],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
omap_findclk(s, "clk32-kHz"));
- s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
- omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
- omap_findclk(s, "lcd_ck"));
+ s->lcd = omap_lcdc_init(0xfffec000,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
+ omap_dma_get_lcdch(s->dma),
+ omap_findclk(s, "lcd_ck"));
omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
omap_pin_cfg_init(system_memory, 0xfffe1000, s);
omap_mpui_init(system_memory, 0xfffec900, s);
s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
- s->irq[0][OMAP_INT_BRIDGE_PRIV],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
omap_findclk(s, "tipb_ck"));
s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
- s->irq[0][OMAP_INT_BRIDGE_PUB],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
omap_findclk(s, "tipb_ck"));
- omap_tcmi_init(0xfffecc00, s);
+ omap_tcmi_init(system_memory, 0xfffecc00, s);
- s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
+ s->uart[0] = omap_uart_init(0xfffb0000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
omap_findclk(s, "uart1_ck"),
omap_findclk(s, "uart1_ck"),
s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
"uart1",
serial_hds[0]);
- s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
+ s->uart[1] = omap_uart_init(0xfffb0800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
omap_findclk(s, "uart2_ck"),
omap_findclk(s, "uart2_ck"),
s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
"uart2",
serial_hds[0] ? serial_hds[1] : NULL);
- s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],
+ s->uart[2] = omap_uart_init(0xfffb9800,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
omap_findclk(s, "uart3_ck"),
omap_findclk(s, "uart3_ck"),
s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
"uart3",
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
- omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
- omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
- omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
+ omap_dpll_init(system_memory,
+ &s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
+ omap_dpll_init(system_memory,
+ &s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
+ omap_dpll_init(system_memory,
+ &s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
dinfo = drive_get(IF_SD, 0, 0);
if (!dinfo) {
exit(1);
}
s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
- s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
+ &s->drq[OMAP_DMA_MMC_TX],
omap_findclk(s, "mmc_ck"));
- s->mpuio = omap_mpuio_init(0xfffb5000,
- s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
- s->wakeup, omap_findclk(s, "clk32-kHz"));
+ s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
+ s->wakeup, omap_findclk(s, "clk32-kHz"));
s->gpio = qdev_create(NULL, "omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
+ qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck"));
qdev_init_nofail(s->gpio);
sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
- s->irq[0][OMAP_INT_GPIO_BANK1]);
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000);
- s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
+ s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
- omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
- omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
+ omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck"));
+ omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck"));
- s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
+ s->i2c[0] = omap_i2c_init(0xfffb3800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
- s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
+ s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
omap_findclk(s, "clk32-kHz"));
- s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
+ s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
&s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
- s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
+ s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_310_McBSP2_TX),
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_310_McBSP2_RX),
&s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
- s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
+ s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
&s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
- s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
- s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
+ s->led[0] = omap_lpg_init(system_memory,
+ 0xfffbd000, omap_findclk(s, "clk32-kHz"));
+ s->led[1] = omap_lpg_init(system_memory,
+ 0xfffbd800, omap_findclk(s, "clk32-kHz"));
/* Register mappings not currenlty implemented:
* MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
* DSP MMU fffed200 - fffed2ff
*/
- omap_setup_dsp_mapping(omap15xx_dsp_mm);
- omap_setup_mpui_io(s);
+ omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm);
+ omap_setup_mpui_io(system_memory, s);
qemu_register_reset(omap1_mpu_reset, s);
projects / qemu.git / blobdiff