#ifndef CPU_MICROBLAZE_H
#define CPU_MICROBLAZE_H
+#include "config.h"
+#include "qemu-common.h"
+
#define TARGET_LONG_BITS 32
-#define CPUState struct CPUMBState
+#define CPUArchState struct CPUMBState
-#include "cpu-defs.h"
+#include "exec/cpu-defs.h"
+#include "fpu/softfloat.h"
struct CPUMBState;
+typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
#define TARGET_HAS_ICE 1
-#define ELF_MACHINE EM_XILINX_MICROBLAZE
+#define ELF_MACHINE EM_MICROBLAZE
#define EXCP_NMI 1
#define EXCP_MMU 2
#define EXCP_HW_BREAK 5
#define EXCP_HW_EXCP 6
+/* MicroBlaze-specific interrupt pending bits. */
+#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
+
/* Register aliases. R0 - R15 */
#define R_SP 1
#define SR_PC 0
#define MSR_DCE (1<<7) /* 0x080 */
#define MSR_EE (1<<8) /* 0x100 */
#define MSR_EIP (1<<9) /* 0x200 */
+#define MSR_PVR (1<<10) /* 0x400 */
#define MSR_CC (1<<31)
/* Machine State Register (MSR) Fields */
#define ESR_DIZ (1<<11) /* Zone Protection */
#define ESR_S (1<<10) /* Store instruction */
+#define ESR_ESS_FSL_OFFSET 5
+
#define ESR_EC_FSL 0
#define ESR_EC_UNALIGNED_DATA 1
#define ESR_EC_ILLEGAL_OP 2
#define ESR_EC_DIVZERO 5
#define ESR_EC_FPU 6
#define ESR_EC_PRIVINSN 7
+#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
#define ESR_EC_DATA_STORAGE 8
#define ESR_EC_INSN_STORAGE 9
#define ESR_EC_DATA_TLB 10
#define ESR_EC_INSN_TLB 11
+#define ESR_EC_MASK 31
+
+/* Floating Point Status Register (FSR) Bits */
+#define FSR_IO (1<<4) /* Invalid operation */
+#define FSR_DZ (1<<3) /* Divide-by-zero */
+#define FSR_OF (1<<2) /* Overflow */
+#define FSR_UF (1<<1) /* Underflow */
+#define FSR_DO (1<<0) /* Denormalized operand error */
/* Version reg. */
/* Basic PVR mask */
#define PVR0_USE_ICACHE_MASK 0x02000000
#define PVR0_USE_DCACHE_MASK 0x01000000
#define PVR0_USE_MMU 0x00800000 /* new */
+#define PVR0_USE_BTC 0x00400000
+#define PVR0_ENDI 0x00200000
+#define PVR0_FAULT 0x00100000
#define PVR0_VERSION_MASK 0x0000FF00
#define PVR0_USER1_MASK 0x000000FF
#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
+#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
/* ICache base address PVR mask */
#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
#define PVR11_MMU_ITLB_SIZE 0x38000000
#define PVR11_MMU_DTLB_SIZE 0x07000000
#define PVR11_MMU_TLB_ACCESS 0x00C00000
-#define PVR11_MMU_ZONES 0x003C0000
+#define PVR11_MMU_ZONES 0x003E0000
/* MSR Reset value PVR mask */
#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
#define CC_EQ 0
#define NB_MMU_MODES 3
-typedef struct CPUMBState {
+
+#define STREAM_EXCEPTION (1 << 0)
+#define STREAM_ATOMIC (1 << 1)
+#define STREAM_TEST (1 << 2)
+#define STREAM_CONTROL (1 << 3)
+#define STREAM_NONBLOCK (1 << 4)
+
+struct CPUMBState {
uint32_t debug;
uint32_t btaken;
uint32_t btarget;
uint32_t imm;
uint32_t regs[33];
uint32_t sregs[24];
+ float_status fp_status;
+ /* Stack protectors. Yes, it's a hw feature. */
+ uint32_t slr, shr;
+
+ /* lwx/swx reserved address */
+#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
+ uint32_t res_addr;
/* Internal flags. */
#define IMM_FLAG 4
#define DRTE_FLAG (1 << 17)
#define DRTB_FLAG (1 << 18)
#define D_FLAG (1 << 19) /* Bit in ESR. */
-/* TB dependant CPUState. */
-#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG \
- | DRTE_FLAG | DRTB_FLAG | MSR_EE_FLAG)
+/* TB dependent CPUMBState. */
+#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
uint32_t iflags;
struct {
#endif
CPU_COMMON
-} CPUMBState;
+};
+
+#include "cpu-qom.h"
-CPUState *cpu_mb_init(const char *cpu_model);
-int cpu_mb_exec(CPUState *s);
-void cpu_mb_close(CPUState *s);
-void do_interrupt(CPUState *env);
+MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
+int cpu_mb_exec(CPUMBState *s);
+void cpu_mb_close(CPUMBState *s);
+void do_interrupt(CPUMBState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define cpu_init cpu_mb_init
+static inline CPUMBState *cpu_init(const char *cpu_model)
+{
+ MicroBlazeCPU *cpu = cpu_mb_init(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ return &cpu->env;
+}
+
#define cpu_exec cpu_mb_exec
#define cpu_gen_code cpu_mb_gen_code
#define cpu_signal_handler cpu_mb_signal_handler
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUMBState *env)
{
/* Are we in nommu mode?. */
if (!(env->sregs[SR_MSR] & MSR_VM))
return MMU_KERNEL_IDX;
}
-int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUMBState *env, target_ulong newsp)
{
if (newsp)
env->regs[R_SP] = newsp;
}
#endif
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPUMBState *env, target_ulong newtls)
{
+ env->regs[21] = newtls;
}
-static inline int cpu_interrupts_enabled(CPUState *env)
+static inline int cpu_interrupts_enabled(CPUMBState *env)
{
return env->sregs[SR_MSR] & MSR_IE;
}
-#include "cpu-all.h"
-#include "exec-all.h"
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->sregs[SR_PC] = tb->pc;
-}
+#include "exec/cpu-all.h"
-static inline target_ulong cpu_get_pc(CPUState *env)
+static inline target_ulong cpu_get_pc(CPUMBState *env)
{
return env->sregs[SR_PC];
}
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->sregs[SR_PC];
*cs_base = 0;
- env->iflags |= env->sregs[SR_MSR] & MSR_EE;
- *flags = env->iflags & IFLAGS_TB_MASK;
+ *flags = (env->iflags & IFLAGS_TB_MASK) |
+ (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
}
#if !defined(CONFIG_USER_ONLY)
-void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi, int size);
+void cpu_unassigned_access(CPUMBState *env1, hwaddr addr,
+ int is_write, int is_exec, int is_asi, int size);
#endif
+
+static inline bool cpu_has_work(CPUState *cpu)
+{
+ CPUMBState *env = &MICROBLAZE_CPU(cpu)->env;
+
+ return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec/exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUMBState *env, TranslationBlock *tb)
+{
+ env->sregs[SR_PC] = tb->pc;
+}
+
#endif
projects / qemu.git / blobdiff