#define MAX_PILS 16
+#define TICK_INT_DIS 0x8000000000000000ULL
+#define TICK_MAX 0x7fffffffffffffffULL
+
struct hwdef {
const char * const default_cpu_model;
uint16_t machine_id;
{
}
-static int nvram_boot_set(void *opaque, const char *boot_device)
+static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
- unsigned int i;
- uint8_t image[sizeof(ohwcfg_v3_t)];
- ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
- m48t59_t *nvram = (m48t59_t *)opaque;
-
- for (i = 0; i < sizeof(image); i++)
- image[i] = m48t59_read(nvram, i) & 0xff;
-
- pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
- boot_device);
- header->nboot_devices = strlen(boot_device) & 0xff;
- header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
-
- for (i = 0; i < sizeof(image); i++)
- m48t59_write(nvram, i, image[i]);
-
+ fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
return 0;
}
unsigned int i;
uint32_t start, end;
uint8_t image[0x1ff0];
- ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
- struct sparc_arch_cfg *sparc_header;
struct OpenBIOS_nvpart_v1 *part_header;
memset(image, '\0', sizeof(image));
- // Try to match PPC NVRAM
- pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
- "QEMU_BIOS");
- header->struct_version = cpu_to_be32(3); /* structure v3 */
-
- header->nvram_size = cpu_to_be16(NVRAM_size);
- header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
- header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
- pstrcpy((char *)header->arch, sizeof(header->arch), arch);
- header->nb_cpus = smp_cpus & 0xff;
- header->RAM0_base = 0;
- header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
- pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
- boot_devices);
- header->nboot_devices = strlen(boot_devices) & 0xff;
- header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
- header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
- if (cmdline) {
- pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
- header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
- header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
- }
- header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
- header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
- header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
-
- header->width = cpu_to_be16(width);
- header->height = cpu_to_be16(height);
- header->depth = cpu_to_be16(depth);
- if (nographic)
- header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
-
- header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
-
- // Architecture specific header
- start = sizeof(ohwcfg_v3_t);
- sparc_header = (struct sparc_arch_cfg *)&image[start];
- sparc_header->valid = 0;
- start += sizeof(struct sparc_arch_cfg);
+ start = 0;
// OpenBIOS nvram variables
// Variable partition
for (i = 0; i < sizeof(image); i++)
m48t59_write(nvram, i, image[i]);
- qemu_register_boot_set(nvram_boot_set, nvram);
-
return 0;
}
-void pic_info(void)
+void pic_info(Monitor *mon)
{
}
-void irq_info(void)
+void irq_info(Monitor *mon)
{
}
CPUState *env = s->env;
cpu_reset(env);
- ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
- ptimer_run(env->tick, 0);
- ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
- ptimer_run(env->stick, 0);
- ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
- ptimer_run(env->hstick, 0);
+ env->tick_cmpr = TICK_INT_DIS | 0;
+ ptimer_set_limit(env->tick, TICK_MAX, 1);
+ ptimer_run(env->tick, 1);
+ env->stick_cmpr = TICK_INT_DIS | 0;
+ ptimer_set_limit(env->stick, TICK_MAX, 1);
+ ptimer_run(env->stick, 1);
+ env->hstick_cmpr = TICK_INT_DIS | 0;
+ ptimer_set_limit(env->hstick, TICK_MAX, 1);
+ ptimer_run(env->hstick, 1);
env->gregs[1] = 0; // Memory start
env->gregs[2] = ram_size; // Memory size
env->gregs[3] = 0; // Machine description XXX
{
CPUState *env = opaque;
- env->softint |= SOFTINT_TIMER;
- cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ if (!(env->tick_cmpr & TICK_INT_DIS)) {
+ env->softint |= SOFTINT_TIMER;
+ cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ }
}
static void stick_irq(void *opaque)
{
CPUState *env = opaque;
- env->softint |= SOFTINT_TIMER;
- cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ if (!(env->stick_cmpr & TICK_INT_DIS)) {
+ env->softint |= SOFTINT_STIMER;
+ cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ }
}
static void hstick_irq(void *opaque)
{
CPUState *env = opaque;
- env->softint |= SOFTINT_TIMER;
- cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ if (!(env->hstick_cmpr & TICK_INT_DIS)) {
+ cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ }
}
void cpu_tick_set_count(void *opaque, uint64_t count)
static fdctrl_t *floppy_controller;
+static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
+ uint32_t addr, uint32_t size, int type)
+{
+ DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
+ switch (region_num) {
+ case 0:
+ isa_mmio_init(addr, 0x1000000);
+ break;
+ case 1:
+ isa_mmio_init(addr, 0x800000);
+ break;
+ }
+}
+
+/* EBUS (Eight bit bus) bridge */
+static void
+pci_ebus_init(PCIBus *bus, int devfn)
+{
+ PCIDevice *s;
+
+ s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL);
+ pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
+ pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
+ s->config[0x04] = 0x06; // command = bus master, pci mem
+ s->config[0x05] = 0x00;
+ s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
+ s->config[0x07] = 0x03; // status = medium devsel
+ s->config[0x08] = 0x01; // revision
+ s->config[0x09] = 0x00; // programming i/f
+ pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
+ s->config[0x0D] = 0x0a; // latency_timer
+ s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+ pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
+ ebus_mmio_mapfunc);
+ pci_register_io_region(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM,
+ ebus_mmio_mapfunc);
+}
+
static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
const struct hwdef *hwdef)
m48t59_t *nvram;
int ret, linux_boot;
unsigned int i;
- long prom_offset, initrd_size, kernel_size;
- PCIBus *pci_bus;
+ ram_addr_t ram_offset, prom_offset;
+ long initrd_size, kernel_size;
+ PCIBus *pci_bus, *pci_bus2, *pci_bus3;
QEMUBH *bh;
qemu_irq *irq;
int drive_index;
env->npc = env->pc + 4;
/* allocate RAM */
- cpu_register_physical_memory(0, RAM_size, 0);
+ ram_offset = qemu_ram_alloc(RAM_size);
+ cpu_register_physical_memory(0, RAM_size, ram_offset);
- prom_offset = RAM_size + vga_ram_size;
+ prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
cpu_register_physical_memory(hwdef->prom_addr,
(PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
TARGET_PAGE_MASK,
}
}
}
- pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
+ pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
+ &pci_bus3);
isa_mem_base = VGA_BASE;
- pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
- vga_ram_size);
+ pci_vga_init(pci_bus, vga_ram_size, 0, 0);
+
+ // XXX Should be pci_bus3
+ pci_ebus_init(pci_bus, -1);
i = 0;
if (hwdef->console_serial_base) {
}
}
- for(i = 0; i < nb_nics; i++) {
- if (!nd_table[i].model)
- nd_table[i].model = "ne2k_pci";
- pci_nic_init(pci_bus, &nd_table[i], -1);
- }
+ for(i = 0; i < nb_nics; i++)
+ pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
hd[i] = NULL;
}
- // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
- pci_piix3_ide_init(pci_bus, hd, -1, irq);
+ pci_cmd646_ide_init(pci_bus, hd, 1);
+
/* FIXME: wire up interrupts. */
i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
for(i = 0; i < MAX_FD; i++) {
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ if (kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
enum {
/* Sun4u hardware initialisation */
static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
+ sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
}
/* Sun4v hardware initialisation */
static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
+ sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
}
/* Niagara hardware initialisation */
static void niagara_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
+ sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
}
.name = "sun4u",
.desc = "Sun4u platform",
.init = sun4u_init,
- .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
- .nodisk_ok = 1,
- .max_cpus = 16,
+ .max_cpus = 1, // XXX for now
};
QEMUMachine sun4v_machine = {
.name = "sun4v",
.desc = "Sun4v platform",
.init = sun4v_init,
- .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
- .nodisk_ok = 1,
- .max_cpus = 16,
+ .max_cpus = 1, // XXX for now
};
QEMUMachine niagara_machine = {
.name = "Niagara",
.desc = "Sun4v platform, Niagara",
.init = niagara_init,
- .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
- .nodisk_ok = 1,
- .max_cpus = 16,
+ .max_cpus = 1, // XXX for now
};
projects / qemu.git / blobdiff